數(shù)字系統(tǒng)設計課件lect1312編程器件

1、1Winter 2009 ZDMC Lec. #1 1Digital System Design I數(shù)字系統(tǒng)設計 1Weidong Wang (王維東) Dept. of Information Science & Electronic EngineeringISEEZhejiang University-編程器件2Winter 2009 ZDMC Lec. #1 2任課教師王維東 浙江大學信息與電子工程學系, 信電樓306Zhejiang UniversityDepartment of Information Science and Electronic EngineeringHangzho

2、u, 310027Tel: 86-571-87953170 (O)TA:聶濤： ; Office Hours;Xindian (High-Tech) Building 308.3Winter 2009 ZDMC Lec. #1 3課程簡介參考書閻石, 數(shù)字電子技術基礎,第5版, 高等教育出版社, 2006.R.H.Katz, G.Borriello, Contemporary Logic Design, second edition,電子工業(yè)出版社, 2005.M.M.Mano, 數(shù)字設計(第四版), 電子工業(yè)出版社, 2010.補充材料，見8/數(shù)字電路教學/2012 教學工作/考核平時30%

3、(作業(yè),上課,期中考試或平時測驗)期末考試70%答疑信電樓308房間/周二下午3:00-4:30課間email4Winter 2009 ZDMC Lec. #1 4存儲器復習隨機存取存儲器（RAM）在計算機及數(shù)據(jù)處理系統(tǒng)中需要存放大量數(shù)據(jù)、中間結果、表格等設備，這就是隨機存取存儲器SRAM。RAM可分為單極型和雙極型：雙極型工作速率高，但是集成度不如單極型的高，目前，由于工藝水平的不斷提高，單極型RAM的速率已經(jīng)可以和雙極型RAM相比，而且單極型RAM具有功耗低的優(yōu)點。單極型RAM又可分為靜態(tài)SRAM與動態(tài)DRAM：靜態(tài)RAM是用MOS管觸發(fā)器來存儲代碼，所用MOS管較多、集成度低、功耗也較大

4、。動態(tài)RAM是用柵極分布電容保存信息，它的存儲單元所需要的MOS管較少，因此集成度高、功耗也小。靜態(tài)RAM使用方便，不需要刷新。5Winter 2009 ZDMC Lec. #1 5SRAM結構一、外部特性二、內(nèi)部組織地址譯碼器分行譯碼器和列譯碼器，只有行及列共同選中的單元才能進行讀、寫。這種尋址的方式所需要行線和列線的總數(shù)較少。- 例如要存儲256字1位的容量，采用一元尋址就需要256條字線，若采用二元尋址只需A=16，B=16，共32條線也就可以了。6Winter 2009 ZDMC Lec. #1 6SRAM的存儲單元 RAM中的存儲單元可由雙極型管組成，也可由MOS管組成。7Winte

5、r 2009 ZDMC Lec. #1 7動態(tài)隨機存儲器（DRAM）動態(tài)存儲單元是利用MOS管柵極電容可以存儲電荷的原理柵極電容保留信息只有一段時間，需定期地給它刷新，以免信息丟失，所以在每一行上設有刷新電路。8Winter 2009 ZDMC Lec. #1 8（二）動態(tài)MOS存儲單元如下圖這是一動態(tài)存儲單元，靠柵極電容C1及C2存儲電荷。如要寫入“1”，只需在數(shù)據(jù)線D上作用“1”便可以給C2充上足夠的電荷，而C1則不被充電，表示記入了“1”當刷新端加高電壓時，負載管T3、T4導通，同時行線加高電壓使T6、T5也導通，構成R-S觸發(fā)器，觸發(fā)器的狀態(tài)由C1及C2中的電壓決定柵極電容保留信息只有

6、一段時間，需定期地給它刷新，以免信息丟失，所以在每一行上設有刷新電路。當X、Y線均為高電平時，T5、T6、T7及T8都導通，此單元接至數(shù)據(jù)線，9Winter 2009 ZDMC Lec. #1 9RAM的擴展當使用一片RAM器件不能滿足存儲量的需要時，可以將若干片RAM組合到一起，接成一個容量更大的RAM。位擴展方式將各片的地址線、讀寫線、片選線并聯(lián)即可字擴展方式/地址擴展方式RAM的片選信號用譯碼器實現(xiàn)，每一片RAM的數(shù)據(jù)端I/O1I/O8都有三態(tài)緩沖器，而它們的片選信號又不會同時出現(xiàn)低電平，可將它們的數(shù)據(jù)端并聯(lián)起來，作為整個RAM的八位數(shù)據(jù)輸入/輸出端。先進行位位擴展，再進行字擴展10Wi

7、nter 2009 ZDMC Lec. #1 10Typical SRAM TimingWrite Timing:DRead Timing:WE_LAWriteHold TimeWrite Setup TimeADOE_L2Nwordsx M bitSRAMNMWE_LData InWrite AddressOE_LHigh ZRead AddressJunkRead AccessTimeData OutRead AccessTimeData OutRead AddressOE determines direction Hi = Write, Lo = ReadWrites are dange

8、rous! Be careful! Double signaling: OE Hi, WE Lo11Winter 2009 ZDMC Lec. #1 11存儲器的HDL描述1024個字的存儲器，每個字是16位reg 15:0 memword 0:1023;module memory (Enable, ReadWrite, Address, DataIn, DataOut); input Enable, ReadWrite; input 3:0 DataIn; input 5:0 Address; output 3:0 DataOut; reg 3:0 DataOut; reg 3:0 Mem

9、0:63 /64x4 memory always (Enable or ReadWrite) if (Enable) if (ReadWrite) DataOut = MemAddress; /Read else MemAddress = DataIn; /Write else DataOut= 4bz /High impedance stateendmodule 12Winter 2009 ZDMC Lec. #1 12第八章 可編程邏輯器件13Winter 2009 ZDMC Lec. #1 13第八章 可編程邏輯器件（PLD, Programmable Logic Device）8.1

10、概述一、PLD的基本特點1. 數(shù)字集成電路從功能上有分為通用型、專用型兩大類2. PLD的特點：是一種按通用器件來生產(chǎn)，但邏輯功能是由用戶通過對器件編程來設定的數(shù)字系統(tǒng)14Winter 2009 ZDMC Lec. #1 14Programmable LogicRegular logicProgrammable Logic ArraysMultiplexers/DecodersROMsField Programmable Gate ArraysXilinx Vertex“Random Logic”Full Custom Design“Regular Logic”Structured Desig

11、n15Winter 2009 ZDMC Lec. #1 15二、PLD的發(fā)展和分類PROM是最早的PLDPAL 可編程邏輯陣列FPLA 現(xiàn)場可編程陣列邏輯GAL 通用陣列邏輯EPLD 可擦除的可編程邏輯器件FPGA 現(xiàn)場可編程門陣列ISP-PLD 在系統(tǒng)可編程的PLD16Winter 2009 ZDMC Lec. #1 16三、LSI中用的邏輯圖符號17Winter 2009 ZDMC Lec. #1 178.2 現(xiàn)場可編程邏輯陣列 FPLA組合電路和時序電路結構的通用形式1970s邏輯函數(shù)與或表達式與邏輯+或邏輯最小項之和部分最小項與EPROM很相似時序型FPLAA0An-1W0W(2n-1

12、)D0Dm18Winter 2009 ZDMC Lec. #1 188.2 FPLA結構組合電路和時序電路結構的通用形式19Winter 2009 ZDMC Lec. #1 198.3 PAL（Programmable Array Logic）8.3.1 PAL的基本電路結構，1970s，曾大規(guī)模應用，采用雙極型熔絲工藝，工作速度較高。一、基本結構形式可編程“與”陣列+固定“或”陣列+輸出電路最簡單的形式為：二、編程單元出廠時，所有的交叉點均有熔絲三、輸出有限、減少單元數(shù)20Winter 2009 ZDMC Lec. #1 208.3.2 PAL的輸出電路結構和反饋形式PAL器件的輸入、輸出結

13、構以及輸入、輸出的數(shù)目是由集成電路制造商根據(jù)實際設計情況大致估計確定。一. 專用輸出結構用途：產(chǎn)生組合邏輯電路21Winter 2009 ZDMC Lec. #1 21二. 可編程輸入/輸出結構用途：組合邏輯電路，有三態(tài)控制可實現(xiàn)總線連接可將輸出作輸入用當最上面的乘積項為高電平時，三態(tài)門開通，I/O可作為輸出或反饋；乘積項為低電平時，三態(tài)門關斷，是輸入。22Winter 2009 ZDMC Lec. #1 22三. 寄存器輸出結構、時序結構用途：產(chǎn)生時序邏輯電路或門的輸出通過D觸發(fā)器，在CP的上升沿時到達輸出。觸發(fā)器的Q端可以通過三態(tài)緩沖器送到輸出引腳觸發(fā)器的反相端反饋回與陣列，作為輸入信號參

14、與更復雜的時序邏輯運算23Winter 2009 ZDMC Lec. #1 23四. 帶異或輸出結構時序邏輯電路還可便于對“與-或”輸出求反兩個和項在觸發(fā)器的輸入端異或之后，在時鐘上升沿到來時存入觸發(fā)器內(nèi)把乘積項分割成兩個和項24Winter 2009 ZDMC Lec. #1 24五. 運算反饋結構時序邏輯電路可產(chǎn)生A、B的十六種算術、邏輯運算由8個寄存器型輸出結構組成的PAL器件命名為PAL16R8，由8個可編程I/O結構組成的PAL器件則命名為PAL16L8。25Winter 2009 ZDMC Lec. #1 25ROM vs. PLAROMDesign time is short (

15、no need to minimize output functions)Most input combinations are needed (e.g., code converters)Little sharing of product terms among output functionsSize doubles for each additional inputCant exploit dont caresCheap (high-volume component)Can implement any function of n inputsMedium speedPLA Design

16、tools are available for multi-output minimizationThere are relatively few unique minterm combinationsMany minterms are shared among the output functionsMost complex in design, need more sophisticated toolsCan implement any function up to a product term limitSlow (two programmable planes)26Winter 200

17、9 ZDMC Lec. #1 268.3.3 PAL的應用舉例邏輯函數(shù)EDA軟件設計自學：P397例8.3.1P399例8.3.227Winter 2009 ZDMC Lec. #1 278.4 通用邏輯陣列 GAL8.4.1 電路結構形式1985采用E2CMOS工藝和靈活的輸出結構，有電擦寫反復編程的特性?？删幊獭芭c”陣列 + 固定“或”陣列 + 可編程輸出電路OLMC編程單元采用E2CMOS 可改寫統(tǒng)一型號輸出邏輯宏單元OLMC（Output Logic Macro Cell） 適當?shù)貫镺LMC進行編程，GAL就可以在功能上代替前面討論過的PAL各種輸出類型以及其派生類型28Winter

18、2009 ZDMC Lec. #1 28GAL16V8由OLMC編程決定input or OE由OLMC編程決定input or ouput由OLMC編程決定input or CLKGAL16V8：16表示陣列的輸入端數(shù)量，8表示輸出端數(shù)量，V則表示輸出形式可以改變的普通型29Winter 2009 ZDMC Lec. #1 29GAL器件結構和特點GAL16V8的基本結構8個輸入緩沖器8個輸出反饋緩沖器一個共用時鐘CLK8個輸出緩沖器8個OLMC30Winter 2009 ZDMC Lec. #1 308.4.2 OLMC輸出邏輯宏單元數(shù)據(jù)選擇器工作模式：由結構控制字決定AC0,AC1(n)

19、,XOR(n)編程信息：存于狀態(tài)控制字中。31Winter 2009 ZDMC Lec. #1 31狀態(tài)控制字：存放編程信息編程方法：通過對狀態(tài)控制字編程，便可決定OLMC的工作模式 。SYN（8個OLMC各共用）：決定CP 接入方法 ： SYN=0，CP同步接入。 SYN=1，CP作I/O端口32Winter 2009 ZDMC Lec. #1 32輸出邏輯宏單元OLMC組態(tài) 輸出邏輯宏單元由對AC1(n) 和AC0進行編程決定PTMUX、TSMUX、OMUX和FMUX的輸出，共有5種基本組態(tài)： 專用輸入組態(tài)、專用輸出組態(tài)、復合輸入/輸出組態(tài)、寄存器組態(tài)和寄存器組合I/O組態(tài)。8個宏單元可以

20、處于相同的組態(tài)，或者有選擇地處于不同組態(tài)。(1) 專用輸入組態(tài) ：如下圖所示：此時AC1(n)1，AC00，使TSMUX輸出為0，三態(tài)輸出緩沖器的輸出呈現(xiàn)高電阻，本單元輸出功能被禁止，I/O可以作為輸入端，提供給相鄰的邏輯宏單元。本級輸入信號卻來自另一相鄰宏單元。33Winter 2009 ZDMC Lec. #1 33(2) 專用輸出組態(tài)：如下圖所示：AC1(n)0，AC00，四路反饋數(shù)據(jù)選擇器FMUX輸出接在低電平，本單元的反饋信號和相鄰單元的信號都被阻斷 由于或非門，使異或門的輸出不經(jīng)過D觸發(fā)器，直接由處于使能狀態(tài)的三態(tài)門輸出由于與非門輸出使第一條乘積項經(jīng)過乘積項數(shù)據(jù)選擇器作為或門的輸入

21、34Winter 2009 ZDMC Lec. #1 348.4.3 GAL的輸入和輸出特性GAL是一種較為理想的高輸入阻抗器件CMOS輸入不可懸空35Winter 2009 ZDMC Lec. #1 35GAL輸出緩沖級三態(tài)N-MOS高速大電流36Winter 2009 ZDMC Lec. #1 368.5 可擦除的可編程邏輯陣列EPLD一、結構特點相當于“與-或”陣列（PAL） + OLMC二、采用EPROM工藝 集成度提高 高密度復雜的可編程邏輯陣列CPLD37Winter 2009 ZDMC Lec. #1 378.7 現(xiàn)場可編程門陣列FPGA一、基本結構1. IOB輸入輸出2. CL

22、B邏輯3. 互連資源IR4. SRAM編程數(shù)據(jù)Simplified version of FPGA internal architectureBasic idea: two-dimensional array of logic blocks and flip-flops with a means for the user to configure:1. the interconnection between the logic blocks,2. the function of each block.38Winter 2009 ZDMC Lec. #1 38Why FPGAs?By the e

23、arly 1980s most of the logic circuits in typical systems where absorbed by a handful of standard large scale integrated circuits (LSI). Microprocessors, bus/IO controllers, system timers, .Every system still had the need for random “glue logic” to help connect the large ICs:generating global control

24、 signals (for resets etc.)data formatting (serial to parallel, multiplexing, etc.) Systems had a few LSI components and lots of small low density SSI (small scale IC) and MSI (medium scale IC) components.39Winter 2009 ZDMC Lec. #1 39Why FPGAs?Custom ICs sometimes designed to replace the large amount

25、 of glue logic:reduced system complexity and manufacturing cost, improved performance.However, custom ICs are very expensive to develop, and delay introduction of product to market (time to market) because of increased design time. Note: need to worry about two kinds of costs:1. cost of development,

26、 sometimes called non-recurring engineering (NRE)2. cost of manufactureA tradeoff usually exists between NRE cost and manufacturing costs40Winter 2009 ZDMC Lec. #1 40Why FPGAs?Custom IC approach viable for products that are very high volume (where NRE could be amortized), not time-to-market sensitiv

27、e.FPGAs introduced as an alternative to custom ICs for implementing glue logic:improved density relative to discrete SSI/MSI components (within around 10 x of custom ICs)with the aid of computer aided design (CAD) tools circuits could be implemented in a short amount of time (no physical layout proc

28、ess, no mask making, no IC manufacturing), relative to ASICs.lowers NREsshortens TTMBecause of Moores law the density (gates/area) of FPGAs continued to grow through the 80s and 90s to the point where major data processing functions can be implemented on a single FPGA.41Winter 2009 ZDMC Lec. #1 41PL

29、As: 100s of gate equivalentsFPGAs: 1000-10000s gates upto 10,000,000gatesLogic blocksImplement combinationaland sequential logicInterconnectWires to connect inputs andoutputs to logic blocksI/O blocksSpecial logic blocks at periphery of device forexternal connectionsKey questions:How to make logic b

30、locks programmable?How to connect the wires?After the chip has been fabbed Field-Programmable Gate Arrays42Winter 2009 ZDMC Lec. #1 421. IOB可以設置為輸入/輸出；輸入時可設置為：同步（經(jīng)觸發(fā)器） 異步（不經(jīng)觸發(fā)器）43Winter 2009 ZDMC Lec. #1 432. CLB本身包含了組合電路和觸發(fā)器，可構成小的時序電路將許多CLB組合起來，可形成大系統(tǒng)-陣列44Winter 2009 ZDMC Lec. #1 44The Xilinx 4000

31、CLB45Winter 2009 ZDMC Lec. #1 453. 互連資源46Winter 2009 ZDMC Lec. #1 46Xilinx 4000 Interconnect47Winter 2009 ZDMC Lec. #1 47Xilinx FPGAs (interconnect detail)48Winter 2009 ZDMC Lec. #1 484. SRAM分布式每一位觸發(fā)器控制一個編程點49Winter 2009 ZDMC Lec. #1 49Details of Virtex-E SliceLUT4-input fun16x1 sram32x1 or 16x2 in

32、slice16 bit shift registerStorage element D flipflip latchCombinational outputs5 and 6 input functionsCarry chain arithmetic along row or col50Winter 2009 ZDMC Lec. #1 50二、編程數(shù)據(jù)的裝載數(shù)據(jù)可先放在EPROM或PC機中通電后，自行啟動FPGA內(nèi)部的一個時序控制邏輯電路，將在EPROM中存放的數(shù)據(jù)讀入FPGA的SRAM中“裝載”結束后，進入編程設定的工作狀態(tài)！每次停電后，SRAM中數(shù)據(jù)消失下次工作仍需重新裝載51Winter

33、2009 ZDMC Lec. #1 51Xilinx FPGA Adder ExampleExample2-bit binary adder - inputs: A1, A0, B1, B0, CIN outputs: S0, S1, CoutFull Adder, 4 CLB delays tofinal carry out2 x Two-bit Adders (3 CLBseach) yields 2 CLBs to finalcarry out52Winter 2009 ZDMC Lec. #1 52Virtex-E Family of Parts53Winter 2009 ZDMC L

34、ec. #1 53Why are FPGAs Interesting?Technical viewpoint:For hardware/system-designers, like ASICs only better! “Tape-out” new design every few minutes/hours.Does the “reconfigurability” or “reprogrammability” offer other advantages over fixed logic?Dynamic reconfiguration? In-field reprogramming? Sel

35、fmodifying hardware,evolvable hardware?FPGAs have tracked Moores Law better than any other programmable device.Staggering logic capacity growth (10000 x):54Winter 2009 ZDMC Lec. #1 54Why are FPGAs Interesting?Logic capacity now only part of the story: on-chip RAM, high-speed I/Os, “hard” function bl

36、ocks, .Modern FPGAs are “reconfigurable systems”Have been an archetype for the semiconductor industry as a whole:But, the heterogeneity erodes the “purity”argument. Mapping is more difficult. Introduces uncertainty in efficiency of solution.55Winter 2009 ZDMC Lec. #1 55Why are FPGAs Interesting?Have

37、 attracted an huge amount of investment for new ventures:Most startups have failed. Why?Business dominated by Xilinx and AlteraFPGAs at the leading edge of IC processing:Xilinx V7 out next year with 28nm TSMC processingFoundaries like FPGAs - regularity help get process up the “l(fā)earning curve”High-volume commitment gets interest of foundry(Gives FPGAs a competitive edge over ASICs, which usually are built on an older process.)FPGAs have been wildl