SoC設(shè)計方法和實現(xiàn)第十一章-低功耗

1、第十一章 低功耗設(shè)計OutlineWhy low powerSources of power consumptionLow power design methodologyLow power techniques Power analysis and toolsTrends in the futureWhy Low PowerPotable system - Battery lifetimeExample: mobile phone, PDA, Digital cameraDesktops: high power consumptionReliability and performanceNe

2、ed expensive chip package, cooling systemSeveral deleterious effectsDecreased reliability and performanceIncreased cost: packaging cost and cooling systemExceed power limits of the chip & systemPower, Cost and HeatComponent: silicon and packageIncreased die size (wider power busses)Need better therm

3、al capabilities (package material)Need better electrical capabilities System: Cooling and mechanicalsLarger fansOversized power suppliesPower limits to the wall1100W dc limit for 110V/20A plugChallenge of Design as Process ScalingOutlineWhy low powerSources of power consumptionLow power design metho

4、dologyLow power techniques Power analysis and toolsTrends in the futureSource of Power ConsumptionDynamic power consumptionStatic power consumptionKey areas of power consumption in SOCSource of Power Dissipation in CMOS DevicesC = node capacitancesNsw = switching activities (number of gate transitio

5、ns per clock cycle)F = frequency of operationVDD = supply voltageQsc = charge carried byshort circuit currentper transitionIleak = leakage currentStatic Power Consumption:Leakage currents:Sub-threshold current (I2)Gate leakage Gate tunnelling (I4)Gate induced drain leakage (I3)pn-junction reverse cu

6、rrent (I1)DC currentsAnalog circuit: sense-amps, pull-upsState dependentLeakage vs. ProcessWhat will be the dominated leakage current?Long Channel(L1um)Very small leakageShort channel(L180nm,tox30A)Subthreshold leakageVery short channel(L90nm, tox20A)subthreshold+gate leakageNano-scaled(L90nm,Tox20A

7、) Subthreshold+gate+junction leakageSub-threshold leakage current Has become quite important with technology scalingGate leakage currentIs becoming important with shrinking device dimensions PN junction leakage currentNegligible OutlineWhy low powerSources of power consumptionLow power design method

8、ologyLow power techniques Low power analysis and toolsTrends in the futureLow Power Design MethodologyMust know your systemMaximize the performance while minimize the power consumptionMinimize the power consumption while maximize the performanceOpportunities for Power SavingOutlineWhy low powerSourc

9、es of power consumptionLow power design methodologyLow power techniques Power analysis and toolsTrends in the futureLow Power TechniquesLeakage power controlDynamic power controlArchitecture level power optimizationSystem level power optimizationLow Power TechniquesProcess scaling Low Vdd, Multi-thr

10、esholdVoltage scalingSubstrate bias(200mv)Multi-voltage (voltage island)Dynamic voltage scaling; multi-thresholdHW design techniquesPre-computation, glitch minimization, Logic level,Physical level optimizationLow power System/SW Power aware Operation System, compiler, SW design etc.Low Power Techniq

11、ues on Chip DesignLeakage PowerMulti Vt optimizationPower gatingSubstrate biasPower gatingDynamic PowerMulti-voltage designAdvanced clock-gatingGate-level power optimizationTechniques for Reduce Leakage PowerUsing Multi-Vt LibrariesTiming and leakage tradeoffLow Vt cell: faster speed, high leakageHi

12、gh Vt cell: slower speed, lower leakagePrinciple: low Vt for critical path and high Vt for non-critical pathsHigh Vt cell on Critical PathHints:You need to have dual Vt libraryYou need to pay for the extra layer mask for multi-vt Using Multi-Vt Libraries cont.Synthesis Strategy: Use high Vt cells fi

13、rst, then fix setup violation by replace the high Vt cells on the critical path to low Vt cellsUse low Vt cells first, then swap to high Vt cells, fix setup violation by swap low Vt cells on the pathsNo area penalty Library design for freely mix and match on SoC designPower Gating Also called Multi-

14、Threshold CMOS (MTCOMS), logic sleep control, etc.Active mode: sleep control devices on, VDDV and GNDV act as virtual supplySleep mode: sleep control devices off, reduce leakageHigh Vt transistors reducing both leakage and switching powerPower Gating cont.Sleep transistors used only on the supply ra

15、il or on both supply and ground railsNot added on every gatePower gating retention registerActive modeHigh performance regular FF functionSleep ModeCut-off VddLow leakage stage saving latch functionBody BiasVariable threshold according to body biasingZero body bias in active mode (Low Vt)Reverse bod

16、y bias in stand-by mode (High Vt)Tradeoff between the time on module turn-on and leakage currentTriple well structure CMOS InverterHint:Do you have the triple well structuredstandard cell lib?Techniques for Reduce Dynamic PowerMulti Voltage DesignBlock based approach in the design flowNeed to additi

17、onal isolation cells and voltage level-shifter cells between voltage domainsClock Gating TechnologyToggling consume power.Enable the module clock only when neededgated_clkEnableLogicGlobalClkComb.LogicDataRegClock Gating Cell DesignProblem with simple clock gating:Uncompleted cycleGlitchClock Gating

18、 with LatchAdd a transparent-low latchMake sure the clk gating cells are placed tightly for correct function clk cell hardeningCommonly in SoC: make a “hardmacro” - clk gating cellRTL code for clk cell:always (clk or clk_en) if(!clk) ctrl_latch = clk_en;assign gclk = ctrl_latch & clkClock gating cel

19、ls and a glitch free clock gatingClock Gating With Integrated Test LogicAbility to let clk pass through in test mode (TEST=1)Gated Clock in Clock Tree DesignDisable clocking near the root of a clock tree, instead of at each FF.Special care must be taken in clk tree synthesis to prevent the buffers i

20、nserted between clk root and the clk gating cellGate Level OptimizationTechnology independent optimization:Circuit optimization: logic optimization, reduce redundant logicTrimming for low power: reduce positive slackGate resizingPin swapping/reassignmentRe-mappingPhase assignmentRe-factoringLow powe

21、r driven technology mappinglow power cellGate Level Optimization Gate SizingGate sizingDown-size gates on fast paths to decrease their input capacitances for minimizing switching current in front driver Enlarge heavily loaded gates to increase their output slew rates for minimizing short-circuit cur

22、rentDealing with GlitchesFor some type of data path circuits, up to 60% of the dynamic power is due to glitchesVery expensive calculationNeed to propagate probabilistic waveformsExample: Glitch MinimizationHazardous transition occurs at the output of AND gate due to different delays through two diff

23、erent delay paths converging at the inputs to the gatePhysical Level OptimizationLibrary Design: Energy-efficient cells Design planning: develop a realizable floorplan and realistic budgets for powerPlacement and routing: reduce glitchesIn placement optimization: buffer & wire resizing Transistor re

24、sizing: minimize capacitanceWidth/Spacing/Shielding/Metal layer optimization to reduce C &R.Reduce via resistance by adding more viasPhysical level optimization cont.Power planning: defines power rings and mesh. Power driven floor-planningDecoupling cap between Supply and GroundSudden change in powe

25、r consumption occur when blocks are powered on or offDecoupling capacitor helps to reduce the transient current for high speed designHave seen in filler cell at 0.13um processBut the leakage on decoupling cap itself at 90nm and below must take into accountGlobal Clock RoutingReduce Clock LoadReduce

26、oversized clock driverReduce # of clock driversReduce # of clock tracksMinimum Width Clock Tracks are resistance limitedLower R for drivabilityLower C for powerIncrease width & space to minimize C & R where possible.Add enough vias to reduce resistanceArchitecture level Power OptimizationMemory Opti

27、mizationParallel/Pipeline AlgorithmMemory OptimizationMemory cell redesignReduce leakageDual Vt SRAM CellGated Vdd SRAM cellGated GND SRAM cellPower-aware DRAMMemory hierarchySmall segmentEach bank can independently put into appropriate power modeMemory management & data localityCacheMultiple power

28、statesSystem Level Power OptimizationEnergy is consumed by all hardware unitsSoftware organization affects hardware energy consumptionManagement: run-time system management and control of all unitsEnergy Saving PrincipleOnly need to run just fast enough to meet the application software deadlines and

29、 maintain qualityRun task as slow as possibleReduce voltage to lower levelRun task in time availableReduce voltage to match timeSource: ARM. IEM: Intellectual Energy ManagementDynamic power managementWhat is Dynamic power management?To selective shutoff or slow-down of system components that are idl

30、e or underutilizedPower manager observes system & responds at run-timeWhy OS Directed Power Management?Dynamic Voltage and Frequency ScalingDynamic Power ManagementChange the power state of the system components to lower the energy consumption depending on the performance constraintsDynamic Voltage

31、and Frequency Scaling (DVFS)Adjust the performance and energy consumption levels while the device is activeKey is to meet users performance needs while saving energyReduce the processors voltage and frequency to obtain quadric energy savingExample A close loop intelligent energy managementIncrease t

32、he battery life of handheld portable devices in several stages from 25% up to 400%. DVS & DFS designed by ARM & National Semiconductor ARM & National SemiconductorNews on July 18, 2019:TSMC and ARM Collaboration Achieves Significant Power Reduction On 65nm Low-Power Test ChipPower Management Strateg

33、yMulti-corner timing closure capability, which anticipates the timing impact of voltage scaling on the timing of library cells that offer different threshold voltages. This technique recognizes shifts in the critical path and earmarks them for timing analysis at any point in the design cycle. Multi-

34、threshold (MT) CMOS technology is implemented together with dynamic voltage and frequency scaling (DVFS) to reduce dynamic and standby (leakage) power for different operating conditions. Design methodologies are demonstrated for power-gating cell wake-up/sleep control, power isolation and timing sig

35、noff for voltage islands. ARM Intelligent Energy Manager (IEM) technology supports dynamic voltage and frequency scaling, and is now being extended to include leakage control using power gating and state retention under software control. Summary of Power Reduction TechniqueSource: conference papers,

36、 magazine articles低功耗技術(shù)漏電功耗的減小靜態(tài)功耗的減小時序影響面積影響設(shè)計方法影響驗證復(fù)雜度影響仿真影響面積優(yōu)化10%10%0%-10%無低無多閾值工藝80%0%0%2%低低無時鐘門控020%0%2%低低無多電壓50%40-50%0%10%中中低電源門控90-98%0%4-8%5-15%中高低動態(tài)電壓及動態(tài)頻率縮放 50-70%40-70%0%10%高高高體偏置90%-10%10%高高高OutlineWhy low powerSources of power consumptionLow power design methodologyLow power technique

37、s Power analysis and toolsTrends in the futurePurposeFind the main power consumption components in our design to help us optimization designFind the power consumption in early stage to to enable efficient design space exploration and help system level decisions Power Types and UsesPeak powerNeed to

38、size power busses, limit ground noise (bounce)Time averaged powerPackage choicesCooling devices and systemBattery lifeRMS (Root mean square)Used for electromigration rulesAccuracy vs. Efficiency TradeoffPower Estimation and SimulationRTLEarly-analysis, fastest, simulation pattern refining and debugging easierLess accurate, results depend on the accuracy of library data Gate LevelAccurate-analysis, simulation with RC and SDFNeed accuracy library, state dep