數(shù)字設計課件-第6章--組合邏輯設計實踐2

1、Chapter 6 Combinational Logic Design PracticesMSI building blocks are the important element of combinational circuits.7/18/20221本章重點具備一定功能的通用組合邏輯電路的設計方法及實例掌握常用的MSI的使用方法及功能擴展掌握譯碼器、MUX實現(xiàn)組合邏輯功能的方法能分析、設計由MSI構建的電路7/18/20222chapter 66.1 Documentation Standard1. Signal Names and Active LevelsMost signals (

2、signal name) have active level. active high active lowNaming convention surffix “_L” attaching to signal name represent active low level. Like, EN_L、READY_L In logic relation, EN_L=EN， READY_L=READY。7/18/20223chapter 62. Active levels for pinsENEN_LDinstartDoutflgstart_LDinDoutflg_LInversion bubbleA

3、ctive lowENENDinstartDoutflgstartDinDoutflgActive hign7/18/20224chapter 6Exp2：EN=1 (active high), data can be transferredEN=0 (active low), data can be transferredENCLKEN_LCLK7/18/20225chapter 63. bubble-to-bubble logic designMake the logic circuit easier to understand.Exp：Not matchABSELDATAABASELDA

4、TAmatch7/18/20226chapter 66.3 Combinational PLDs1. Programmable logic arrays (PLA) two level “ANDOR”device. Can be programmed to realize any sum-of-products logic expression.An nm PLA with p product terms: ninputs moutputs pproduct terms7/18/20227chapter 643 with 6 product termsAND arrayOR array7/18

5、/20228chapter 67/18/20229chapter 62. Programmable Array Logic DevicesFixed OR array，programmable AND arrayBidirectional input/output pins，熔絲型PAL16L8，Output enable7/18/202210chapter 63. Generic Array Logic Devices（GAL）an innovation of the PAL; can be erased and reprogrammed; 7/18/202211chapter 66.4 D

6、ecoderAn important type of combinational circuit .input code wordenable inputOutput code word decodeer1-to-1mapping1-out-of-m codenmn-bitm-bit7/18/202212chapter 61、bianry decodersinput code：n-bitoutput code：2n-bit 2-4 decoder（2-22） I1I0Y3Y2Y1Y0truth table：？Yi：？I1I0Y3Y2Y1Y0000001010010100100111000Yi=

7、miY0=I1I0Y1=I1I0Y2=I1I0Y3=I1I02-4decoderOne input combination chooses an output port.7/18/202213chapter 62-4 decoder with enable inputYi=EN miENI1I0Y3Y2Y1Y0000001000001101001011001001111000I1I0Y3Y2Y1Y0EN2-4 decoder7/18/202214chapter 6（2）74139 , dual 2-4 decoderInput code：B（MSB） A（LSB）Also be called

8、address input.Output code：Y3_LY0_LEN 7/18/202215chapter 6（3）74138, 3-8 decoderEnable inputEN=G1G2A_LG2B_LInput code：C（MSB）、B、 AOutput code： Y0_L Y7_LYi_L=（ENmi）Y0_LY1_LY2_LY3_L Y4_L Y5_L Y6_L Y7_LG1G2A_LG2B_LEN7/18/202216chapter 6ENmsblsb7/18/202217chapter 62、realizing combinational circuits with de

9、coderreview：canonical sumDecoder output：Yi_L=(ENmi) when EN=1， Yi_L=mi =Mi add an NAND gate to the decoders output.Exp: (1) F=AB（0、3）F=AB+ABEnable asserted7/18/202218chapter 6（2）if a 3-bit number XYZ is odd number，then ODD output 1，else output 0. realize the function with decoder and gates.solution：

10、F=？F=XYZ（1，3，5，7）7/18/202219chapter 6（3）F=XYZ（0、1、5） 解：7/18/202220chapter 63. Cascading binary decodersHow to construct a 4-16、5-32 decoder？ use multiple 2-4 or 3-8 decoders to cascade.PS.：confirm the number of decoders according to the input and output bits.only one chip works in each decoding oper

11、ation.7/18/202221chapter 6Exp：a 4-16 decoderInputs: 4-bit N3、N2、N1、N0。Outputs: 16-bit DEC15_LDEC0_LNeed 2 3-8 decoders. Use the MSB of the inputs as chip-select bit. 000000010111100010011111N3 N2 N1 N0N3 N2 N1 N07/18/202222chapter 6Chip selecting7/18/202223chapter 6Exp：4-bit prime-number detector. R

12、ealizing it with 74138 and some gates.N3N2N1N0F7/18/202224chapter 64、7-segment decoderClassify of 7-seg displayer：in materials: LED（發(fā)光二極管） LCD（液晶）In working mode: common-cathode (共陰極) common-anode (共陽極)afbcegddpabcdedpfggndgnd7/18/202225chapter 67-segment decoder transform the input BCD code to 7-se

13、gment displaying code.devices： 7446A、74LS47 （驅動共陽） 74LS48、 74LS49（驅動共陰）00001001 are useful input codes.10101111 are unused BCD code.7/18/202226chapter 674LS497/18/202227chapter 65、BCD decoder（二十進制譯碼器）Inputs: BCDY0Y9BCD decoderOutput:1-out-of 10 code74HC427/18/202228chapter 65.5 Encoder1、binary encod

14、er inputs:1-out-of-2n codeI0I1Im(m=2n-1) output:n-bitY0Y1Yn-1binary encoder7/18/202229chapter 68-3 encoderinputoutputI7I6I5I4I3I2I1I0Y2Y1Y01000000011101000000110001000001010001000010000001000011000001000100000001000100000001000In/out:active high7/18/202230chapter 6Y0=I1+I3+I5+I7Y1=I2+I3+I6+I7Y2=I4+I

15、5+I6+I7Each input port has its corresponding output code.7/18/202231chapter 62、Priority Encoderif multiple inputs are asserted, how to deal with?solution：assign priority to each input from high to low. let I7 highest priority and decrease from I6 down to I0 A2,A1,A0encode output IDLEwhen no input is

16、 asserted, IDLE=17/18/202232chapter 6inputoutputI7I6I5I4I3I2I1I0A2A1A0IDLE111100111000011010000110000000101100000010100000000100100000000100000000000000017/18/202233chapter 6Logic expressions for priority encoderH7=I7H6=I6I7H5=I5I6I7H0=I0I1I2I3I4I5I6I7A2=H4+H5+H6+H7A1=H2+H3+H6+H7A0=H1+H3+H5+H7IDLE=(

17、I0+I1+I2+I3+I4+I5+I6+I7) =I0I1I2I3I4I5I6I7Expressions for each asserted input in the truth table of priority encoderOutput code expressions 7/18/202234chapter 63、74148 Priority EncoderEI_L：Enable Input.I7_LI0_L：encode input，I7_L has highest priority.A2_LA0_L：encode outputGS_L：GS_L =0 when one or mor

18、e of the request inputs are asserted.EO_L：enable output, EO_L=0 when all of the request inputs are negative and EI_L=0. 高低優(yōu)先級7/18/202235chapter 674148真值表7/18/202236chapter 64、cascading priority encoderproblem：how to construct 16-4、32-5 priority encoder？Connecting multiple 8-3 endoder.note：make sure

19、the needed number of chips according to the inputs.need to redesign the output circuit that could produce the correct encoding output.7/18/202237chapter 616-4 priority encoder: use two 74148 U1、U2，(1) U1: input E15_LE8_L; U2: input E7_LE0_L; E15_L is the highest priority,(2) output: A3_LA0_L，active

20、low;(3) When one or more inputs is asserted，GS0_L=0；and A3_LA0_L=1111.7/18/202238chapter 616-4 priority encoderU174HC148A09A110A211GS14D34D45D56D23D12D78D67EI12EO13U274HC148A09A110A211GS14D34D45D56D23D12D01D78D67EI12EO13U3A74HC08U3B74HC08U3C74HC08U3D74HC08D01EN15_LEN14_LEN13_LEN12_LEN11_LEN10_LEN9_L

21、EN8_LEN7_LEN6_LEN5_LEN4_LEN3_LEN2_LEN1_LEN0_LD0_LD1_LD2_LD3_LGS_L7/18/202239chapter 6思考：若需要編碼輸出、GS0為高電平有效，如何修改電路輸出結構？P.413 figure 6-49 shows the 32-5 priority encoders strcture,.7/18/202240chapter 66.6 Three-state Devices1、three-state buffers7/18/202241chapter 6EN_LAOUTENEN_LAAOUT_LOUT_LEnable means

22、: the buffer output normal logic 0、1 when EN is asserted；the buffer output Hi-Z when EN is negated. 7/18/202242chapter 6Application data返回時序 address of data source7/18/202243chapter 6Issues in application TPLZ 、TPHZ ：time that takes from normal logic into Hi-Z; TPZL 、TPZH ：time that takes from Hi-Z

23、into normal logic;generally， TPLZ 、TPHZ TPZL 、TPZH But to confirm the correction in application, a control logic is adopted.7/18/202244chapter 674138的相關引腳信號查看電路 截止時間（停滯時間）7/18/202245chapter 6課堂練習試設計一個電路，當控制信號M=1時，電路為“判一致”電路，即當三個輸入變量取值全部相同時輸入為1；當控制信號M=0時，電路為“多數(shù)表決”電路，即輸出等于輸入變量中占多數(shù)的取值。請寫出最簡表達式。（注：至少要寫出

24、卡諾圖，三變量為X、Y、Z）7/18/202246chapter 66.7 Multiplexer2-to-1 MUXABSELYY=SELA+SELBS=0， Y=AS=1，Y=BABS=0Y=AABS=1Y=BLogic circuit7/18/202247chapter 6又稱數(shù)據(jù)選擇器，簡稱MUXOutput:enableselect n data source data output n2s mj：SELj minterm1、基本結構：7/18/202248chapter 6Let b=1, D0D1DjDn-1SELENY7/18/202249chapter 6Exp:4-to-1

25、 MUXABCDS1S001101234outputCS0S1output00A01B10C11D7/18/202250chapter 62、MSI MUX（1）8-to-1 MUX ，74151EN_LaddressY_LY7/18/202251chapter 6返回7/18/202252chapter 6G_L S （2）4-bit, 2 input MUX ，741577/18/202253chapter 6（3）2 bit, 4 input MUX，74 153inputoutput1G_L2G_LBA1Y2Y00001C02C000011C12C100101C22C200111C32

26、C301001C0001011C1001101C2001111C30100002C0100102C1101002C2101102C311001G_L2G_L7/18/202254chapter 63、Expanding MUXsExp1：use 74151 to realize a 16-to-1 MUX, some gates can be used if necessary.Chips needed： according to the 16 inputs, 2 74151 chips.output： combine two chips outputs into one output.7/1

27、8/202255chapter 6The MSB(A3) of input act as the chip-select bit.7/18/202256chapter 6Exp2：用74153實現(xiàn)4輸入，4位MUX，。 設4路輸入分別是：1D3.0、2D3.0、3D3.0、4D3.0； 4位輸出是：Dout3.0 輸入選擇：S1、S0解：無需外加門，只需要合理安排輸入、輸出數(shù)據(jù)端口即可。7/18/202257chapter 6Dout3S1S07/18/202258chapter 64、用MUX實現(xiàn)組合邏輯函數(shù)的標準和 multiple input, 1 bit MUX, the output

28、： when EN is asserted： the canonical sum form.74151的內部電路mj: minterm of the select (address) inputs.7/18/202259chapter 6MUX的數(shù)據(jù)輸入端與真值表的每行輸出對應，MUX的地址選擇端作為最小項產生器，即 真值表：輸出值輸入變量 MUX：數(shù)據(jù)輸入端地址端Exp1：a circuit output 1 when its 3-bit input can be divided by 3. construct the circuit by using 74151. So：F=XYZ（？）

29、and circuit？按最小項編號順序變量與選擇端對應7/18/202260chapter 6例1的電路XYZFU1W6D04D13D22D31D415D514D613D712S011S29S110Y5G7VCCGNDR17/18/202261chapter 6例2：若例1中輸入數(shù)為4位二進制數(shù)，如何實現(xiàn)？解1：用16輸入，1位的MUX來實現(xiàn)，選用74150。 F=WXYZ（0，3，6，9，12，15）解2：仍選用74151，先對所求函數(shù)的卡諾圖做降維處理。預備知識：卡諾圖的降維 用一個n變量的卡諾圖來處理m變量的函數(shù)（nB)F(A=B)F(AB= ABFABFABFA=BFAB=(A1B1

30、)+(A1=B1) ( A0B0) = A1B1 + (AB+AB)(A1B1 )FA=B=(A1=B1)(A0=B0)FAB=(A1B1)+(A1=B1)(A0BFA=BFABA1B11A1=B1A0B01A1=B1A0=B01Pseudo-logic7/18/202291chapter 64. Standard MSI magnitude comparator7485: 4-bitMagnitude input: A3.0, B3.0Cascading input：ALBI、AEBI、AGBI，which are used to expanding comparator.output：AL

31、BO、AEBO、AGBOAGBO=(AB)+(A=B)AGBIAEBO=(A=B)AEBIALBO=(ABFA=BFABFA=BFABX11.8Y11.8X7.4Y7.4X3.0Y3.07/18/202294chapter 6Class exerciseABCDFDAADCDCABJudge whether the following circuit has static hazard or not, if static hazard exist, please point it and eliminate by using K-map. Then write the hazardless m

32、inimal sum.7/18/202295chapter 66.10 Adders、Subtractors and ALUUsed to do binary addition and subtraction1. Half adders and full adders（1）half addersXYHSCO0000011010101101half sum：HS=XYcarry-out：CO=XYXYHSCO7/18/202296chapter 6（2）full addersCINXYSCO0000000110010100110110010101011100111111sum：S=XYCINcarry：CO=XY+CINX+CINY7/18/202297chapter 62、ripple addersUse 1-bit full adder as a module to construct n-bit ripple adder.XY