GPIO中斷使用說明

1、GPIO中斷使用說明1. GPIO的配置一共有四組GPIO基址寄存器：Base Address: GPIO 0: 0 xD401_9000 (對應(yīng)GPIO0_31)Base Address: GPIO 1: 0 xD401_9004 (對應(yīng)GPIO32_63)Base Address: GPIO 2: 0 xD401_9008 (對應(yīng)GPIO64_95)Base Address: GPIO 3: 0 xD401_9100 (對應(yīng)GPIO96_127) 需要配置GPIO的三個寄存器：GPIO Direction Register (GPIO_CDR, offset 0 x60)BitsNameT

2、ypeResetDescription31:0PDxw0 x0PDnSet GPIO port direction n (where n = 0 through 31)0 二 GPIO Pin Direction Register bit not affected1 二 GPIO Pin Direction Register bit is cleared and GPIIO n function is set to INPUT設(shè)置對應(yīng)GPIO的方向為輸入；GPIO Falling-Edge Detect Enable Register (GPIO_FERx, offset 0 x3C)Bits

3、NameTypeResetDescription31:0FexR.W0 x0FEnGPIO port falllling-edge detect enable n (where n = 0 through 31)0 二 Disable falling-edge detect enable1 = Set corresponding GPIO Edge Detect Status Register status bit when a falling edge is detected on the GPIO port使能對應(yīng)GPIO的下降沿觸發(fā)Modem ARM*(Seagull) Core Bit

4、-wise Mask of GPIO Edge Detect Register (CPMASK_REG, offset 0 xA8)BitsNameTypeReetDescription31:0PDxRnv0 x0PDnMask GPIO Edge detect n (where n = 0 through 31) 0 = GPIO Edge detects are masked1 = GPIO Edge detects are not masked打開對應(yīng)GPIO的邊沿探測使用示例(GPIO23，對應(yīng)的基址寄存器是GPIO 0: 0 xD401_9000)： volatile unsigne

5、d long * r;/set GPIO_CDR, set GPIO23 direction as inputr = (volatile unsigned long*)(0 xD4019000 + 0 x60);*r = (1 23);/set GPIO_FERx, set GPIO23 Falling-Edge enable r = (volatile unsigned long*)(0 xD4019000 + 0 x3C);/set CPMASK_REG, set GPIO23 Edge detects are not masked r = (volatile unsigned long*

6、)(0 xD4019000 + 0 xA8);*r |= (123);2. ICU(中斷控制器)的配置使能中斷控制器組中對應(yīng)于GPIO的中斷源寄存器（GPIO是中斷控制器中第55個中斷 源，地址是中斷控制器的基址+55*4）BitsNameTypeResetDescription317ReservedRSVDReserved. Always write 0. Ignore read value.6MOHAWKJNTR/W0 x1Mohawk PJ1 Core InterruptMohawk PJ1 Core Interrupt1 = Route to Mo hawk PJ1 Core Inte

7、rrupt5SEAGULL_INTR/W0 x1Modem ARM* (Seagull) Core InterruptModem ARM* (Seagull) Core Interrupt1 = Route to Modem ARM* (Seagull) Core InterruptIRQ_FIQR/W0 x0IRQ/FIQIRQ/FIQ1 二 Route to IRQ0 二 Route to FIQ3:0PRIORITY_MASKINR/W0 x0Priority/M askingPriority/Mias kingOxF to 0 x1 二 Interrupt arbitration pr

8、iority0 x0 = Interrupt is masked使用示例：/enable icu gpio intr = (volatile unsigned long*)(0 xD4282000 + 55*4);*r = 0 x3F;3.配置并使能GPIO中斷配置中斷源和中斷觸發(fā)類型，并綁定到客戶自己定義的中斷處理函數(shù)，并使能中斷。 使用示例：INTCConfigure(INTC_SRC_GPIO_COMBINED_CP, INTC_IRQ, INTC_FALLING_EDGE);/user defined ISR: gpio_test_isrINTCBind(INTC_SRC_GPIO_C

9、OMBINED_CP, gpio_test_isr);INTCEnable(INTC_SRC_GPIO_COMBINED_CP);4. GPIO Edge Detect Status Register The GPIO Edge Detect Status Registers (GPIO_EDRO, GPIO_EDR1, GPIO_EDR2, and GPIO_ EDR3) contain a total of 128 status bits that correspond to the 128 GPIO ports.These registers contain one edge detec

10、t status bit for each of the 128 ports. GPIO_EDRO31:0 correspond to GPIO31:0. GPI0_EDR1 31:0 correspond to GPIO63:32.GPIO_EDR231:0 correspond to GPIO95:64.GPIO_EDR331:0 correspond to GPIO127:96When an edge-detect occurs on a port that matches the type of edge programmed in the GPIO Rising-Edge Detec

11、t Enable and/or GPIO Falling-Edge Detect Enable Registers, the corresponding status bit is set in this register. Once a bit is set in this register the CPU must clear it. Status bits in this register are cleared by writing a 11 to them. Writing a 0 has no effect.Each edge-detect that sets the corres

12、ponding status bit in this register for GPIO ports 0 - 127 can trigger an interrupt request, ports 2-127 together form a group that can cause one interrupt request to be triggered when any one of the status bits 2 -127 in this register is set. GPIO ports 0 and 1 each cause their own, independent fir

13、st-level interrupt. This register shows the GPIO_EDRO bit locations.Table 668: GPIO Edge Detect Status Register (GPIO_EDR) Offset: 0 x0048BitsField(Short)TypeI nit VaiDescription31:0EDn(Edx)RW1C 0 x0GPIO edge detect status n (where n = 0 through 31)0 = No edge detect has occurred on the port as specified in GPIO Rising-Edge Detect Enable and/or GPIO FallingEdge Detect Enable Registers1 = Edge detect has occurred on the port as specified in the GPIO Rising-Edge Detect Enable and/or GPIO FallingEdge Detect Enable Registersvoid * GPIO_MylSR (void) 一if (Platfonn