RF射頻電路設(shè)計(jì)英文課件Lecture02_Voltage and power transporta

1、Lecture 2精選ppt1 Lecture 2 : Voltage and Power Transportation Richard Chi-Hsi Li 李緝熙李緝熙 Email : 1. Voltage Delivered from a Source to a Load o General Expression of Voltage Delivered from a Source to a Load o Additional jitter or Distortion in a Digital Circuit Block 2. Power Delivered from a Source

2、to a Load o General Expression of Power Delivered from a Source to a Load o Power Instability o Additional Power Loss o Additional Distortion o Additional interference3. Impedance Conjugate Matching o Maximization of Power Transportation o Power Transportation without Phase Shift o Impedance Matchin

3、g Network o Necessity of Impedance Matching 4. Additional Effect of Impedance Matching o Voltage Pumped up by Impedance Matching o Power MeasurementLecture 2精選ppt21. Voltage delivered from a source to a loado General expression of voltage delivered from source to loadSSSjXRZLLLjXRZ oSoSSZZZZoLoLLZZZ

4、ZoSZZoLZZ0S0L tjSoSevv02)()1 (nnLSnTTtjLLSLSoTtRdddLeZZRvv112)()1 ()1 (nnLSTntjLLSLSoTtjLLSLSoTtRdddLeZZRveZZRvvFigure 1 Voltage delivered from a source to a loadSLZoRSXS ZSSourcePSvS XL ZLLoadRLLRPLecture 2精選ppt3tl (Delay time =Td) SourceLoadFigure 2 Voltages bouncing back and forth arrive at load

5、when t =Td . Note: kv = RL/(ZS+ZL)Voltage delivered from Source:Voltage delivered from Source:-12Td -11Td Voltage delivered from Source:Voltage delivered from Source:-10Td -9Td -8Td 2Td 1Td -1Td 0 -3Td -2Td -5Td -4Td -7Td -6Td Voltage delivered from Source:Voltage delivered from source: Voltage deli

6、vered from Source:Voltage arrived at RL ,)12(dTtjSovevkdLTtRv)10(dTtjSovevk)8(dTtjSovevk)6(dTtjSovevk)4(dTtjSovevk)2(dTtjSovevktjSovevkLecture 2精選ppt40dT0)()1 (nnLSLLSLtjSoTtRZZRevvdLLSnnLS110LSLLSLtjSoTtRZZRevvdL111)()1 ()1 (nnLSLLSLtjSoLLSLtjSoTtRZZRevZZRevvdLNote thatIfthenLecture 2精選ppt5 , o Add

7、itional Jitter or Distortion in a Digital Circuit BlocksrvTtRstTtRTtRdLdLdLvvv,1 ,)1 (1 ,LLSLtjSostTtRZZRevvdLLSLSLLSLtjSosdvTtRZZRevvdL11,LSLSstTtRsdvTtRvdLdLvvD11 ,%LSLSvDjitter1%LSLSstTtRsdvTtRfvvTjitterdLdL111 ,secLecture 2精選ppt6Table 1 Additional distortion and additional jitter in voltage tran

8、sportation when f = 3.86 GHz S, %L, % D,% f, GHz T, ns Jitter, % Jitter, ps00 3.86 0.2590.00 050 3.860.2590.00 0100 3.860.2590.00 0200 3.860.2590.00 0500 3.860.2590.00 0053.860.2590.00 0553.860.2591053.860.259 2053.860.2595053.860.2590103.860.2590.00 05103.860.259 10103.860.25920103.860.25950103.860

9、.259 0203.860.259 0.00 05203.860.25910203.860.25920203.860.25950203.860.2590503.860.2590.00 05503.860.25910503.860.25920503.860.25950503.860.259Lecture 2精選ppt7%10L%10Spsjitter6 . 2sec%01. 1%jitterD , and then,1) when%10L%10Spsjitter6 . 2sec%01. 1%jitterD , and then,2) when %50L%50Spsjitter4 .86sec%3

10、 .33%jitterD , and then,3) when The voltage reflection becomes pernicious. The voltage reflection seems not too harmful. The voltage reflection is horrible!Lecture 2精選ppt82. Power delivered from a source to a loado General expression of power delivered from source to loadSSSjXRZLLLjXRZoSoSSZZZZoLoLL

11、ZZZZoSZZoLZZtjSoSevv0S0L2SS2LL02222)()1 (nnLSnTTtjLLSLSoTtRdddLeZZRvPFigure 3 Power delivered from a source to a loadSLZoRSXS ZSSourcePSvS XL ZLLoadRLLRP12222222)()1 ()1 (nnLSnTTtjLLSLSoTtjLLSLSoTtRddddLeZZRveZZRvPLecture 2精選ppt9tl (Delay time =Td) SourceLoadFigure 4 Powers bounce forth and back and

12、 arrive at load when t =Td . (Note: kp=RL/|ZS+ZL|2)Power delivered from source:Power delivered from source:-12Td -11Td Power delivered from source:Power delivered from source:-10Td -9Td -8Td 2Td 1Td -1Td 0 -3Td -2Td -5Td -4Td -7Td -6Td Power delivered from source:Power delivered from source:Power de

13、livered from source:Power arrived at RL ,dLTtRP)12(22dTtjSopevk)10(22dTtjSopevk)8(22dTtjSopevk)6(22dTtjSopevk)4(22dTtjSopevk)2(22dTtjSopevktjSopevk22Lecture 2精選ppt1002222)()1 (nnLSnTTtjLLSLSoTtRdddLeZZRvP0dTLSLLSLSLSLLSLtjSoTtRZZRvZZRevPdL111122222o Power Instability02222)()1 (nnLSnTTtjLLSLSoTtRdddL

14、eZZRvPLSnnLS110Note thatIfthenLecture 2精選ppt11o Additional Power Loss222220,LSLSLSLtjSoTtRZZRvZZRevPLdLLSLSTtRTtRTtRTtRLdLLdLdLdLPPPP110,0,LSLSTtRTtRLdLdLPP110,LSLLSLSLSLLSLtjSoTtRZZRvZZRevPdL111122222Lecture 2精選ppt12 Table 2 Additional power loss due to the unmatched case when = -30 dBm.S, %L, % ,d

15、Bm ,dBm ,dBm000.0000 -30-infinite-30500.0000 -30 -infinite-301000.0000-30 -infinite-302000.0000-30-infinite-305000.0000-30 -infinite-30050.0500-30 -43.01-30.22550.0476 -30 -43.22-30.211050.0452-30-43.45-30.202050.0404-30-43.94-30.185050.0256 -30-45.91-30.110100.1000 -30 -40.00-30.465100.0955 -30 -40

16、.20-30.4410100.0909-30-40.41-30.4120100.0816 -30 -40.88-30.3750100.0526-30-49.79-30.230200.2000-30-36.99-30.975200.1919-30-37.17-30.9310200.1837 -30-37.36-30.8820200.1667 -30-37.78-30.7950200.1111-30-354-30.510500.5000-30-33.01-33.015500.4872-30-33.12-39.9010500.4737-30-33.25-39.7920500.4444-30-33.5

17、2-39.5550500.3333-30-34.77-31.76LSLS110,LdLTtRPdLTtRPdLTtRPLecture 2精選ppt13o Additional DistortionsrpTtRstTtRTtRdLdLdLPPP,1 ,1222222)()1 ()1 (nnLSLLSLtjSoLLSLtjSoTtRZZRevZZRevPdLLSLSLSnnLSnnLS1111101LSLSLLSLtjSoLLSLtjSoTtRZZRevZZRevPdL1)1 ()1 (222222)1 (2221 ,LLSLtjSostTtRZZRevPdLLSLSLLSLtjSosrpTtRZ

18、ZRevPdL11222,LSLSstTtRsrpTtRpdLdLPPD11 ,%Note thatLecture 2精選ppt14Table 3 Additional distortion in power transportation S, % L, % Dp,% 000.00 500.00 1000.00 2000.00 5000.00 0529.365521.8210521.2720520.1050516.0101031.6251030.90101030.15201028.57501029.9402044.7252043.81102049.86202040.82502033.33050

19、70.7155068.00105068.82205066.67505057.74 Lecture 2精選ppt15From Table 3 it can be seen that In cases where L = 0, there is no additional distortion. On the contrary, in the cases of L 0, the additional distortion is appreciable! The additional distortion is more sensitive to the value of L than to the

20、 value of S, For given value of L , the additional distortion is somewhat reduced as the value of S is increased. For given value of S , the additional distortion is somewhat increased as the value of L is increased. The highest value of the additional distortion in Table 3 is 70.71% when S=0 and L

21、=50%.Lecture 2精選ppt16o Additional Interference)1 (2221 ,LLSLtjSostTtRZZRevPdLLSLSLLSLtjSosrpTtRZZRevPdL11222,LLSLtjSostTtRTtRZZRevPSdLdL12221 ,LSLSLLSLTtjSosrpTtRTtRZZReVPIddLdL1)1 (222,2LSLSTtRTtRdLdLSI1dLdLdoLTtRTtRTtRISSIRoLoLLLoLLLILLRLSLSRRRRRRRRSIRSIRIISIRIISSIR1111111oLoLLRLSLSRRSIRSIRSIR11Le

22、cture 2精選ppt17 Table 4 Calculated ratio of signal to interference as the reflection coefficient, , is varied.S, L,% % dB W % W W dB0015 31.620.00000.00001.0015.005015 31.62 0.00000.00001.0015.0010015 31.620.00000.00001.0015.0020015 31.620.00000.00001.0015.0050015 31.62 0.00000.00001.0015.000515 31.6

23、20.00000.00001.0015.005515 31.620.00250.00251.0814.6710515 31.620.00500.00501.1614.3620515 31.620.01000.01011.3213.8050515 31.620.02500.02561.8112.4201015 31.620.00000.00001.0015.0051015 31.620.00500.00501.1614.36101015 31.620.01000.01011.3213.80201015 31.620.02000.02041.6512.84501015 31.620.05000.0

24、5262.6610.7402015 31.620.00000.00001.0015.0052015 31.620.01000.01011.3213.80102015 31.620.02000.02041.6512.84202015 31.620.04000.04172.3211.35502015 31.620.10000.11114.51 8.4505015 31.620.00000.00001.0015.0055015 31.620.02500.02561.8112.42105015 31.620.05000.05262.6610.74205015 31.620.10000.11114.51

25、 8.45505015 31.620.25000.333311.54 4.38oRLSIRoRLSIRLSLSLS1/oRLSLSLSIR11LRSIRLecture 2精選ppt18From Table 4 it can be seen that In cases where L = 0, there is no additional interference, so the SIR is kept unchanged. The additional interference is more sensitive to the value of L than to the value of S

26、, For a given value of L, the additional interference increases as the value of S increases so that the SIR is reduced. For a given value of S, the additional interference increases as the value of L increases so that the SIR is reduced. The highest value of the additional interference in Table 9.4

27、is reached when S=50% and L=50%. At this point the SIR drops from 15 dB to 4.38 dB.Lecture 2精選ppt19 o Maximizing of Power TransportationLSRR02132322LSLSSLSLLSSLRRRRRvRRRRRvRPL LLSSRRZZvvL 222LSLSLSRXXRRRvPL0LSXX, or, LSXX LSZZ*, or*LSZZ SSLSRRRvRvPPLL4422max, , or, 3. Impedance Conjugate Matching0S0

28、L22LSLSRRRRvPLFigure 5 Power delivered from a source to a load without reflectionS= 0L= 0ZoRSXS ZSSourcePSvS XL ZLLoadRLLRPLecture 2精選ppt20LSXXThis is called “neutralization” of reactance between source and load. 0SLvvo Power Transportation without Phase Shift Figure 6 Two matching cases when reacta

29、nce of source is “neutralized” by reactance of load, or, vice versa, that is, XS = -XL(a) RS in series with XS (b) RS in parallel with XS RL in series with XL RL in parallel with XLRSRLvS vLXSXL“Neutralization”of reactanceRSRLvL XLXS“Neutralization”of reactancevS Lecture 2精選ppt21(c) 8PSK(b) 4PSK(a)

30、BPSK(e) 16QAM(f) 64QAM9.46oFigure 7 Progress of modulation technology from PSK to QAM(d) 16PSK22.5o26.56oLecture 2精選ppt222max,*SRZZRvvvLLSLLSRZZRRvPPLLSL42max,*2max,*SRZZRvvvSLSSSSRZZRRvPPSLSS42max,*2max,max,SRRvvvSLSSLSRRRvRvPPSL4422max,max,LSRRSPPPSRRPPPSL21Lecture 2精選ppt23 A matching network must

31、 be inserted between source and load so that the impedance matching condition can be satisfied as following :o Impedance Matching Network*SinZZ*LoutZZ Usually*LSZZ RSvSXSSourcePSXLRLLoadFigure 8 An impedance matching network is inserted between source and load when ZS ZL* Impedance MatchingNetworkZi

32、nZoutZSZLPinPoutLRPSRPLecture 2精選ppt24SSRSRSSinSinininPRvRvRvRvP222244XLRLOld LoadRSvSXSOld SourcePSFigure 9 First sub- impedance matching loop: *New source = old source, *New load = Impedance matching network + old load Impedance Matching NetworkZinZoutZSZLPinPoutNew Source=Old sourceXinRinNew load

33、=Impedance matching network +old loadvinLRPSRPLecture 2精選ppt25Figure 10 Second sub- impedance matching loop: the impedance matching network itself Impedance MatchingNetworkZinZoutPinPoutRinXinRoutXoutoutoutoutinininPRvRvP22Lecture 2精選ppt26outoutoutLRRPRvRvPLL22RSvSXSOld SourcePSXLRLOld LoadFigure 11

34、 Third sub-impedance matching loop: * New source = Old source+ Impedance matching network * New load = Old load Impedance Matching NetworkZinZoutZSZLPinPoutNew load=Old loadXoutRoutNew source= old source + Impedance matching network LRPSRPLecture 2精選ppt27SRoutinRPPPPPLS21RSvSXSSourcePSXLRLLoadFigure

35、 12 An impedance matching network is inserted between source and load when ZS ZL* Impedance MatchingNetworkZinZoutZSZLPinPoutLRPSRPLecture 2精選ppt28o Necessity of Impedance MatchingIs this impedance matching network necessary ?Figure 13 A source follower (DC bias is neglected)VddInRoOutVddInRoImpedan

36、ceMatching Network OutZx(a) Primary source follower(b) “Improved” source follower?Is it necessary to insert an impedance matching network between two parts (Inductor, capacitor, resistor) ?Lecture 2精選ppt29(a) A primary MOSFET cascode amplifierCZeroBias 1Bias 2VddOutRF chokeRF chokeInRdM1M2Figure 14

37、A MOSFET cascode amplifier(b) An impedance matching network inserted between two stagesCZeroBias 1Bias 2VddOutRF chokeRF chokeInRdM1M2ImpedanceMatching NetworkIs this impedance matching network necessary ?Lecture 2精選ppt304. Additional effects of impedance matchingZLO in seriesZLO = 3.325k / 0.39pF i

38、n parallelFigure 15 Conversion of impedance at LO port of a mixer (f = 3.86 GHz)LOZLOLOZLODevice0.39 pF3.325 LOZLODevice3.325 ZLO 3.325k, if 0.39 pF is neutralized. (Measured) Is it necessary to match LO portion ? Some engineers design mixer without matching of LO portion. The reasons are Instead of

39、 power, only voltage is needed to ON/OFF the devices.As long as the runner from LO source to LO injection gate is short enough, the voltage from source would be directly effective on the gate.Or, one can simply put a 50 on LO injection gate for matching to 50 source.o Voltage Pumped Up by Impedance

40、MatchingLecture 2精選ppt31Rs=50 vgDevicevsVRs=50 DevicevgRs=50 Rg=50 vgDevicevsVvsVMatchingNetworkRs=50 vgDeviceRL=3.325 kRs=50 RL=3.325 kDevicevgvs=VRs=50 Rg=50 vgDeviceRL=3.325 kvs=VvsV(a) At LO port, the impedance matching is ignored.(b) At LO port, a 50 resistor is connected in parallel(At LO port

41、, impedance is well-matched by inserting of a matching network between the LO injection source and the LO injection port.)MatchingNetworkPs=0 dBmPs=0 dBmPs=0 dBmPs=0 dBmPs=0 dBmPs=0 dBmPg= -3 dBmLO portEquivalent circuitFigure 16 Three different ways for impedance matching at the LO port of a mixerL

42、ecture 2精選ppt32by power meter or spectrum analyzero Additional effects of impedance matching* Power MeasurementFigure 17 Output power of a tested block is measured by a power meter or a spectrum analyzer.PPEquivalentTested circuitvSZS*50 ZSPower meterOrSpectrum AnalyzerMatchNetwork(ZS* to 50 ohms)(a

43、) Matched caseEquivalentTested circuitvSPL50 ZSPower meterOrSpectrum Analyzer(b) Un-matched case PL50 Lecture 2精選ppt33* Power Measurement by spectrum analyzer (Matched case)LSoLZvPP42(a) Matched caseTested BlockvSZS*vL, PL50 ZSSpectrumAnalyzerMatchNetwork(ZS* to 50 )Figure 18 Power measurement by spectrum analyzerLecture 2精選pp