譯碼器的VHDL設計

1、3-8譯碼器的VHDL設計1.實體框圖2.程序設計正確的程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY DECODER38A IS PORT(A2,A1,A0,S1,S2,S3:IN STD_LOGIC; Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ENTITY DECODER38A;ARCHITECTURE ONE OF DECODER38A ISSIGNAL S: STD_LOGIC_VECTOR(5 DOWNTO 0); BEGINS<=A2&A1&A0&S1&S2

2、&S3; WITH S SELECT Y<="11111110" WHEN "000100", "11111101" WHEN "001100", "11111011" WHEN "010100", "11110111" WHEN "011100", "11101111" WHEN "100100", "11011111" WHEN "101100&qu

3、ot;, "10111111" WHEN "110100", "01111111" WHEN "111100", "11111111" WHEN OTHERS;END ARCHITECTURE ONE;3.仿真波形圖4.仿真波形分析當S1 S2 S3=100時，只有當A2 A1 A0=111時，Y7才輸出低電平，否則為高電平，當A2 A1 A0=110時，Y6才輸出低電平，否則為高電平，當A2 A1 A0=101時，Y5才輸出低電平，否則為高電平，Y4到Y0同理。可見該程序設計的是3-8譯碼器三

4、、共陽極數碼管七段顯示譯碼器的VHDL設計1.實體框圖2.程序設計正確的程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY DISPLAY_DECODER IS PORT(A3,A2,A1,A0:IN STD_LOGIC; Y:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END ENTITY DISPLAY_DECODER;ARCHITECTURE ONE OF DISPLAY_DECODER ISSIGNAL S: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGINS<=A3&A2&

5、;A1&A0; WITH S SELECT Y<="1111110" WHEN "0000", "0110000" WHEN "0001", "1101101" WHEN "0010", "1111001" WHEN "0011", "0110011" WHEN "0100", "1011011" WHEN "0101", "1011

6、111" WHEN "0110", "1110000" WHEN "0111", "1111111" WHEN "1000", "1111011" WHEN "1001", "0000000" WHEN OTHERS;END ARCHITECTURE ONE;3.仿真波形圖4.仿真波形分析由圖可知，當A3 A2 A1 A0=0000時，輸出Y6到Y0對應為1111110，即只有g不亮，數碼管顯示為0，A3 A2 A1 A0=0

7、001時，輸出對應為0110000，數碼管顯示為1，A3 A2 A1 A0=0010時，輸出對應為1101101，數碼管顯示為2，其他同理，當A3 A2 A1 A0>1001，即大于9，數碼管無顯示。由此可知，程序設計的是七段顯示譯碼管。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY COMPARE4 IS 四位比較器 PORT(IA_MORE_THAN_B:IN STD_LOGIC; 高位比較的標志位的輸入 IB_MORE_THAN_A:IN STD_LOGIC; IA_EQ

8、UAL_B:IN STD_LOGIC; A:IN STD_LOGIC_VECTOR(3 DOWNTO 0);兩個輸入 B:IN STD_LOGIC_VECTOR(3 DOWNTO 0); OA_MORE_THAN_B:OUT STD_LOGIC; OB_MORE_THAN_A:OUT STD_LOGIC; OA_EQUAL_B:OUT STD_LOGIC); END COMPARE4;ARCHITECTURE BEHAV OF COMPARE4 ISBEGIN PROCESS(IB_MORE_THAN_A, IA_EQUAL_B,IA_EQUAL_B) BEGIN IF(IA_EQUAL_B=

9、'1')THEN從最高位比較，如果高位大則停止比較輸出結果，否則進行下一位比較 IF(A(3)>B(3)THEN OA_MORE_THAN_B<='1'OB_MORE_THAN_A<='0'OA_EQUAL_B<='0' ELSIF(A(3)<B(3)THEN OA_MORE_THAN_B<='0'OB_MORE_THAN_A<='1'OA_EQUAL_B<='0' ELSIF(A(2)>B(2)THEN OA_MORE_THAN

10、_B<='1'OB_MORE_THAN_A<='0'OA_EQUAL_B<='0' ELSIF(A(2)<B(2)THEN OA_MORE_THAN_B<='0'OB_MORE_THAN_A<='1'OA_EQUAL_B<='0' ELSIF(A(1)>B(1)THEN OA_MORE_THAN_B<='1'OB_MORE_THAN_A<='0'OA_EQUAL_B<='0' ELSIF

11、(A(1)<B(1)THEN OA_MORE_THAN_B<='0'OB_MORE_THAN_A<='1'OA_EQUAL_B<='0' ELSIF(A(0)>B(0)THEN OA_MORE_THAN_B<='1'OB_MORE_THAN_A<='0'OA_EQUAL_B<='0' ELSIF(A(0)<B(0)THEN OA_MORE_THAN_B<='0'OB_MORE_THAN_A<='1'OA

12、_EQUAL_B<='0' ELSE 如果輸入中兩個數相等的標志位為0，則表明高位不相等，停止比較，輸出結果。 OA_MORE_THAN_B<='0'OB_MORE_THAN_A<='0'OA_EQUAL_B<='1' END IF; ELSEOA_MORE_THAN_B<=IA_MORE_THAN_B;OB_MORE_THAN_A<=IB_MORE_THAN_A;OA_EQUAL_B<=IA_EQUAL_B; END IF; END PROCESS;END BEHAV;LIBRARY I

13、EEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY  comparator IS  PORT ( CLK :  IN STD_LOGIC;         SIN :  IN STD_LOGIC_VECTOR (3 DOWNTO 0);           SJ :  IN ST

14、D_LOGIC_VECTOR (3 DOWNTO 0);           Q : OUT STD_LOGIC);END comparator;ARCHITECTURE behave OF comparator IS  SIGNAL SIN1 : INTEGER RANGE 0 TO 15;  SIGNAL SJ1  : INTEGER RANGE 0 TO 15;BEGINSIN1<= CONV_INTEGER(SIN); SJ1<= CONV_INTEGER(SJ);PROCESS(CLK )BEGIN  IF (CLK'EVENT AND CLK = '1') THEN  &#