數(shù)字系統(tǒng)設(shè)計(jì)補(bǔ)充講義數(shù)電cmos

1、Digital CircuitsLect補(bǔ)充-CMOS Gate劉 鵬浙江大學(xué)信息與電子工程學(xué)系liupeng May. 22, 2012MOS管結(jié)構(gòu)和符號(hào)MVistorV之當(dāng)結(jié)所以D-S間不導(dǎo)通. iD=0門(mén)電路 (2)FALL 2008ZDMCVDDVGS(th)N+|VGS(th)P|，CMOS 反相器VGS(th)N-NMOS的開(kāi)啟電壓VGS(th)P-PMOS的開(kāi)啟電壓VGS(th)N=|VGS(th)P|工作原理：1、輸入為低電平VVGS1VGS(th)N=0V時(shí)ILT1管截止；T2導(dǎo)通PMOS|VGS2| |VGS(th)P|電路中電流近似為零（忽略T1的截襯止底漏與電漏流源）間

2、,V的P主N結(jié)要始降終落處在于T反漏極相連做輸出端NMOS偏，NMOS管的襯DD底總是接到電1路上，輸出為高電平VOHVDD的最低電位，PMOS管的襯底總是2、輸入為高電平VIH = VDD時(shí)，接到電路的最高電位T1 通T2 止，VDD主要降在T2 上，柵極相連做輸入端輸出為低電平V 0V。OL實(shí)現(xiàn)邏輯“非”功能F = A門(mén)電路 (3)FALL 2008ZDMC與非門(mén)邏輯兩個(gè)并聯(lián)的MOS門(mén)電路PMOS管T3、T4止二輸入“與非”門(mén)電路結(jié)構(gòu)如圖通 1 當(dāng)A和B為高電:輸出低電平當(dāng)A和B有一個(gè)或一個(gè)以上 0 止為低電電路輸出: 1 通電路F兩NMOS聯(lián)的T1、T2門(mén)電路 (8)MC每個(gè)輸入端與一

3、個(gè)實(shí)NMOS管和一個(gè)PMOS 管的柵極相連或非門(mén)邏輯功能的CMOS門(mén)電路兩個(gè)串聯(lián)的PMOS管01VDD二輸入“或非”門(mén)電T1、T3止通T3當(dāng)A和B為低電:00A輸出高電平通T1當(dāng)A和B有一個(gè)或一個(gè)以上為01 Y高電:T4通T2電路輸出低電平電路實(shí)現(xiàn)“或非”邏輯功能F = A + B止止兩個(gè)并聯(lián)的NMOST1、T2門(mén)電路 (9)FALL 2008ZDMCTransistor-level Logic Circuits (inv)Vdd(NOT gate):Gndwhat is the relationship between in and out?Vddinout0 volts3 voltsGnd

4、門(mén)電路 (11)FALL 2008ZDMCLogical Values+3+3Logic 1Logic 0Input VoltageLogic 1Input VoltageVVoutLogic 000+5VinThresholdn Logical 1 (true) : V > Vdd V thn Logical 0 (false) : V < VthNoise margin?nnot( out, in)n門(mén)電路 (12)FALL 2008ZDMCinoutF TTFComputing with Switchesn Compose switches into more complex

5、 functions:(Boolean)BAANDZ º A and BAORZ º A or BBTwo fundamental structures: series (AND) and parallel (OR)門(mén)電路 (13)FALL 2008ZDMCTransistor-level Logic Circuits - NANDNAND gatenn Inverter (NOT gate):nand (out, a, b)aboutLogic Function:n001101011110out = 0 iff both a AND b = 1 therefore out

6、 = (ab)pFET network and nFET network are duals of one another.nnHow about AND gate?門(mén)電路 (14)FALL 2008ZDMCTransistor-level Logic CircuitsSimple rule for wiring up MOSFETs:nFET is used only to pass logic zero.pFet is used only to pass logic one. For example, NAND gate:nnnNote: This rule is sometimes vi

7、olatedby expert designers under special conditions.門(mén)電路(15)FALL 2008ZDMCTransistor-level Logic Circuits - NORNOR gatenNAND gatenFunction:nout = 0 iff both a OR b = 1 thereforeout = (a+b)Again pFET network and nFET network are duals of one another.Other more complex functions are possible. Ex: out = (

8、a+bc)aboutnnor (out, a, b)001101011000nn門(mén)電路 (16)FALL 2008ZDMCTransmission GateTransmission gates are the way to build “switches” in CMOS.Both transistor types are needed:n nFET to pass zeros.nnn pFET to pass ones.The transmission gate is bi-directional (unlike logic gatesnand tri-state buffers).Func

9、tionally it is similar to the tri-state buffer, but does not connect to Vdd and GND, so must be combined with logicngates or buffers.門(mén)電路 (20)FALL 2008ZDMCCMOS三態(tài)門(mén)1.電路組成VDDENT'13.原理：EN = 0,T '1 T '2 導(dǎo)通,Y = A Y AEN = 1,T '1 T '2 截止，Y為高阻態(tài)4.三態(tài)門(mén)的應(yīng)用主要應(yīng)用： 總線(xiàn)邏輯 雙向傳輸T'212.邏輯符號(hào)AYEN門(mén)電路 (

10、21)FALL 2008ZDMCT1T2Transistor-level Logic CircuitsTri-state BuffernTransistor circuit for inverting tri-state buffer:n“high impedance”(output disconnected)n VariationsInverting bufferInverted enable“transmission gate”Tri-state buffers are used when multiple circuits all connect to a common bus. Onl

11、y one circuit at a time is allowed to drive the bus. All others “disconnect”.門(mén)電路 (22)FALL 2008ZDMCTransistor-level Logic Circuits - MUXMultiplexorTransistor Circuit for inverting multiplexor:nnIf s=1 then c=b門(mén)電路 (23)FALL 2008ZDMCa else c=Unused InputsCMOS inputs should be never be left disconnected.

12、 All CMOS inputs must be tied either to a fixed voltage level (0V or VDD) or to another input.This rule applies even to the inputs of extra unused logic gates on a chip.An unconnected CMOS input is susceptible to noise and static charges that could easily bias both the P- channel and the N-channel MOSFETs in the conductive state, resulting in increased power dissipation and possible overheating.nnn門(mén)電路 (24)FALL 2008ZDMCCMOS電路的特點(diǎn)功耗?。篊MOS門(mén)工作時(shí)，總是一管導(dǎo)通另一管截止，