基于FPGA與PC串口自收發(fā)通信-Verilog

1、FPGA與PC串口自收發(fā)通信實(shí)現(xiàn)的功能如題，就是FPGA里實(shí)現(xiàn)從PC接收數(shù)據(jù)，然后把接收到的數(shù)據(jù)發(fā)回去。使用的是串口UART協(xié)議進(jìn)行收發(fā)數(shù)據(jù)。上位機(jī)用的是通用的串口調(diào)試助手。發(fā)送數(shù)據(jù)的波特率可選9600bps,19200bps,38400bps,57600bps,115200bps等，是可調(diào)的。發(fā)送格式為：1bit起始位，8bit數(shù)據(jù)，1bit停止位，無(wú)校驗(yàn)位。以下的代碼有比較詳細(xì)的注釋?zhuān)?jīng)過(guò)下載驗(yàn)證，存在誤碼率（<5%），僅供學(xué)習(xí)！代碼如下：（頂層模塊）：module my_uart_top(clk,rst_n,rs232_rx,rs232_tx);input clk;/ 50MHz主

2、時(shí)鐘input rst_n;/低電平復(fù)位信號(hào)input rs232_rx;/ RS232接收數(shù)據(jù)信號(hào)output rs232_tx;/RS232發(fā)送數(shù)據(jù)信號(hào)wire bps_start;/接收到數(shù)據(jù)后，波特率時(shí)鐘啟動(dòng)信號(hào)置位wire clk_bps;/ clk_bps的高電平為接收或者發(fā)送數(shù)據(jù)位的中間采樣點(diǎn) wire7:0 rx_data;/接收數(shù)據(jù)寄存器，保存直至下一個(gè)數(shù)據(jù)來(lái)到wire rx_int;/接收數(shù)據(jù)中斷信號(hào),接收到數(shù)據(jù)期間始終為高電平/-speed_selectspeed_select(.clk(clk),/波特率選擇模塊，接收和發(fā)送模塊復(fù)用，不支持全雙工通信.rst_n(rst

3、_n),.bps_start(bps_start),.clk_bps(clk_bps);my_uart_rxmy_uart_rx(.clk(clk),/接收數(shù)據(jù)模塊.rst_n(rst_n),.rs232_rx(rs232_rx),.clk_bps(clk_bps),.bps_start(bps_start),.rx_data(rx_data),.rx_int(rx_int);my_uart_txmy_uart_tx(.clk(clk),/發(fā)送數(shù)據(jù)模塊.rst_n(rst_n),.clk_bps(clk_bps),.rx_data(rx_data),.rx_int(rx_int),.rs232

4、_tx(rs232_tx),.bps_start(bps_start);endmodulemodule speed_select(clk,rst_n,bps_start,clk_bps);input clk;/ 50MHz主時(shí)鐘input rst_n;/低電平復(fù)位信號(hào)input bps_start;/接收到數(shù)據(jù)后，波特率時(shí)鐘啟動(dòng)信號(hào)置位output clk_bps;/ clk_bps的高電平為接收或者發(fā)送數(shù)據(jù)位的中間采樣點(diǎn) parameter bps9600 = 5207,/波特率為9600bpsbps19200 = 2603,/波特率為19200bpsbps38400 = 1301,/波特率

5、為38400bpsbps57600 = 867,/波特率為57600bpsbps115200= 433;/波特率為115200bpsparameter bps9600_2 = 2603,bps19200_2= 1301,bps38400_2= 650,bps57600_2= 433,bps115200_2 = 216;reg12:0 bps_para;/分頻計(jì)數(shù)最大值reg12:0 bps_para_2;/分頻計(jì)數(shù)的一半reg12:0 cnt;/分頻計(jì)數(shù)reg clk_bps_r;/波特率時(shí)鐘寄存器/-reg2:0 uart_ctrl;/ uart波特率選擇寄存器/-always (posed

6、ge clk or negedge rst_n) beginif(!rst_n) begin uart_ctrl <= 3'd0;/默認(rèn)波特率為9600bpsendelse begincase (uart_ctrl)/波特率設(shè)置3'd0:beginbps_para <= bps9600;bps_para_2 <= bps9600_2;end3'd1:beginbps_para <= bps19200;bps_para_2 <= bps19200_2;end3'd2:beginbps_para <= bps38400;bps_p

7、ara_2 <= bps38400_2;end3'd3:beginbps_para <= bps57600;bps_para_2 <= bps57600_2;end3'd4:beginbps_para <= bps115200;bps_para_2 <= bps115200_2;enddefault: ;endcaseendendalways (posedge clk or negedge rst_n)if(!rst_n) cnt <= 13'd0;else if(cnt<bps_para && bps_star

8、t) cnt <= cnt+1'b1;/波特率時(shí)鐘計(jì)數(shù)啟動(dòng)else cnt <= 13'd0;always (posedge clk or negedge rst_n)if(!rst_n) clk_bps_r <= 1'b0;else if(cnt=bps_para_2 && bps_start) clk_bps_r <= 1'b1;/ clk_bps_r高電平為接收或者發(fā)送數(shù)據(jù)位的中間采樣點(diǎn) else clk_bps_r <= 1'b0;assign clk_bps = clk_bps_r;endmodul

9、emodule my_uart_rx(clk,rst_n,rs232_rx,clk_bps,bps_start,rx_data,rx_int);input clk;/ 50MHz主時(shí)鐘input rst_n;/低電平復(fù)位信號(hào)input rs232_rx;/ RS232接收數(shù)據(jù)信號(hào)input clk_bps;/ clk_bps的高電平為接收或者發(fā)送數(shù)據(jù)位的中間采樣點(diǎn)output bps_start;/接收到數(shù)據(jù)后，波特率時(shí)鐘啟動(dòng)信號(hào)置位output7:0 rx_data;/接收數(shù)據(jù)寄存器，保存直至下一個(gè)數(shù)據(jù)來(lái)到 output rx_int;/接收數(shù)據(jù)中斷信號(hào),接收到數(shù)據(jù)期間始終為高電平/-reg

10、 rs232_rx0,rs232_rx1,rs232_rx2;/接收數(shù)據(jù)寄存器，濾波用wire neg_rs232_rx;/表示數(shù)據(jù)線接收到下降沿always (posedge clk or negedge rst_n) beginif(!rst_n) beginrs232_rx0 <= 1'b1;rs232_rx1 <= 1'b1;rs232_rx2 <= 1'b1;endelse beginrs232_rx0 <= rs232_rx;rs232_rx1 <= rs232_rx0;rs232_rx2 <= rs232_rx1;end

11、endassign neg_rs232_rx = rs232_rx2 & rs232_rx1;/接收到下降沿后neg_rs232_rx置高一個(gè)時(shí)鐘周期/-reg bps_start_r;reg3:0num;/移位次數(shù)reg rx_int;/接收數(shù)據(jù)中斷信號(hào),接收到數(shù)據(jù)期間始終為高電平always (posedge clk or negedge rst_n) beginif(!rst_n) beginbps_start_r <= 1'bz;rx_int <= 1'b0;endelse if(neg_rs232_rx) beginbps_start_r <

12、= 1'b1;/啟動(dòng)接收數(shù)據(jù) rx_int <= 1'b1;/接收數(shù)據(jù)中斷信號(hào)使能endelse if(num=4'd12) beginbps_start_r <= 1'bz;/數(shù)據(jù)接收完畢rx_int <= 1'b0;/接收數(shù)據(jù)中斷信號(hào)關(guān)閉endend assign bps_start = bps_start_r;/-reg7:0 rx_data_r;/接收數(shù)據(jù)寄存器，保存直至下一個(gè)數(shù)據(jù)來(lái)到/-reg7:0rx_temp_data;/但前接收數(shù)據(jù)寄存器reg rx_data_shift;/數(shù)據(jù)移位標(biāo)志always (posedge c

13、lk or negedge rst_n) beginif(!rst_n) beginrx_data_shift <= 1'b0;rx_temp_data <= 8'd0;num <= 4'd0;rx_data_r <= 8'd0;endelse if(rx_int) begin/接收數(shù)據(jù)處理if(clk_bps) begin/讀取并保存數(shù)據(jù),接收數(shù)據(jù)為一個(gè)起始位，8bit數(shù)據(jù)，一個(gè)結(jié)束位rx_data_shift <= 1'b1;num <= num+1'b1;if(num<=4'd8) rx_t

14、emp_data7 <= rs232_rx;/鎖存9bit（1bit起始位，8bit數(shù)據(jù)）endelse if(rx_data_shift) begin/數(shù)據(jù)移位處理rx_data_shift <= 1'b0;if(num<=4'd8) rx_temp_data <= rx_temp_data >> 1'b1;/移位8次，第1bit起始位移除，剩下8bit正好時(shí)接收數(shù)據(jù)else if(num=4'd12) beginnum <= 4'd0;/接收到STOP位后結(jié)束,num清零rx_data_r <= rx_

15、temp_data;/把數(shù)據(jù)鎖存到數(shù)據(jù)寄存器rx_data中endendendendassign rx_data = rx_data_r;endmodulemodule my_uart_tx(clk,rst_n,clk_bps,rx_data,rx_int,rs232_tx,bps_start);input clk;/ 50MHz主時(shí)鐘input rst_n;/低電平復(fù)位信號(hào)input clk_bps;/ clk_bps的高電平為接收或者發(fā)送數(shù)據(jù)位的中間采樣點(diǎn)input7:0 rx_data;/接收數(shù)據(jù)寄存器input rx_int;/接收數(shù)據(jù)中斷信號(hào),接收到數(shù)據(jù)期間始終為高電平,在次利用它的

16、下降沿來(lái)啟動(dòng)發(fā)送數(shù)據(jù)output rs232_tx;/ RS232發(fā)送數(shù)據(jù)信號(hào)output bps_start;/接收或者要發(fā)送數(shù)據(jù)，波特率時(shí)鐘啟動(dòng)信號(hào)置位/-reg rx_int0,rx_int1,rx_int2;/rx_int信號(hào)寄存器，捕捉下降沿濾波用wire neg_rx_int;/ rx_int下降沿標(biāo)志位always (posedge clk or negedge rst_n) beginif(!rst_n) beginrx_int0 <= 1'b0;rx_int1 <= 1'b0;rx_int2 <= 1'b0;endelse begin

17、rx_int0 <= rx_int;rx_int1 <= rx_int0;rx_int2 <= rx_int1;endendassign neg_rx_int =rx_int1 & rx_int2;/捕捉到下降沿后，neg_rx_int拉地保持一個(gè)主時(shí)鐘周期/-reg7:0 tx_data;/待發(fā)送數(shù)據(jù)的寄存器/-reg bps_start_r;reg tx_en;/發(fā)送數(shù)據(jù)使能信號(hào)，高有效reg3:0 num;always (posedge clk or negedge rst_n) beginif(!rst_n) beginbps_start_r <= 1&

18、#39;bz;tx_en <= 1'b0;tx_data <= 8'd0;endelse if(neg_rx_int) begin/接收數(shù)據(jù)完畢，準(zhǔn)備把接收到的數(shù)據(jù)發(fā)回去bps_start_r <= 1'b1;tx_data <= rx_data;/把接收到的數(shù)據(jù)存入發(fā)送數(shù)據(jù)寄存器tx_en <= 1'b1;/進(jìn)入發(fā)送數(shù)據(jù)狀態(tài)中endelse if(num=4'd11) begin/數(shù)據(jù)發(fā)送完成，復(fù)位bps_start_r <= 1'bz;tx_en <= 1'b0;endendassign bps_start = bps_start_r;/-reg rs232_tx_r;always (posedge clk or negedge rst_n) beginif(!rst_n) beginnum <= 4'd0;rs232_tx_r <= 1'b1;endelse if(tx_