數(shù)字時(shí)鐘外文翻譯

1、 外文資料翻譯L ED using digital tube digital display its high-brightness, indicating the advantages of intuitive intelligence is widely used in areas such as equipment and household appliances. AT89C52This article describes a single-chip microcomputer as the core, to a total of anode high-brightness LED L

2、 ED as a display composed of seven figures show that the practical design of multi-function electronic clocks, the clock shows a week, hour, minute, second, it can be switched to year, month, day showed that the whole point of music at the same time and from time to time the alarm time and other fun

3、ctions can also be used for electronic stopwatch.Clock circuit is the heart of the computer, which controls the rhythm of the work of the computer is through the completion of complex sequential circuits function in different directions.Clock, since it was invented that day on, people's lives ha

4、s become an indispensable tool, especially in this era of efficient, the clock is in the human production and living, learning and other fields is widely. However, with the passage of time, people not only to the requirements of the clock is getting higher and higher precision, and functional requir

5、ements for the clock more and more, the clock has not only a tool used to display time, in many practical applications It also needs to be able to achieve more other functions. Features such as alarm clock, calendar display, temperature measurement function, humidity measurements, voltage measuremen

6、ts, frequency measurements, have been under-voltage alarm function. Digital clocks to the people's production and life has brought great convenience, but also greatly expands the time feature the original clocks. Such as regular auto-alarm, Automatic time-ling, time process automation, from time

7、 to time broadcast, from closed-circuit automatic lights, oven timer switch, on-off power equipment, electrical and even a variety of timing is automatically enabled, all of which are based on digital clocks and watches based. It can be said that the design of the significance of multi-function Digi

8、tal Clock Digital Clock is not just itself, a greater significance of the multi-function digital clock in a number of real-time control systems. In many practical applications, as long as the digital clock circuit of the programs and hardware to a certain degree of modification could be useful for r

9、eal-time control system, which applied to the actual work and production to. Thus, digital clock and to expand its applications, has a very practical significance. With the development of human civilization, science and technology, there is the request of the clock continues to improve. Clock has no

10、t only seen as a tool to display the time, in many practical applications also need to be able to achieve more other functions. High-precision, multifunction, small size, low power consumption, is the development trend of the modern clock. In this trend, digital clock, multifunction clock has become

11、 the modern design of the production of research-led direction. This article is based on this design direction for the control of a single-chip core design requirements of a multi-function indicators in line with the digital clock. The design is based on the principle of single-chip technology to ch

12、ip AT89C52single-chip microcomputer as the core controller, through the production of hardware and software procedures for the preparation, design to produce a multi-functional digital clock system. The clock system mainly by clock module, alarm module, the ambient temperature detection module, liqu

13、id crystal display module, control module and the keyboard signal prompted module. System is simple and clear user interface that can 4V 7V DC power under normal operation. Able to accurately display time (display format hh: mm: seconds seconds, 24-hour system), may be time to adjust at any time, wi

14、th clock time settings, alarm on / off, only to make functions, where the clock to measure the ambient temperature and displayed. Hardware and software design into the guiding ideology, give full play to the single-chip features, most of the functions through software programming to achieve, the cir

15、cuit is simple and clear, high system stability. At the same time, the clock system also has the power of small, low cost, and highly practical. System components as a result of less use, single-chip occupied by the I / O port not more than, the system has a certain degree of scalability.Clock desig

16、n is no theory of discrete logic, programmable logic, or using full-custom silicon devices of any digital design, in order to successfully operate and reliable clock is crucial. Poor design of the clock in the limits of temperature, voltage deviation or the manufacturing process will result in the c

17、ase wrong, and debugging difficult, spending a lot. In the design of FPGA / CPLD clock when several types of commonly used. Clock can be divided into the following four types: global clock, clock gating, multi-level logic clock clock and volatility. Multi-clock system to include the above-mentioned

18、four types of any combination of the clock. No matter what methods are the real circuit clock tree can not achieve the ideal assumption that the clock, so we must be based on an ideal clock, the clock real work to build a model to analyze the circuit, so as to make the circuit performance and the pr

19、actical work as expected . Clock in the actual model, we have to consider the spread of clock-tree skew, vertical jump and absolute bias and other uncertainties. To register, the clock was working along the arrival of the data terminal when it should have been stable, so as to ensure that the work a

20、long the sampling clock to the accuracy of the data, this data preparation time that we call set-up time (setup time). Data should also be working along the clock to maintain over a period of time, this period of time known as the hold time (hold time). Global clock for a design project, the global

21、clock (or clock synchronous) is the simplest and most predictable clock. In the PLD / FPGA design of the clock the best options are: by a dedicated global clock input pins of a single master clock-driven clock design projects to each flip-flop. As long as possible should be used in the design of glo

22、bal clock projects. PLD / FPGA has a dedicated global clock pins, the device is directly connected to each register. Global clock to provide such a device in the shortest possible delay to the output clock. Clock-gated in many applications, the entire design of the overall use of external clock is n

23、ot possible or practical. With the product of PLD logic array clock (that is, the clock is generated by the logic), to allow arbitrary function alone all trigger clock. However, when you use the array clock, the clock should be carefully analyzed the function, in order to avoid glitches. Usually con

24、stitute the array clock clock-gated. Clock gating often interface with the microprocessor, and used the address to write to control the pulse line. However, when using combination of flip-flop when the clock function, usually there is a clock-gated. If the following conditions, such as clock gating

25、can be as reliable as global clock work: Drive the clock logic must contain only one "and" the door or a "or" gate. If any additional work in some state of logic, the competition will be the burr. A logic gate input as the actual clock, and the logic gate must be of all other inp

26、ut as the address or control lines, in relation to their compliance with the establishment and maintenance of clock time bound. Multi-level logic generated clock when the clock-gating logic of the combination of more than one (or more than the individual "and" doors or "or" gate)

27、, the evidence of the reliability of the design of the project has become very difficult. Even if the prototype or simulation results show that there is no static dangerous, but in fact the risk may still exist. In general, we should not use multi-level combinational logic to clock the flip-flop in

28、the PLD design. Traveling-wave clock clock another popular use of traveling-wave circuit is the clock, that is, the output of a flip-flop used as a clock input of another flip-flop. If careful design, traveling-wave clock can be the same as the global clock to work reliably. However, the traveling-w

29、ave clock made from time to time with the calculation of the circuit becomes very complicated. Line-wave traveling-wave clock flip-flop of the chain have a greater clock time between the offset and exceed the worst case the set-up time, hold time and clock to the output circuit of the delay, allowin

30、g the system to the actual slowed down. Multi-clock system, many system requirements within the same multi-PLD clock. The most common example is the two asynchronous interfaces between microprocessors, or microprocessors and asynchronous communication channel interface. As the clock signal between t

31、he two requirements to establish and maintain a certain time, so that the above application from time to time the introduction of additional constraints. They also requested that some asynchronous synchronization signal. In many applications, only the synchronization of asynchronous signals is not e

32、nough, when the system of two or more non-homologous clock, the data it is difficult to establish and maintain the time to be assured that we will face the complex matter of time . The best way is to all non-homologous clock synchronization. PLD internal use of the lock loop (PLL or DLL) is a very g

33、ood, but not all of PLD with a PLL, DLL, and chip PLL with most expensive, so unless there are special requirements, the general occasions PLL can not use with the PLD.At this time we need to take to enable the use of the D flip-flop-side, and the introduction of a high-frequency clock. 采用L ED 數(shù)碼管的數(shù)

34、字顯示以其亮度高、顯示直觀等優(yōu)點(diǎn)被廣泛應(yīng)用于智能儀器及家用電器等領(lǐng)域. 本文介紹一種以AT89C52單片機(jī)為核心,以共陽極高亮度L ED 數(shù)碼管作為顯示器件組成7 位數(shù)字顯示的實(shí)用多功能電子時(shí)鐘的設(shè)計(jì),該時(shí)鐘可顯示星期、時(shí)、分、秒,也可切換為年、月、日顯示,同時(shí)具有整點(diǎn)音樂報(bào)時(shí)及定時(shí)鬧鐘等功能,也可作電子秒表使用。時(shí)鐘電路是計(jì)算機(jī)的心臟, 它控制著計(jì)算機(jī)的工作節(jié)奏就是通過復(fù)雜的時(shí)序電路完成不同的指令功能的。時(shí)鐘，自從它被發(fā)明的那天起，就成為人們生活中必不可少的一種工具，尤其是在現(xiàn)在這個(gè)講究效率的年代，時(shí)鐘更是在人類生產(chǎn)、生活、學(xué)習(xí)等多個(gè)領(lǐng)域得到廣泛的應(yīng)用。然而隨著時(shí)間的推移，人們不僅對于時(shí)鐘精

35、度的要求越來越高，而且對于時(shí)鐘功能的要求也越來越多，時(shí)鐘已不僅僅是一種用來顯示時(shí)間的工具，在很多實(shí)際應(yīng)用中它還需要能夠?qū)崿F(xiàn)更多其它的功能。諸如鬧鐘功能、日歷顯示功能、溫度測量功能、濕度測量功能、電壓測量功能、頻率測量功能、過欠壓報(bào)警功能等。鐘表的數(shù)字化給人們的生產(chǎn)生活帶來了極大的方便，而且大大地?cái)U(kuò)展了鐘表原先的報(bào)時(shí)功能。諸如定時(shí)自動報(bào)警、按時(shí)自動打鈴、時(shí)間程序自動控制、定時(shí)廣播、自動起閉路燈、定時(shí)開關(guān)烘箱、通斷動力設(shè)備、甚至各種定時(shí)電氣的自動啟用等，所有這些，都是以鐘表數(shù)字化為基礎(chǔ)的?？梢哉f，設(shè)計(jì)多功能數(shù)字時(shí)鐘的意義已不只在于數(shù)字時(shí)鐘本身，更大的意義在于多功能數(shù)字時(shí)鐘在許多實(shí)時(shí)控制系統(tǒng)中的應(yīng)用

36、。在很多實(shí)際應(yīng)用中，只要對數(shù)字時(shí)鐘的程序和硬件電路加以一定的修改，便可以得到實(shí)時(shí)控制的實(shí)用系統(tǒng)，從而應(yīng)用到實(shí)際工作與生產(chǎn)中去。因此，研究數(shù)字時(shí)鐘及擴(kuò)大其應(yīng)用，有著非常現(xiàn)實(shí)的意義。隨著人類科技文明的發(fā)展，人們對于時(shí)鐘的要求在不斷地提高。時(shí)鐘已不僅僅被看成一種用來顯示時(shí)間的工具，在很多實(shí)際應(yīng)用中它還需要能夠?qū)崿F(xiàn)更多其它的功能。高精度、多功能、小體積、低功耗，是現(xiàn)代時(shí)鐘發(fā)展的趨勢。在這種趨勢下，時(shí)鐘的數(shù)字化、多功能化已經(jīng)成為現(xiàn)代時(shí)鐘生產(chǎn)研究的主導(dǎo)設(shè)計(jì)方向。本文正是基于這種設(shè)計(jì)方向，以單片機(jī)為控制核心，設(shè)計(jì)制作一個(gè)符合指標(biāo)要求的多功能數(shù)字時(shí)鐘。本設(shè)計(jì)基于單片機(jī)技術(shù)原理，以單片機(jī)芯片AT89C52作為核

37、心控制器，通過硬件電路的制作以及軟件程序的編制，設(shè)計(jì)制作出一個(gè)多功能數(shù)字時(shí)鐘系統(tǒng)。該時(shí)鐘系統(tǒng)主要由時(shí)鐘模塊、鬧鐘模塊、環(huán)境溫度檢測模塊、液晶顯示模塊、鍵盤控制模塊以及信號提示模塊組成。系統(tǒng)具有簡單清晰的操作界面，能在4V7V直流電源下正常工作。能夠準(zhǔn)確顯示時(shí)間（顯示格式為時(shí)時(shí)：分分：秒秒，24小時(shí)制），可隨時(shí)進(jìn)行時(shí)間調(diào)整，具有鬧鐘時(shí)間設(shè)置、鬧鐘開/關(guān)、止鬧功能，能夠?qū)r(shí)鐘所在的環(huán)境溫度進(jìn)行測量并顯示。設(shè)計(jì)以硬件軟件化為指導(dǎo)思想，充分發(fā)揮單片機(jī)功能，大部分功能通過軟件編程來實(shí)現(xiàn)，電路簡單明了，系統(tǒng)穩(wěn)定性高。同時(shí)，該時(shí)鐘系統(tǒng)還具有功耗小、成本低的特點(diǎn)，具有很強(qiáng)的實(shí)用性。由于系統(tǒng)所用元器件較少，單片

38、機(jī)所被占用的I/O口不多，因此系統(tǒng)具有一定的可擴(kuò)展性。時(shí)鐘設(shè)計(jì)無淪是用離散邏輯、可編程邏輯，還是用全定制硅器件實(shí)現(xiàn)的任何數(shù)字設(shè)計(jì)，為了成功地操作，可靠的時(shí)鐘是非常關(guān)鍵的。設(shè)計(jì)不良的時(shí)鐘在極限的溫度、電壓或制造工藝的偏差情況下將導(dǎo)致錯(cuò)誤的行為，并且調(diào)試?yán)щy、花銷很大。在設(shè)計(jì)FPGA/CPLD時(shí)通常采用幾種時(shí)鐘類型。時(shí)鐘可分為如下四種類型：全局時(shí)鐘、門控時(shí)鐘、多級邏輯時(shí)鐘和波動式時(shí)鐘。多時(shí)鐘系統(tǒng)能夠包括上述四種時(shí)鐘類型的任意組合。無論采用何種方式，電路中真實(shí)的時(shí)鐘樹也無法達(dá)到假定的理想時(shí)鐘，因此我們必須依據(jù)理想時(shí)鐘，建立一個(gè)實(shí)際工作時(shí)鐘模型來分析電路，這樣才可以使得電路的實(shí)際工作效果和預(yù)期的一樣。在實(shí)際的時(shí)鐘模型中，我們要考慮時(shí)鐘樹傳播中的偏斜、跳變和