VHDL與數(shù)字系統(tǒng)課程設(shè)計簡單處理器設(shè)計

1、 課程設(shè)計報告實踐課題： VHDL與數(shù)字系統(tǒng)課程設(shè)計 學(xué) 生： XXX 指導(dǎo)老師： XXX、XXX 系 別： 電子信息與電氣工程系 專 業(yè)： 電子科學(xué)與技術(shù) 班 級： XXX 學(xué) 號： XXX 一、設(shè)計任務(wù) 用VHDL設(shè)計一個簡單的處理器，并完成相關(guān)的仿真測試。 .設(shè)計要求：圖1是一個處理器的原理圖，它包含了一定數(shù)量的寄存器、一個復(fù)用器、一個加法/減法器（Addsub）,一個計數(shù)器和一個控制單元。圖1 簡單處理器的電路圖數(shù)據(jù)傳輸實現(xiàn)過程：16位數(shù)據(jù)從DIN輸入到系統(tǒng)中，可以通過復(fù)用器分配給R0R7和A，復(fù)用器也允許數(shù)據(jù)從一個寄存器傳通過Bus送到另外一個寄存器。加法和減法的實現(xiàn)過程：復(fù)用器先將

2、一個數(shù)據(jù)通過總線放到寄存器A中，然后將另一個數(shù)據(jù)放到總線上，加法/減法器對這兩個數(shù)據(jù)進行運算，運算結(jié)果存入寄存器G中，G中的數(shù)據(jù)又可根據(jù)要求通過復(fù)用器轉(zhuǎn)存到其他寄存器中。下表是該處理所支持的指令。操作功能mv Rx, Rymvi Rx, #Dadd Rx, Rysub Rx, RyRx RyRx DataRx Rx + RyRx Rx - Ry1） Rx Ry :將寄存器Ry中的內(nèi)容復(fù)制到Rx；2） Mvi Rx，#D ：將立即數(shù)存入寄存器Rx中去。 所有指令都按9位編碼（取自DIN的高9位）存儲在指令存儲器IR中，編編碼規(guī)則為IIIXXXYYY，III表示指令，XXX表示Rx寄存器，YYY表

3、示Ry寄存器。立即數(shù)#D是在mvi指令存儲到IR中之后，通過16位DIN輸入的。 有一些指令，如加法指令和減法指令，需要在總線上多次傳輸數(shù)據(jù)，因此需要多個時鐘周期才能完成?？刂茊卧褂昧艘粋€兩位計數(shù)器來區(qū)分這些指令執(zhí)行的每一個階段。當(dāng)Run信號置位時，處理器開始執(zhí)行DIN輸入指令。當(dāng)指令執(zhí)行結(jié)束后，Done信號置位，下表列出四個指令在執(zhí)行過程中每一個時間段置位的控制信號。時間指令T0T1T2T3(mv):I0(mvi):I1(add):I2(sub):I3IRinIRinIRinIRinRYout,RXin,DoneDINout,RXin,DoneRXout,AinRXout,Ain-RYou

4、t,Gin,AddsubRYout,Gin,Addsub-Gout,RXin,DoneGout,RXin,Done二、實現(xiàn)功能說明2.1 mv Rx,Ry實現(xiàn)的功能：將寄存器Rx的值賦給寄存器Ry（以mv R0, R5為例）（1 ）計數(shù)器為“00”時,指令寄存器的置位控制信號輸入端IRin=1有效，將DIN輸入的數(shù)據(jù)的高9位鎖存。置位的控制信號如圖3加粗黑線所示。圖3（2）計數(shù)器為“01”時,首先控制單元根據(jù)設(shè)計器為“00”時輸入的指令，向復(fù)用器發(fā)出選通控制信號，復(fù)用器根據(jù)該控制信號讓R5的值輸出到總線上，然后控制單元控制寄存器R0將總線上的值鎖存，完成整個寄存器對寄存器的賦值過程。置位的控制

5、信號和數(shù)據(jù)流如圖4加粗黑線所示。圖42.2 mvi Rx,#D實現(xiàn)的功能：將的立即數(shù)#D賦給寄存器Rx（以mv R0, #D為例）（1）計數(shù)器為“00”時,指令寄存器的置位控制信號輸入端IRin=1有效，將DIN輸入的數(shù)據(jù)的高9位鎖存。置位的控制信號如圖5加粗黑線所示。圖5（2）計數(shù)器為“01”時,首先控制單元根據(jù)設(shè)計器為“00”時輸入的指令，向復(fù)用器發(fā)出選通控制信號，復(fù)用器根據(jù)該控制信號讓DIN的值輸出到總線上，然后控制單元控制寄存器R0將總線上的值鎖存，完成整個立即數(shù)對寄存器的賦值過程。置位的控制信號和數(shù)據(jù)流如圖6加粗黑線所示。圖62.3 add Rx,Ry和sub Rx,Ry實現(xiàn)的功能：

6、將寄存器Ry的值加上/減去寄存器Rx的值并賦給寄存器Rx（以add/sub R0,R1為例）。（1）計數(shù)器為“00”時,指令寄存器的置位控制信號輸入端IRin=1有效，將DIN輸入的數(shù)據(jù)的高9位鎖存。置位的控制信號如圖7加粗黑線所示。圖7（2）計數(shù)器為“01”時,首先控制單元根據(jù)設(shè)計器為“00”時輸入的指令，向復(fù)用器發(fā)出選通控制信號，復(fù)用器根據(jù)該控制信號讓R0的值輸出到總線上，然后控制單元控制寄存器A將總線上的值鎖存。置位的控制信號和數(shù)據(jù)流如圖8加粗黑線所示。圖8（3）計數(shù)器為“10”時,首先控制單元根據(jù)設(shè)計器為“00”時輸入的指令，向復(fù)用器發(fā)出選通控制信號，復(fù)用器根據(jù)該控制信號讓R1的值輸出

7、到總線上，然后控制單元控制加法/減法器addsub將寄存器A的值和總線上的值相加/相減并輸出，接著寄存器G將加法/減法器addsub的計算結(jié)果鎖存。置位的控制信號和數(shù)據(jù)流如圖9加粗黑線所示。圖9（4）計數(shù)器為“11”時,首先控制單元向復(fù)用器發(fā)出選通控制信號，復(fù)用器根據(jù)該控制信號讓寄存器G的值輸出到總線上，寄存器R0將總線上的值進行鎖存，完成整個寄存器與對寄存器見加減法的運算過程。置位的控制信號和數(shù)據(jù)流如圖10加粗黑線所示。圖10三、單元模塊設(shè)計說明4.1寄存器Registe寄存器R0R7、寄存器A或寄存器G : 用于數(shù)據(jù)的存儲。當(dāng)時鐘輸入clk的上升沿到來且rin=1時，將數(shù)據(jù)輸入端rxin1

8、5.0的數(shù)據(jù)鎖存到寄存器中并從數(shù)據(jù)輸出端rxout15.0輸出；當(dāng)rin=0時，輸出端保持原來的值不變。寄存器Registe的VHDL代碼： LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY registe isport( clk:in std_logic; rin:in std_logic; rxin:in std_logic_vector(15 downto 0); rxout:out std_logic_vector(15 downto 0);end entity registe;architecture one of registe isb

9、egin process(clk) begin if clk'event and clk='1' then if rin='1' then rxout<=rxin; end if; end if; end process;end one;4.2指令寄存器IR指令寄存器IR用于對輸入的16為指令進行處理，取其高9位。當(dāng)時鐘輸入clk的上升沿到來且rin=1時，取數(shù)據(jù)輸入端rxin15.0的高9位將其鎖存到寄存器中并從數(shù)據(jù)輸出端rxout8.0輸出；當(dāng)rin=0時，輸出端保持原來的值不變。指令寄存器IR的VHDL代碼：LIBRARY IEEE;USE

10、IEEE.STD_LOGIC_1164.ALL;ENTITY IR isport( clk:in std_logic; rin:in std_logic; rxin:in std_logic_vector(15 downto 0); rxout:out std_logic_vector(8 downto 0);end entity IR;architecture one of IR isbegin process(clk) begin if clk'event and clk='1' then if rin='1' then rxout<=rxin

11、(15 downto 7); end if; end if; end process;end one;4.3加/減法器addsub加/減法器addsub用于處理兩個輸入的數(shù)據(jù)datain215.0 和datain115.0，當(dāng)控制端Addsub=1時，兩個數(shù)據(jù)輸入端datain215.0 和datain115.0相加并從數(shù)據(jù)輸出端dataout15.0輸出；當(dāng)控制端Addsub=0時，數(shù)據(jù)輸入端datain215.0 減去datain115.0，結(jié)果從數(shù)據(jù)輸出端dataout15.0輸出。 加/減法器addsub的VHDL代碼：LIBRARY IEEE;USE IEEE.STD_LOGIC_1

12、164.ALL;use ieee.std_logic_unsigned.all;ENTITY addsub isport( ain:in std_logic_vector(15 downto 0); bin:in std_logic_vector(15 downto 0); adsub:in bit; about:out std_logic_vector(15 downto 0);end entity addsub;architecture one of addsub issignal a,b:std_logic_vector(15 downto 0);beginprocess(adsub,a

13、in,bin)beginif adsub='0' then about<=ain+bin;elsif adsub='1' then about<=ain-bin;end if;end process;end one; 4.4 計數(shù)器 counter計數(shù)器counter用于產(chǎn)生控制單元的輸入脈沖，對控制單元的工作時序進行控制。當(dāng)clear=0時（清零端clear無效），時鐘輸入clk每來一個上升沿，輸出count1.0加1， 所以輸出為00>01>10>11>00不斷循環(huán)；當(dāng)clear=1時（清零端clear有效），對輸出Q1.

14、0同步清零，與時鐘有關(guān)。 計數(shù)器counter的VHDL代碼：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter isport( clk:in std_logic; clear:in std_logic; count:out std_logic_vector(1 downto 0);end counter;architecture one of counter issignal c:std_logic_vector(1 downto 0);beginprocess(clk

15、,clear)begin if clk'event and clk='1' then if(clear='1')then c<="00" else c<=c+1;end if; end if;end process; count<=c;end one; 4.5 復(fù)用器 multiplexers復(fù)用器根據(jù)控制單元的控制信號將指定的輸入數(shù)據(jù)輸出到總線上。來自控制單元的控制信號為R0outR7out、Gout、DINout，輸入數(shù)據(jù)位來自寄存器R0R7、寄存器A、數(shù)據(jù)輸入端DIN，當(dāng)控制信號的某一位為1時，將其對應(yīng)的輸入數(shù)

16、據(jù)輸出到總線上。復(fù)用器 multiplexers的VHDl代碼：library ieee;use ieee.std_logic_1164.all;entity multiplexers isport ( din:in std_logic_vector(15 downto 0); gin:in std_logic_vector(15 downto 0); r0:in std_logic_vector(15 downto 0);r1:in std_logic_vector(15 downto 0);r2:in std_logic_vector(15 downto 0);r3:in std_logi

17、c_vector(15 downto 0);r4:in std_logic_vector(15 downto 0);r5:in std_logic_vector(15 downto 0);r6:in std_logic_vector(15 downto 0);r7:in std_logic_vector(15 downto 0); ren:in bit_vector(7 downto 0); gen:in bit; dinen:in bit; dout:out std_logic_vector(15 downto 0);end multiplexers;architecture bhv of

18、multiplexers isbegindout<=gin when gen='1' else r0 when ren(0)='1' else r1 when ren(1)='1' else r2 when ren(2)='1' else r3 when ren(3)='1' else r4 when ren(4)='1' else r5 when ren(5)='1' else r6 when ren(6)='1' else r7 when ren(7)=&#

19、39;1' else din when dinen='1' else "0000000000000000"end bhv;4.6控制單元control控制單元根據(jù)計數(shù)器發(fā)出的脈沖和DIN輸入的操作指令對整個系統(tǒng)的其他模塊進行控制，完成指定的操作。控制單元control的VHDL代碼：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity control isport( reset:in std_logic; run:in std_logic; cl

20、k:in std_logic_vector(1 downto 0); irin:in std_logic_vector(8 downto 0); clear:out std_logic; irout:out std_logic; gout:out std_logic; dinout:out std_logic; rout:out std_logic_vector(7 downto 0); r0in:out std_logic; r1in:out std_logic; r2in:out std_logic; r3in:out std_logic; r4in:out std_logic; r5in

21、:out std_logic; r6in:out std_logic; r7in:out std_logic; ain:out std_logic; addsub:out std_logic; gin:out std_logic; done:out std_logic);end control;architecture one of control isbeginprocess(clk,run,reset,irin)begin if(reset='0')then clear<='1' irout<='0' gout<='

22、0' dinout<='0' rout<="00000000" r0in<='0' r1in<='0' r2in<='0' r3in<='0' r4in<='0' r5in<='0' r6in<='0' r7in<='0' ain<='0' addsub<='0' gin<='0' done<=

23、'0' else case clk is when"00"=> clear<='0' irout<='1' gout<='0' dinout<='1' rout<="00000000" r0in<='0' r1in<='0' r2in<='0' r3in<='0' r4in<='0' r5in<='0' r6i

24、n<='0' r7in<='0' ain<='0' addsub<='0' gin<='0' done<='0' if run='0' then irout<='1' else irout<='0'end if;when"01"=> if(irin(8 downto 6)="000")then clear<='1' irout<=&

25、#39;0' gout<='0' dinout<='0' ain<='0' addsub<='0' gin<='0' done<='1'case irin(5 downto 3) is when"000"=>r0in<='1'r1in<='0'r2in<='0'r3in<='0'r4in<='0'r5in<='

26、;0'r6in<='0'r7in<='0'when"001"=>r1in<='1'r0in<='0'r2in<='0'r3in<='0'r4in<='0'r5in<='0'r6in<='0'r7in<='0'when"010"=>r2in<='1'r0in<='0'r1in&

27、lt;='0'r3in<='0'r4in<='0'r5in<='0'r6in<='0'r7in<='0'when"011"=>r3in<='1'r0in<='0'r1in<='0'r2in<='0'r4in<='0'r5in<='0'r6in<='0'r7in<='0'w

28、hen"100"=>r4in<='1'r0in<='0'r1in<='0'r2in<='0'r3in<='0'r5in<='0'r6in<='0'r7in<='0'when"101"=>r5in<='1'r0in<='0'r1in<='0'r2in<='0'r3in<='

29、;0'r4in<='0'r6in<='0'r7in<='0'when"110"=>r6in<='1'r0in<='0'r1in<='0'r2in<='0'r3in<='0'r4in<='0'r5in<='0'r7in<='0'when"111"=>r7in<='1'r0in&

30、lt;='0'r1in<='0'r2in<='0'r3in<='0'r4in<='0'r5in<='0'r6in<='0'when others=>null;end case;case irin(2 downto 0)is when"000"=>rout<="00000001" when"001"=>rout<="00000010" whe

31、n"010"=>rout<="00000100" when"011"=>rout<="00001000" when"100"=>rout<="00010000" when"101"=>rout<="00100000" when"110"=>rout<="01000000" when"111"=>rout<=

32、"10000000" when others=>null;end case; elsif(irin(8 downto 6)="001")then clear<='1' irout<='0' gout<='0' dinout<='1' rout<="00000000" ain<='0' addsub<='0' gin<='0' done<='1' ca

33、se irin(5 downto 3) is when"000"=>r0in<='1'r1in<='0'r2in<='0'r3in<='0'r4in<='0'r5in<='0'r6in<='0'r7in<='0'when"001"=>r1in<='1'r0in<='0'r2in<='0'r3in<=

34、'0'r4in<='0'r5in<='0'r6in<='0'r7in<='0'when"010"=>r2in<='1'r0in<='0'r1in<='0'r3in<='0'r4in<='0'r5in<='0'r6in<='0'r7in<='0'when"011"=>r

35、3in<='1'r0in<='0'r1in<='0'r2in<='0'r4in<='0'r5in<='0'r6in<='0'r7in<='0'when"100"=>r4in<='1'r0in<='0'r1in<='0'r2in<='0'r3in<='0'r5in<='0&#

36、39;r6in<='0'r7in<='0'when"101"=>r5in<='1'r0in<='0'r1in<='0'r2in<='0'r3in<='0'r4in<='0'r6in<='0'r7in<='0'when"110"=>r6in<='1'r0in<='0'r1in<=

37、'0'r2in<='0'r3in<='0'r4in<='0'r5in<='0'r7in<='0'when"111"=>r7in<='1'r0in<='0'r1in<='0'r2in<='0'r3in<='0'r4in<='0'r5in<='0'r6in<='0'when

38、others=>null; end case; elsif(irin(8 downto 6)="010" or irin(8 downto 6)="011")then clear<='0' irout<='0' gout<='0' dinout<='0' r0in<='0' r1in<='0' r2in<='0' r3in<='0' r4in<='0'

39、r5in<='0' r6in<='0' r7in<='0' ain<='1' addsub<='0' gin<='0' done<='0'case irin(5 downto 3)is when"000"=>rout<="00000001" when"001"=>rout<="00000010" when"010"=&g

40、t;rout<="00000100" when"011"=>rout<="00001000" when"100"=>rout<="00010000" when"101"=>rout<="00100000" when"110"=>rout<="01000000" when"111"=>rout<="10000000"

41、; when others=>null;end case; else clear<='1' irout<='0' gout<='0' dinout<='0' rout<="00000000" r0in<='0' r1in<='0' r2in<='0' r3in<='0' r4in<='0' r5in<='0' r6in<='0

42、9; r7in<='0' ain<='0' addsub<='0' gin<='0' done<='0' end if;when"10"=> if(irin(8 downto 6)="010")then clear<='0' irout<='0' gout<='0' dinout<='0' r0in<='0' r1in<=&#

43、39;0' r2in<='0' r3in<='0' r4in<='0' r5in<='0' r6in<='0' r7in<='0' ain<='0' addsub<='0' gin<='1' done<='0'case irin(2 downto 0)is when"000"=>rout<="00000001" whe

44、n"001"=>rout<="00000010" when"010"=>rout<="00000100" when"011"=>rout<="00001000" when"100"=>rout<="00010000" when"101"=>rout<="00100000" when"110"=>rout<=

45、"01000000" when"111"=>rout<="10000000" when others=>null;end case; elsif(irin(8 downto 6)="011")then clear<='0' irout<='0' gout<='0' dinout<='0' r0in<='0' r1in<='0' r2in<='0'

46、 r3in<='0' r4in<='0' r5in<='0' r6in<='0' r7in<='0' ain<='0' addsub<='1' gin<='1' done<='0'case irin(2 downto 0)is when"000"=>rout<="00000001" when"001"=>rout<=

47、"00000010" when"010"=>rout<="00000100" when"011"=>rout<="00001000" when"100"=>rout<="00010000" when"101"=>rout<="00100000" when"110"=>rout<="01000000" when"

48、;111"=>rout<="10000000" when others=>null;end case; else clear<='1' irout<='0' gout<='0' dinout<='0' rout<="00000000" r0in<='0' r1in<='0' r2in<='0' r3in<='0' r4in<='0&#

49、39; r5in<='0' r6in<='0' r7in<='0' ain<='0' addsub<='0' gin<='0' done<='0' end if;when"11"=> if(irin(8 downto 6)="010" or irin(8 downto 6)="011")then clear<='0' irout<='0

50、9; gout<='1' dinout<='0' rout<="00000000" ain<='0' addsub<='0' gin<='0' done<='1' case irin(5 downto 3) is when"000"=>r0in<='1'r1in<='0'r2in<='0'r3in<='0'r4in<=&

51、#39;0'r5in<='0'r6in<='0'r7in<='0'when"001"=>r1in<='1'r0in<='0'r2in<='0'r3in<='0'r4in<='0'r5in<='0'r6in<='0'r7in<='0'when"010"=>r2in<='1'r0

52、in<='0'r1in<='0'r3in<='0'r4in<='0'r5in<='0'r6in<='0'r7in<='0'when"011"=>r3in<='1'r0in<='0'r1in<='0'r2in<='0'r4in<='0'r5in<='0'r6in<='0

53、9;r7in<='0'when"100"=>r4in<='1'r0in<='0'r1in<='0'r2in<='0'r3in<='0'r5in<='0'r6in<='0'r7in<='0'when"101"=>r5in<='1'r0in<='0'r1in<='0'r2in<=&

54、#39;0'r3in<='0'r4in<='0'r6in<='0'r7in<='0'when"110"=>r6in<='1'r0in<='0'r1in<='0'r2in<='0'r3in<='0'r4in<='0'r5in<='0'r7in<='0'when"111"=>r7

55、in<='1'r0in<='0'r1in<='0'r2in<='0'r3in<='0'r4in<='0'r5in<='0'r6in<='0'when others=>null; end case; else clear<='0' irout<='0' gout<='0' dinout<='0' rout<="00

56、000000" r0in<='0' r1in<='0' r2in<='0' r3in<='0' r4in<='0' r5in<='0' r6in<='0' r7in<='0' ain<='0' addsub<='0' gin<='0' done<='0' end if; when others=>null;end ca

57、se; end if;end process;end one; 4.7 數(shù)碼管顯示led 采集寄存器R0R7的值作為led的輸入，將各寄存器值的低四位以19、AF分別顯示在8個數(shù)碼管，從而觀察各寄存器值的變化。ledout6.0 為數(shù)碼管段碼輸出端，control2.0 為第幾個數(shù)碼管有效的數(shù)碼管選擇端輸出。數(shù)碼管顯示led的VHDL代碼：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity led isport( clk:in std_logic; reg_0:in std_logic_

58、vector(15 downto 0); reg_1:in std_logic_vector(15 downto 0); reg_2:in std_logic_vector(15 downto 0); reg_3:in std_logic_vector(15 downto 0); reg_4:in std_logic_vector(15 downto 0); reg_5:in std_logic_vector(15 downto 0); reg_6:in std_logic_vector(15 downto 0); reg_7:in std_logic_vector(15 downto 0);

59、 ledout:out std_logic_vector(6 downto 0); control:out std_logic_vector(2 downto 0);end led;architecture one of led issignal controls:std_logic_vector(2 downto 0);signal led0,led1,led2,led3,led4,led5,led6,led7,outer:std_logic_vector(3 downto 0);beginled0<=reg_0(3 downto 0);led1<=reg_1(3 downto

60、0);led2<=reg_2(3 downto 0);led3<=reg_3(3 downto 0);led4<=reg_4(3 downto 0);led5<=reg_5(3 downto 0);led6<=reg_6(3 downto 0);led7<=reg_7(3 downto 0);process(clk)begin if clk'event and clk='1' then if controls="111" then controls<="000" else controls

61、<=controls+1; end if;end if;control<=controls;end process;process(controls)begincase controls is when"000"=>outer<=led0; when"001"=>outer<=led1; when"010"=>outer<=led2; when"011"=>outer<=led3; when"100"=>outer<=led

62、4; when"101"=>outer<=led5; when"110"=>outer<=led6; when"111"=>outer<=led7; when others=>outer<="XXXX"end case;case outer is when"0000" => ledout<="0111111" when"0001" => ledout<="0000110&qu

63、ot; when"0010" => ledout<="1011011" when"0011" => ledout<="1001111" when"0100" => ledout<="1100110" when"0101" => ledout<="1101101" when"0110" => ledout<="1111101" when"0111" => ledout<="0000111" when"1000" => ledout<="1111111" when"1001" => ledout<="1101111" when"1010" => l