《電子技術(shù)數(shù)字基礎(chǔ) Digital Fundamentals》雙語(yǔ)課件PPT-第07章 觸發(fā)器 Latches, Flip-Flops and Timers

1、17 Latches, Flip-Flops and Timers2Contentsw Latches (鎖存器鎖存器)w Edge-triggered Flip-Flops （邊沿觸發(fā)器）（邊沿觸發(fā)器）w Master-Slave Flip-Flops （主從觸發(fā)器）（主從觸發(fā)器）w Flip-Flop Operating Characteristics （觸發(fā)器動(dòng)作特點(diǎn)）（觸發(fā)器動(dòng)作特點(diǎn)）w Flip-Flop Function Expression （觸發(fā)器特性方程）（觸發(fā)器特性方程）37-0 Introductionw A flip-flop (觸發(fā)器）觸發(fā)器） or latch is

2、 a digital circuit that has two outputs Q and , which always in the opposite states.QIf Q is 1 and Q is 0, the flip-flop is said to be set (,on,or preset .置位，置數(shù)）（預(yù)置）If Q is 0 and Q is 1, the flip-flop is said to be reset ,off,or cleared.（復(fù)位）（清零）47-0 Introductionw Unlike the gates studied up to this

3、point, the flip-flop can in some states maintain its output state (on or off) after the input signals which produced the output state change.w It can store the information or the states.w In this chapter, bistable (雙穩(wěn)態(tài)雙穩(wěn)態(tài)), monostable (單單穩(wěn)態(tài)穩(wěn)態(tài)), and astable (暫態(tài)，非穩(wěn)態(tài)暫態(tài)，非穩(wěn)態(tài)) logic devices are covered.57

4、-1 Latches （鎖存器鎖存器）- the basic S-R (set-reset) latch （基本基本RS 觸發(fā)器）觸發(fā)器）w A latch is a type of bistable logic device.w An active-HIGH input S-R latch is formed with two cross-coupled NOR gates.w An active-LOW input S-R latch is formed with two cross-coupled NAND gates. 67-1-1 The Basic S-R Latch w Two

5、versions of S-R latchesCrossed NOR SR latch或非門(mén)構(gòu)成基本或非門(mén)構(gòu)成基本RS觸發(fā)器觸發(fā)器Crossed NAND SR latch與非門(mén)構(gòu)成基本與非門(mén)構(gòu)成基本RS觸發(fā)器觸發(fā)器77-1-1 The Basic S-R Latchw Logic diargram and its operation principle0Q 1,Q ,me(present ti at the and 0,R1,SWhen DDnn原態(tài)）初態(tài)&RDSDQQ1010 101Q , 0Q ,next time( at thethen 11nn新態(tài)）次態(tài)RESET Opera

6、tion (復(fù)位、清零）復(fù)位、清零）RESET： Active-LOW87-1-1 The Basic S-R Latchw Set operation&RDSDQQ0110101Q 0,Qstatepresent theand 1,R0,SWhen DDnn0Q , 1Qstatenext then the11nnSET Operation (置位、預(yù)置）置位、預(yù)置）SET： Active-LOW97-1-1 The Basic S-R Latchw No change condition&RDSDQQ1101101R1,SWhen DDnnnnQQ ,QQstatenext

7、 then the11Latch remains in present state.SET,RESET： nonactive107-1-1 The Basic S-R Latch&RDSDQQ1110011R1,SWhen DDnnnnQQ ,QQstatenext then the11Latch remains in present state.wNo change condition117-1-1 The Basic S-R Latch&RDSDQQ0011InvalidUncertain or invalid stateu Invalid condition127-1-1

8、 The Basic S-R LatchDDS1,R0DDS0,R1DDS0,R0&RDSDQQDDS1,R1Summary:1. Set operation2. Reset operation3. No change operation4. InvalidSET, RESET： Active-LOW137-1-1 The Basic S-R LatchTwo possibilities for the SET operation瞬間低電平瞬間低電平開(kāi)始輸出低電平開(kāi)始輸出低電平14w Two possibilities for the RESET operation7-1-1 The

9、Basic S-R Latch157-1-1 The Basic S-R LatchNo change condition. Invalid condition167-1-1 The Basic S-R Latch Truth table for an active-LOW input SR latch(特性表特性表）177-1-1 The Basic S-R Latchw Logic symbols for the SR latchesSET,RESET:Active-HIGHSET,RESET:Active-LOW187-1-1 The Basic S-R Latchw EX. Deter

10、mine the output waveform according to the input waveforms for a crossed NAND SR latch, and Q starts in the RESET (LOW) state.197-1-1 The Basic S-R LatchEX. UncertainUncertain207-1-1 The Basic S-R Latchw For a S-R latch, it has no enable input (使能端）使能端）, or clock control pin （時(shí)鐘端）（時(shí)鐘端）, so the SET an

11、d RESET inputs can change the output states directly.w In this case, the SET and RESET inputs are also called Direct-SET (SD，直接置位端，直接置位端) and Direct-RESET (RD，直，直接復(fù)位端接復(fù)位端).w A gated latch (同步同步RS觸發(fā)器觸發(fā)器) requires an clock input.217-1-2 The Gated S-R Latch (同步RS觸發(fā)器) Logic diagram and logic symbol for

12、a gated S-R latchIn Chinese books, CP is used more often than EN for a gated SR latch 227-1-2 The Gated S-R Latchw Only when EN is HIGH that the S and R inputs can control the output state.w The latch will remain the present state when EN is LOW.w The invalid state occurs when both S and R are simul

13、taneously HIGH.237-1-2 The Gated S-R LatchEx. Determine the Q output, starting in the RESET (LOW) state.The latch is initially RESET.Q=0CPSRQUncertain247-1-2 The Gated S-R LatchEx. Determine the Q output, and the latch starts in RESET (Q=0).In one CP period, Q changes its state twice.在一個(gè)時(shí)鐘周期內(nèi)，輸出跳變?cè)谝?/p>

14、個(gè)時(shí)鐘周期內(nèi)，輸出跳變2次。次。257-3 Master-Slave Flip-Flops (主從觸發(fā)器）主從觸發(fā)器）w The master-slave flip-flop is a pulse-triggered flip-flop (時(shí)鐘觸發(fā)器時(shí)鐘觸發(fā)器).w In one case, data are entered into the flip-flop at the leading edge of the clock pulses, but the output does not reflect the input state until the trailing edge.w Th

15、is kind of flip-flop doesnt allow data to change while the clock pulse is active.(一個(gè)時(shí)鐘周期內(nèi)，輸出一個(gè)時(shí)鐘周期內(nèi)，輸出只跳變只跳變1次）次）267-3 Master-Slave Flip-Flops Master-Slave S-R Flip-Flop Logic diagram Logic symbolPostponed output symbol (延遲輸出延遲輸出)Invert L主觸發(fā)器主觸發(fā)器從觸發(fā)器從觸發(fā)器The output does not reflect the S-R input data

16、 until the occurrence of the clock edge following the triggering edge.277-3 Master-Slave Flip-Flops Master-Slave S-R Flip-Flopw The master and slave flip-flops are respectively a gated S-R latch.w When CP=1, the master latch is active, and Q changes according to the inputs S and R.w When CP=0 (the f

17、alling edge), the slave latch is active, the output Q changes its states according the states of Q and its complement. The outputs are postponedThe clock is active-LOW287-3 Master-Slave Flip-Flops Master-Slave S-R Flip-FlopTruth-table for a master-slave S-R flip-flopPresent state(原態(tài)原態(tài))Next state(次態(tài)次

18、態(tài))No change保持保持SET置位，置置位，置1RESET復(fù)位，清零復(fù)位，清零Invalid or uncertain state不定狀態(tài)不定狀態(tài)297-3 Master-Slave Flip-Flops Master-Slave S-R Flip-FlopInvalid state Or uncertain stateThis is the limitation to S-R latch or flip-flops307-3 Master-Slave Flip-Flops Master-Slave J-K Flip-Flop0 01 10 01 11 11 11 10 00 01 11

19、,0,1,nnIfJKandatpresent time QQ111,0nnQQ1 10 0317-3 Master-Slave Flip-Flops Master-Slave J-K Flip-Flop1 10 01 10 00 01 10 01 11 10 01,0,nnand QQ110,1nnQQ1,IfJK1 11 1327-3 Master-Slave Flip-Flops Master-Slave J-K Flip-Flop0,1,nnWhen QQ1,0,nnWhen QQ111,0nnQQ110,1nnQQTherefore if J=1，K=1，then the outpu

20、ts change their levels to the opposite levels.(翻轉(zhuǎn)翻轉(zhuǎn))This is called toggle operation337-3 Master-Slave Flip-Flops Master-Slave J-K Flip-FlopTruth table for a master-slave J-Kflip-flopNo change保持SET置位，置1RESET復(fù)位，清零Toggle翻轉(zhuǎn)347-3 Master-Slave Flip-Flops Master-Slave J-K Flip-FlopTruth table for a master-

21、slave J-Kflip-flop357-3 Master-Slave Flip-Flops Master-Slave J-K Flip-FlopEx. Determine the Q output of the master-slave J-K flip-flop for the input waveforms. The flip-flop starts out RESET.Set ResetToggleNo changeFor a master-slave flip-flop, the output cant reflect the input on time. It is postpo

22、ned. The clock is active-LOW367-3 Master-Slave Flip-Flops Master-Slave J-K Flip-FlopCPJK377-2 Edge-Triggered Flip-Flops (邊沿觸發(fā)器邊沿觸發(fā)器)w An edge-triggered flip-flop changes its state either at the positive edge (rising edge)(上升沿上升沿) or at the negative edge (falling edge)(下降沿下降沿) of the clock pulse and

23、is sensitive to its inputs only at this transition of the clock (只在邊沿動(dòng)作只在邊沿動(dòng)作).w Each flip-flop can be either positive edge-triggered (no bubble(沒(méi)有圈沒(méi)有圈) at C/CP input) or negative edge-triggered (bubble at C/CP input).387-2 Edge-Triggered Flip-Flopsw A edge-triggered flip-flop is identified by the s

24、mall triangle (小三角形小三角形) inside the block at the C/CP input.397-2 Edge-Triggered Flip-Flops Logic circuit for a D edge-triggered flip-flopQn+1n+1=D=DTransmission Gate(傳輸門(mén)）傳輸門(mén)）When CP=0, Y=D; otherwise, Y is High-Z (高阻）高阻）407-2 Edge-Triggered Flip-Flops Truth-table Logic symbolDirect-SET SDDirect-RES

25、ET RD417-2 Edge-Triggered Flip-FlopsEx. Determine the Q output of the D edge-triggered flip-flop for the input waveforms. The flip-flop starts out RESET.Positive Edge-triggered427-2 Edge-Triggered Flip-FlopsEx. Determine the Q output of the J-K edge-triggered flip-flop 74112 for the input waveforms.

26、 437-2 Edge-Triggered Flip-FlopsNegative edge-triggered(下降沿觸發(fā)）下降沿觸發(fā)）Q starts out RESET because of Reset input starts out active.Q is RESET whenever Reset input is active.Q is SET whenever Set input is active.Q is changed only at the negative edge if both Reset and Set inputs are nonactive44Addition 1 Logic Symbol ComparisonCPCPCPCPGated FF, Triggered when CP is HIGHMaster-slave FFTriggered at the