實驗408021301張阿偉

1、 基于Quartus II的硬件描述語言電路設計一、實驗要求 基本要求 1： 由四個數(shù)碼管顯示的計時電路， 低兩位按照 20 進制設計，高兩位按照 11進制設計。附加要求 1： 該計時電路具有校準功能,可以按 1Hz 頻率校準高兩位的顯示,可以按 10Hz頻率校準低兩位的顯示；附加要求 2： 高兩位的進制可以任意設置。（不需要從新編譯電路）附加要求 3：在計數(shù)到達某整點值時例如 0300 的時刻 （該值可以根據(jù)老師的要求設置）,4盞 LED 燈一起按照 10Hz 閃爍 5 秒鐘。2、 實驗代碼與器件顯示1. 選擇器的VHDL源文件module xuanze(clk0,clk1,choose,c

2、lk);input clk0;input clk1;input choose;output clk;reg clk;always if ( choose = 1'b1 ) beginclk <= clk0;end else if ( choose = 1'b0 ) beginclk <= clk1;endEndmodule生成的器件：選擇器功能描述：選擇1kHz和10kHz其中一個作為輸出信號2. 分頻器的VHDL源文件library ieee;use ieee.std_logic_1164.all;use IEEE.STD_LOGIC_ARITH.ALL;use

3、IEEE.STD_LOGIC_UNSIGNED.ALL;entity fenpin isport(clk:in std_logic;-input clk 50MHzclk_1Hz :out std_logic;clk_10Hz :out std_logic);-輸出clkend fenpin;architecture fwm of fenpin isconstant m:integer:=2500000;signal tmp1:std_logic;signal tmp2:std_logic;beginprocess(clk)variable cout1:integer:=0;variable

4、cout2:integer:=0;beginif clk'event and clk='1' thencout1:=cout1+1;cout2:=cout2+1;if cout1<=m*10 then tmp1<='0'elsif cout1<m*20 then tmp1<='1'else cout1:=0;end if;if cout2<=m then tmp2<='0'elsif cout2<m*2 then tmp2<='1'else cout2:=0;

5、end if;end if;end process;clk_1Hz<=tmp1;clk_10Hz<=tmp2;end fwm;生成的器件：分頻器功能描述：輸入50MHz的時鐘信號，經(jīng)分頻器后輸出頻率為1Hz和10Hz的兩個信號。3. 計數(shù)器的VHDL源文件（2個）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;entity djishu isport(clk : in std_logic;d1 : out std_logic_vector(3 downto 0);d2 : out st

6、d_logic_vector(3 downto 0);c : out std_logic);END djishu;architecture fwm of djishu issignal dat1:std_logic_vector(3 downto 0);signal dat2:std_logic_vector(3 downto 0);BEGINprocess(clk)begin if clk'event and clk = '1' thenif dat1 = "1001" thendat1 <="0000"if dat2 =

7、 "0001" thendat2 <="0000"c<='1'elsedat2<=dat2+1;c<='0'end if;else dat1<=dat1+1; c<='0'end if;end if;end process;d1 <= dat1;d2 <= dat2;end fwm;生成的器件：低位計數(shù)器功能：將輸出轉換為兩位十進制數(shù)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_arit

8、h.all;USE IEEE.STD_LOGIC_UNSIGNED.ALL;entity gjishu isport(clk : in std_logic;jinzhi : in std_logic_vector(4 downto 0);g1 : out std_logic_vector(3 downto 0);g2 : out std_logic_vector(3 downto 0);END gjishu;architecture fwm of gjishu issignal dat1:std_logic_vector(4 downto 0);signal dat2:std_logic_ve

9、ctor(4 downto 0);signal data1:std_logic_vector(3 downto 0);signal data2:std_logic_vector(3 downto 0);BEGINprocess(jinzhi,clk)variable q1:integer range 0 to 255;variable q2:integer range 0 to 255;variable a:integer range 0 to 255;begin if clk'event and clk = '1' thena := conv_integer(jinz

10、hi);if a = 0 thenif dat1 = "01010" thendat1 <="00000"elsedat1<=dat1+1;end if;q1:=(conv_integer(dat1);q2:=(q1/10);data1 <=conv_std_logic_vector(q1 rem 10,4);data2 <=conv_std_logic_vector(q2 rem 10,4);elseif dat1 = (jinzhi-"00001") thendat1 <="00000&qu

11、ot;elsedat1<=dat1+1;end if;q1:=(conv_integer(dat1);q2:=(q1/10);data1 <=conv_std_logic_vector(q1 rem 10,4);data2 <=conv_std_logic_vector(q2 rem 10,4);end if;end if;end process;g1 <= data1;g2 <= data2;end fwm;生成的器件：高位計數(shù)器功能：將輸出轉換為兩位十進制數(shù)【十位+個位】4. 譯碼器的VHDL源文件LIBRARY IEEE;USE IEEE.STD_LOGIC

12、_1164.ALL;ENTITY yimaqi ISPORT(data_in:IN STD_LOGIC_VECTOR(3 DOWNTO 0);dis_out:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END yimaqi;ARCHITECTURE fwm OF yimaqi ISBEGINPROCESS(data_in)BEGINCASE data_in ISWHEN"0000"=>dis_out<="1000000"WHEN"0001"=>dis_out<="1111001&

13、quot;WHEN"0010"=>dis_out<="0100100"WHEN"0011"=>dis_out<="0110000"WHEN"0100"=>dis_out<="0011001"WHEN"0101"=>dis_out<="0010010"WHEN"0110"=>dis_out<="0000010"WHEN"0111&

14、quot;=>dis_out<="1111000"WHEN"1000"=>dis_out<="0000000"WHEN"1001"=>dis_out<="0010000"WHEN OTHERS=>dis_out<="1111111"END CASE;END PROCESS;END fwm;生成的器件：七段譯碼器5. 控制LED閃爍的VHDL源文件module LED( clk,d1,d2,g1,g2,out );input cl

15、k;input 3:0 d1;input 3:0 d2;input 3:0 g1;input 3:0 g2;output 3:0 out;reg 3:0 out = 4'b0000;parameter T5s = 6'd50;reg 5:0 count; reg flag;always ( posedge clk )beginif ( g2 = 4'd0 && g1 =4'd0 && d2 = 4'd0 && d1 = 4'd0 )flag <= 1'b1;if ( flag = 1'b1 )begincount <= count + 1'b1;out <= out;if( count = T5s )beginflag <= 1'b0;out <= 4'b0000;count <= 6'