因?yàn)樽x與寫寄存器都發(fā)生在Cycleppt課件

1、1Pipelined Implementation2Outline Instruction Stalling Data Forwarding Handle Control Hazard Suggested Reading 4.5 3Data Dependencies: 2 Nops123456789FDE M WFDE M WFDE M WFDE M WFDE M WFDE M WFDE M WFDE M WFDE M WFDE M WFDE M WFDE M W10WR%eax f3DvalA fR%edx = 10valB fR%eax = 0WR%eax f3WR%eax f3DvalA

2、 fR%edx = 10valB fR%eax = 0DvalA fR%edx = 10valB fR%eax = 0Cycle 6Error# demo-h2.ys0 x000:irmovl $10,%edx0 x006:irmovl $3,%eax0 x00c:nop0 x00d:nop0 x00e:addl %edx,%eax0 x010:halt4Data Dependencies: 2 Nops# demo-h2.ys0 x000:irmovl $10,%edx0 x006:irmovl $3,%eax0 x00c:nop0 x00d:nop bubble0 x00e:addl %e

3、dx,%eax0 x010:halt123456789FDE M WFDE M WFDE M WFE M WD DE M WFDE M W10FFDE M W11 If instruction follows too closely after one that writes register, slow it down Hold instruction in decode Dynamically inject nop into execute stagedstMdstE5EMWFDPCPCALUData MemorySelect PCrBSelect AALUAALUBMem.control

4、AddrreadALU funFetchDecodeExecuteMemoryWrite backdata outdata inM_valAW_valMW_valEM_valAW_valMd_rvalAf_PCPredict PCvalEvalMdstEdstMBchvalEvalAdstEdstMicode ifunvalCvalAvalBdstEsrcBvalCvalPicode ifun rApredPCCCe_BchM_BchwritedstMsrcARegister FileAB MEsrcAsrcBd_srcA d_srcBInstructionInstruction Memory

5、incrementicodeicode6Stall Condition Source Registers srcA and srcB of current instruction in decode stage Destination Registers dstE and dstM fields Instructions in execute, memory, and write-back stages Condition srcA=dstE or srcA=dstM srcB=dstE or srcB=dstM Special Case Dont stall for register ID

6、8 Indicates absence of register operand7Data Dependencies: 2 Nops# demo-h2.ys0 x000:irmovl $10,%edx0 x006:irmovl $3,%eax0 x00c:nop0 x00d:nop bubble0 x00e:addl %edx,%eax0 x010:halt123456789FDE M WFDE M WFDE M WFE M WD DE M WFDE M W10FFDE M W11Cycle 6WDW_dstE = %eaxW_valE = 3srcA = %edxsrcB = %eax8Sta

7、lling X3123456789FDE M WFDE M WFE M WDE M WDDE M WFDE M W10FFDFE M W11Cycle 4WW_dstE = %eaxDsrcA = %edxsrcB = %eaxMM_dstE = %eaxDsrcA = %edxsrcB = %eaxEE_dstE = %eaxDsrcA = %edxsrcB = %eaxCycle 5Cycle 6# demo-h0.ys0 x000:irmovl $10,%edx0 x006:irmovl $3,%eax bubble bubble bubble0 x00c:addl %edx,%eax0

8、 x0e:halt9What Happens When Stalling? Stalling instruction held back in decode stage Following instruction stays in fetch stage Bubbles injected into execute stage Like dynamically generated nops Move through later stages0 x000: irmovl $10,%edx0 x006: irmovl $3,%eax0 x00c: addl %edx,%eaxCycle 40 x00

9、e: halt0 x000: irmovl $10,%edx0 x006: irmovl $3,%eax0 x00c: addl %edx,%eax# demo-h0.ys0 x00e: halt0 x000: irmovl $10,%edx0 x006: irmovl $3,%eax bubble0 x00c: addl %edx,%eaxCycle 50 x00e: halt0 x006: irmovl $3,%eax bubble0 x00c: addl %edx,%eax bubbleCycle 60 x00e: halt bubble bubble0 x00c: addl %edx,

10、%eax bubbleCycle 70 x00e: halt bubble bubbleCycle 80 x00c: addl %edx,%eax0 x00e: haltWrite BackMemoryExecuteDecodeFetch10Implementing StallingEMWFDrBsrcAsrcBicodevalEvalMdstE dstMBchicodevalEvalAdstE dstMicode ifunvalCvalAvalBdstE dstM srcA srcBvalCvalPicode ifunrApredPCd_ srcBd_ srcAD_ icodeE_ dstE

11、E_ dstMPipecontrollogicD_stallE_bubbleM_ dstEM_ dstMW_ dstEW_ dstMF_stall11Implementing Stalling Pipeline Control Combinational logic detects stall condition Sets mode signals for how pipeline registers should update12Initial Version of Pipeline Controlbool F_stall = d_srcA = E_dstE | d_srcA = M_dst

12、M | d_srcA = M_dstE | d_srcA = W_dstM |d_srcA = W_dstE ;bool D_stall = d_srcA = E_dstE | d_srcA = M_dstM | d_srcA = M_dstE | d_srcA = W_dstM |d_srcA = W_dstE ;bool E_bubble =d_srcA = E_dstE | d_srcA = M_dstM | d_srcA = M_dstE | d_srcA = W_dstM |d_srcA = W_dstE ;13Pipeline Register ModesRisingclockRi

13、singclock_Output = xx xOutput = xInput = ystall = 1bubble= 0 x xStall14Pipeline Register ModesnopRisingclockRisingclock_Output = nopx xOutput = xInput = ystall = 0bubble= 1Bubble15Pipeline Register ModesRisingclockRisingclock_Output = yy yOutput = xInput = ystall = 0bubble= 0 x xNormal16Data Forward

14、ing Observation Value generated in execute or memory stage Trick Pass value directly from generating instruction to decode stage Needs to be available at end of decode stage17Data Forwarding Example1 2 3 4 5 6 7 8 9F D E M WF D E M WF D E M WF D E M WF D E M WF D E M WF D E M WF D E M WF D E M WF D

15、E M WF D E M WF D E M W10Cycle 6WR%eax f3DvalAfR%edx = 10valBfW_ valE= 3W_ dstE= %eaxW_valE = 3srcA= %edxsrcB= %eax# demo-h2.ys0 x000:irmovl $10,%edx0 x006:irmovl $3,%eax0 x00c:nop0 x00d:nop0 x00e:addl %edx,%eax0 x010:haltirmovl in write-back stageDestination value in W pipeline registerForward as v

16、alB for decode stage18CCALUData memoryWrite backd_srcBd_srcARegister fileA BMEvalA,valBaluA, aluBBche_valEAddr, Datam_valMW_valE,W_valM,W_dstE, W_dstMEMWDForwardW_valE,W_valM19Bypass Paths Decode Stage Forwarding logic selects valA and valB Normally from register file Forwarding: get valA or valB fr

17、om later pipeline stage Forwarding Sources Execute: valE Memory: valE, valM Write back: valE, valM20Data Forwarding Example #2# demo-h0.ys0 x000:irmovl $10,%edx0 x006:irmovl $3,%eax0 x00c:addl %edx,%eax0 x0e:haltRegister %edxGenerated by ALU during previous cycleForward from memory stage as valARegi

18、ster %eaxValue just generated by ALUForward from execute stage as valB12345678FD E MWFD E MWFD E M WFD E M WCycle 4MDvalAfM_valE= 10valBfe_valE= 3M_dstE= %edxM_valE = 10srcA= %edxsrcB= %eaxEE_dstE= %eaxe_valE f0 + 3 = 321Implementing Forwarding Add additional feedback paths from E, M, and W pipeline

19、 registers into decode stage Create logic blocks to select from multiple sources for valA and valB in decode stage22RegisterfileRegisterfileALUALUDatamemoryDatamemorydstE dstMALUBAddrsrcA srcBALUfun.data outdata inAB MEM_ valEW_valEW_valMW_ valEvalEvalAdstE dstMvalAvalBdstE dstM srcA srcBd_ srcBd_ s

20、rcASel+FwdAFwdBvalEvalMdstE dstMm_ valMW_valMe_ valE23Implementing Forwarding# What should be the A value?int new_E_valA = # Use incremented PCD_icode in ICALL, IJXX : D_valP; # Forward valE from execute d_srcA = E_dstE : e_valE; # Forward valM from memoryd_srcA = M_dstM : m_valM; # Forward valE fro

21、m memory d_srcA = M_dstE : M_valE; # Forward valM from write back d_srcA = W_dstM : W_valM; # Forward valE from write backd_srcA = W_dstE : W_valE; # Use value read from register file 1 : d_rvalA;24Limitation of Forwarding#demo-luh.ys0 x000: irmovl $128, %edx0 x006: irmovl $3, %ecx0 x00c: rmmovl %ec

22、x, 0(%edx)0 x012: irmovl $10, %ebx0 x018: mrmovl 0(%edx), %eax # Load %eax0 x10e: addl %ebx, %eax #Use %eax0 x020: haltLoad-use dependencyValue needed by end of decode stage in cycle 7Value read from memory in memory stage of cycle 8ErrorMM_dstM= %eaxm_valMfM128 = 3Cycle 7Cycle 8DvalAfM_valE= 10valB

23、fR%eax = 0DvalAfM_valE= 10valBfR%eax = 0MM_dstE= %ebxM_valE= 10123456789FDEMWFDEMWFDEM WFDEM WFDEM WFDEM WFDEM W10FDEM W1125#demo-luh.ys0 x000: irmovl $128, %edx0 x006: irmovl $3, %ecx0 x00c: rmmovl %ecx, 0(%edx)0 x012: irmovl $10, %ebx0 x018: mrmovl 0(%edx), %eax # Load %eax bubble0 x10e: addl %ebx

24、, %eax #Use %eax0 x020: haltStall using instruction for one cycleCan then pick up loaded value by forwarding from memory stageMM_dstM = %eaxm_valM f M128 = 3MM_dstM = %eaxm_valM f M128 = 3Cycle 8DvalA f W_valE = 10valB f m_valM = 3DvalA f W_valE = 10valB f m_valM = 3WW_dstE = %ebxW_valE = 10WW_dstE = %ebxW_valE = 10123456789FDEMWFDEMWFDEMWFDEMWFDEM WFDEM WFDEM WFDEM WFDEM WFDEM WFDEM WEM W10DDEM W11FDEM WFF12Avoiding Load/Use Hazard26DRegisterfileRegisterfileCCCCALUALUrBdstE dstMALUAALUBsrcA srcBALUfun.DecodeExecuteAB MEW_valMW_ valEEicode ifunvalCvalAvalBdstE dstM srcA srcBvalCval