et1011c數(shù)據(jù)手冊(英文)

1、data sheetseptember 2007truephy ? et1011cgigabit ethernet transceiverfeaturesn10base-t, 100base-tx, and 1000base-t gigabit ethernet transceiver: 0.13 m process 128-pin tqfp and 84-pin mlcc:orgmii, gmii, mii, rtbi, and tbi interfaces to mac or switch 68-pin mlcc:orgmii and rtbi interfaces to mac or s

2、witchnlow power consumption: typical power less than 750 mw in 1000base-t mode advanced power management acpi compliant wake-on-lan supportnoversampling architecture to improve signal integrity and snrnoptimized, extended performance echo and next fil-tersnall-digital baseline wander correctionndigi

3、tal pga controlnon-chip diagnostic supportnautomatic speed negotiationnautomatic speed downshiftnsingle supply 3.3 v or 2.5 v operation: on-chip regulator controllers 3.3 v or 2.5 v digital i/o 3.3 v tolerant i/o pins (mdc, mdio, coma, reset_n, and jtag pins) 1.0 v or 1.1 v core power supplies 1.8 v

4、 or 2.5 v for transformer center tapnjtagnet1011c is a pin-compatible replacement for the et1011 devicencommercial- and industrial-temperature versions avail-ableintroductionthe lsi et1011c is a gigabit ethernet transceiver fabri-cated on a single cmos chip. packaged in either an 128-pin tqfp, an 84

5、-pin mlcc, or a 68-pin mlcc, the et1011c is built on 0.13 m technol-ogy for low power consumption and application in server and desktop nic cards. it features single power supply operation using on-chip regulator controllers. the 10/100/1000base-t device is fully compliant with ieee? 802.3, 802.3u,

6、and 802.3ab standards.the et1011c uses an oversampling architecture to gather more signal energy from the communication channel than possible with traditional architectures. the additional sig-nal energy or analog complexity transfers into the digital domain. the result is an analog front end that d

7、elivers robust operation, reduced cost, and lower power consump-tion than traditional architectures.using oversampling has allowed for the implementation of a fractionally spaced equalizer, which provides better equalization and has greater immunity to timing jitter, resulting in better signal-to-no

8、ise ratio (snr) and thus improved ber. in addition, advanced timing algorithms are used to enable operation over a wider range of cabling plants. table of contentscontentspagecontentspage2lsi corporationdata sheetseptember 2007gigabit ethernet transceivertruephy et1011cfeatures.1introduction.1functi

9、onal description.5oversampling architecture.5automatic speed downshift.5transmit functions.6receive functions.6autonegotiation. 7carrier sense (128-pin tqfp and 84-pin mlcc only).7link monitor.8leds.8regulator control. 8resetting the et1011c.8loopback mode.9digital loopback.9analog loopback.10low-po

10、wer modes.11pin information.12pin diagram, 128-pin tqfp .12pin diagram, 84-pin mlcc.13pin diagram, 68-pin mlcc .14pin descriptions, 128-pin tqfp, 84-pin mlcc, and 68-pin mlcc.15mac interface.22management interface.27configuration interface.29leds interface.31media-dependent interface: transformer in

11、terface.32clocking and reset.33jtag.34regulator control. 34power, ground, and no connect.35cable diagnostics.36register description.37register address map.37register functions/settings.38electrical specifications.62absolute maximum ratings.62recommended operating conditions.62device electrical chara

12、cteristics.63timing specification.67gmii 1000base-t transmit timing (128-pin tqfp and 84-pin mlcc only).67gmii 1000base-t receive timing (128-pin tqfp and 84-pin mlcc only).68rgmii 1000base-t transmit timing.69rgmii 1000base-t receive timing. 71mii 100base-tx transmit timing.73mii 100base-tx receive

13、 timing .74mii 10base-t transmit timing. 75mii 10base-t receive timing.76serial management interface timing.77reset timing.78clock timing.79jtag timing.80package diagram, 128-pin tqfp .81package diagram, 84-pin mlcc .82package diagram, 68-pin mlcc .83ordering information .84table pagetable 1. et1011

14、c device signalsby interface, 128-pin tqfp, 84-pin and 68-pin mlcc.15table 2. multiplexed signals on the et1011c.20table 3. gmii signal description (1000base-t mode) (128-pin tqfp and84-pin mlcc only).22table 4. rgmii signal description (1000base-t mode).23table 5. mii interface (100base-tx and 10ba

15、se-t) (128-pin tqfp and 84-pin mlcc only).24table 6. ten-bit interface (1000base-t) (128-pin tqfp and 84-pin mlcc only).25table 7. rtbi signal description(1000base-t mode) .26table 8. management frame structure.27table 9. management interface.28table 10. configuration signals.29table 11. led .31tabl

16、e 12. transformer interface signals.32table 13. clocking and reset . 33table 14. jtag test interface.34table 15. regulator control interface.34table 16. supply v oltage combinations.35table 17. power, ground, and no connect.35table 18. cable diagnostic functions.36table 19. register address map.37ta

17、ble 20. register type definition.37table 21. control register address 0.38table 22. status register address 1.39table 23. phy identifier register 1 address 2.40table 24. phy identifier register 2 address 3.40table 25. autonegotiation advertisement registeraddress 4.41table 26. autonegotiation link p

18、artner ability register address 5. 42table 27. autonegotiation expansion register address 6.43table of contents(continued)tablepagetablepagelsi corporation3data sheetseptember 2007gigabit ethernet transceivertruephy et1011ctable 28. autonegotiation next page transmit register address 7.43table 29. l

19、ink partner next page register address 8.44table 30. 1000 base-t control registeraddress 9.45table 31. 1000base-t status registeraddress 10.46table 32. reserved registers addresses 11 14.47table 33. extended status register address 15.47table 34. reserved registers addresses 16 17.47table 35. phy co

20、ntrol register 2 address 18.48table 36. mdi/mdi-x configuration.49table 37. mdi/mdi-x pin mapping.49table 38. loopback control register address 19.50table 39. loopback bit (0.14) and cable diagnostic mode bit (23.13) settings for loopback mode.50table 40. rx error counter register address 20.51table

21、 41. management interface (mi) control register address 21.51table 42. phy configuration register address 22.52table 43. phy control register address 23.53table 44. interrupt mask register address 24.54table 45. interrupt status register address 25.55table 46. phy status register address 26.56table

22、47. led control register 1 address 27.57table 48. led control register 2 address 28.58table 49. led control register 3 address 29.58table 50. diagnostics control register(tdr mode) address 30.59table 51. diagnostics status register (tdr mode) address 31.60table 52. diagnostics control register (link

23、 analysis mode) address 30.61table 53. mdi/mdi-x configuration for 1000base-t with c and d swapped/not swapped.61table 54. absolute maximum ratings.62table 55. et1011c recommended operating conditions.62table 56. device characteristics 3.3 v digital i/o supply (dvddio).63table 57. device characteris

24、tics 2.5 v digital i/o supply (dvddio).63table 58. et1011c current consumption 1000base-t.64table 59. et1011c current consumption 100base-tx.64table 60. et1011c current consumption 10base-t.64table 61. et1011c current consumption 10base-t idle.65table 62. et1011c current consumption hardware powerdo

25、wn.65table 63. et1011c current consumption low power energy detect (lped). 65table 64. et1011c current consumption standby powerdown . 66table 65. et1011c current consumption software powerdown.66table 66. gmii 1000base-t transmit timing.67table 67. gmii 1000base-t receive timing.68table 68. rgmii 1

26、000base-t transmit timing.69table 69. rgmii 1000base-t transmit timing.70table 70. rgmii 1000base-t receive timing.71table 71. rgmii 1000base-t receive timing.72table 72. mii 100base-tx transmit timing.73table 73. mii 100base-tx receive timing.74table 74. mii 10base-t transmit timing.75table 75. mii

27、 10base-t receive timing.76table 76. serial management interface timing.77table 77. reset timing . 78table 78. clock timing.79table 79. jtag timing.80table 80. ordering information. 84table of contentscontentspagecontentspage4lsi corporationdata sheetseptember 2007gigabit ethernet transceivertruephy

28、 et1011cfigure 1. et1011c block diagram.5figure 2. loopback functionality.9figure 3. digital loopback.9figure 4. replica and line driver analog loopback.10figure 5. external cable loopback.10figure 6. pin diagram for et1011c in 128-pin tqfp package (top view).12figure 7. pin diagram for et1011c in 8

29、4-pin mlcc package (top view).13figure 8. pin diagram for et1011c in 68-pin mlcc package (top view).14figure 9. et1011c gigabit ethernet card block diagram.21figure 10. gmii mac-phy signals.22figure 11. rgmii mac-phy signals.23figure 12. mii signals.24figure 13. ten-bit interface.25figure 14. reduce

30、d ten-bit interface.26figure 15. gmii 1000base-t transmit timing.67figure 16. gmii 1000base-t receive timing. 68figure 17. rgmii 1000base-t transmit timingtrace delay.69figure 18. rgmii 1000base-t transmit timinginternal delay.70figure 19. rgmii 1000base-t receive timingtrace delay.71figure 20. rgmi

31、i 1000base-t receive timinginternal delay.72figure 21. mii 100base-tx transmit timing.73figure 22. mii 100base-tx receive timing.74figure 23. mii 10base-t transmit timing.75figure 24. mii 10base-t receive timing.76figure 25. serial management interface timing.77figure 26. reset timing.78figure 27. c

32、lock timing.79figure 28. jtag timing.80figurefigure(continued)data sheetseptember 2007lsi corporation5gigabit ethernet transceivertruephy et1011cfunctional descriptionthe lsi et1011c is a gigabit ethernet transceiver that simultaneously transmits and receives on each of the four utp pairs of categor

33、y 5 cable (signal dimensions or channels a, b, c, and d) at 125 msymbols/s using five-level pulse-amplitude modulation (pam). figure 1 is a block diagram of its basic configuration.figure 1. et1011c block diagrampma apcsnextcancellersechocancellertransmitshapingffergmiigmiimiirtbitbigaincontroltimin

34、gcontrolblwcorrectiondacadcpgahybridtrellisdecoderclockgeneratorpma bpma cpma dtrd0-3 txd7:0rx_errx_dvtx_entx_ergtx_clkrxd7:0rx_clkclockmanagementinterfacemi registersjtag/testauto-negotiationleds/config10base-tmdcmdint_nmdioxtal_1reset_nxtal_2sys_clkledscolcrstcktrst_ntmstdotdiconfigphyad4:0biasrse

35、tresettx_clkoversampling architecturethe et1011c architecture uses oversampling techniques to sample at two times the symbol rate. a fractionally spaced feed forward equalizer (ffe) adapts to remove intersymbol interference (isi) and to shape the spectrum of the received signal to maximize the (snr)

36、 at the trellis decoder input. the ffe equalizes the channel to a fixed target response. oversampling enables the use of a fractionally spaced equal-izer (fse) structure for the ffe, resulting in symbol rate clocking for both the ffe and the rest of the receiver. this provides robust operation and s

37、ubstantial power savings.automatic speed downshiftautomatic speed downshift is an enhanced feature of autone-gotiation that allows the et1011c to:nfallback in speed, based on cabling conditions or link partner abilities.noperate over cat-3 cabling (in 10base-t mode).noperate over two-pair cat-5 cabl

38、ing (in 100base-tx mode).for speed fallback, the et1011c first tries to autonegotiate by advertising 1000base-t capability. after a number of failed attempts to bring up the link, the et1011c falls back to advertising 100base-tx and restarts the autonegotiation process. this process continues throug

39、h all speeds down to 10base-t. at this point, there are no lower speeds to try and so the host enables all technologies and starts again.phy configuration register, address 22, bits 11 and 10 enable automatic speed downshift and specifies if fallback to 10base-t is allowed. phy control register, add

40、ress 23, bits 11 and 12 specify the number of failed attempts before downshift (programmable to 1, 2, 3, or 4 attempts). data sheetseptember 2007gigabit ethernet transceivertruephy et1011c6lsi corporationfunctional description (continued)transmit functions 1000base-t encoderin 1000base-t mode, the e

41、t1011c translates 8-bit data from the mac interfaces into a code group of four quinary symbols that are then transmitted by the pma as 4d five-level pam signals over the four pairs of cat-5 cable.100base-tx encoderin 100base-tx mode, 4-bit data from the media independent interface (mii) is 4b/5b enc

42、oded to output 5-bit serial data at 125 mhz. the bit stream is sent to a scrambler, and then encoded to a three-level mlt3 sequence that is then transmitted by the pma.10base-t encoderin 10base-t mode, the et1011c transmits and receives manchester-encoded data. receive functionsdecoder 1000base-tin

43、1000base-t mode, the pma recovers the 4d pam signals after compensating for the cabling conditions. the resulting code group is decoded to 8-bit data. data stream delimiters are translated appropriately, and the data is output to the receive data pins of the mac interfaces. the gmii receive error si

44、gnal is asserted when invalid code groups are detected in the data stream.decoder 100base-txin 100base-tx mode, the pma recovers the three-level mlt3 sequence that is descrambled and 5b/4b decoded to 4-bit data. this is output to the mii receive data pins after data stream delimiters have been trans

45、lated appropriately. the mii receive error signal is asserted when invalid code groups are detected in the data stream.decoder 10base-tin 10base-t mode, the et1011c decodes the manchester-encoded received signal.hybridthe hybrid subtracts the transmitted signal from the input signal allowing full-du

46、plex operation on each of the twisted-pair cables.programmable gain amplifier (pga)the pga operates on the received signal in the analog domain prior to the analog-to-digital converter (adc). the gain control module monitors the signal at the output of the adc in the digital domain to control the pg

47、a. it implements a gain that maximizes the signal at the adc while ensuring that no hard clipping occurs.clock generatora clock generator circuit uses the 25 mhz input clock signal and a phase-locked loop (pll) circuit to generate all the required internal analog and digital clocks. a 125 mhz sys-te

48、m clock is also generated and is available as an output clock.analog-to-digital converterthe adc operates at 250 mhz oversampling at twice the symbol rate in 1000base-t and 100base-tx. this enables innovative timing recovery and fractional skew correction and has allowed transfer of analog complexit

49、y to the digital domain.timing recovery/generationthe timing recovery and generator block creates transmit and receive clocks for all modes of operation. in transmit mode, the 10base-t and 100base-tx modes use the 25 mhz clock input. while in receive mode, the input clock is locked to the receive da

50、ta stream. 1000base-t is imple-mented using a master-slave timing scheme, where the mas-ter transmit and receive are locked to the 25 mhz clock input, and the slave acquires timing information from the receive data stream. timing recovery is accomplished by first acquiring lock on one channel and th

51、en making use of the constant phase relationship between channels to lock on the other pairs, resulting in a simplified pll architecture. timing shifts due to changing environmental conditions are tracked by the et1011c.data sheetseptember 2007gigabit ethernet transceivertruephy et1011clsi corporati

52、on7functional description (continued)adaptive fractionally spaced equalizerthe et1011c s unique oversampling architecture employs an fse in place of the traditional ffe structure. this results in robust equalization of the communications channel, which translates to superior bit error rate (ber) per

53、formance over the widest variety of worst-case cabling scenarios. the all-digital equalizer automatically adapts to changing condi-tions.echo and crosstalk cancellerssince the four twisted pairs are bundled together and not insulated from each other in gigabit ethernet, each of the transmitted signa

54、ls is coupled onto the three other cables and is seen at the receiver as near-end crosstalk (next). a hybrid circuit is used to transmit and receive simultaneously on each pair. if the transmitter is not perfectly matched to the line, a signal component will be reflected back as an echo. reflections

55、 can also occur at other connectors or cable imperfections. the et1011c cancels echo and next by subtracting an estimate of these signals from the equalizer output. baseline wander correctiona known issue for 1000base-t and 100base-tx is that the transformer attenuates at low frequencies. as a resul

56、t, when a large number of symbols of the same sign are transmitted consecutively, the signal at the receiver gradually dies away. this effect is called baseline wander. by employing a circuit that continuously monitors and compensates for this effect, the probability of encountering a receive symbol

57、 error is reduced.autonegotiationautonegotiation is implemented in accordance with ieee802.3. the device supports 10base-t, 100base-tx, and 1000base-t and can autonegotiate between them in either half- or full-duplex mode. it can also parallel detect 10base-t or 100base-tx. if autonegotiation is dis

58、abled, a 10base-t or 100base-tx link can be manually selected via the ieeemii registers.pair skew correctionin gigabit ethernet, pair skew (timing differences between pairs of cable) can result from differences in length or manu-facturing variations between the four individual twisted-pair cables. t

59、he et1011c automatically corrects for both integer and fractional symbol timing differences between pairs.automatic mdi crossoverduring autonegotiation, the et1011c automatically detects and sets the required mdi configuration so that the remote transmitter is connected to the local receiver and vic

60、e versa. this eliminates the need for crossover cables or crosswired (mdix) ports. if the remote device also implements auto-matic mdi crossover, and/or the crossover is implemented in the cable, the crossover algorithm ensures that only one ele-ment implements the required crossover.polarity invers