常見AWARD主板診斷卡詳細(xì)代碼

1、常見award主板診斷卡詳細(xì)代碼code: ff, 00, co, do, cf, fl, or nothing mean the cpu failedcl,c6,c3,d3,d4,d6, d8, b0, a7, el represent memory24,25,26,01,0a,0b, 2a, 2b, 3123,24,25,said some integrated graphics motherboard cannormal light, some via chipset showed 13 said can light lip, some in the name-brand compute

2、r motherboard shows obis normal, some motherboard shows 4 e said normal light, some intel motherboard chipset showed 26 or 16 can normal lightthe combination cycle of cl, c6, c3, 01, and 02 is mostly i / 0 bad or swiping the biosif shown in 05, ed, 41, direct the bios 00. you will control the ini19

3、boot load.1 processor test 1, processor status verification, and if the test fails, the loop is infinite the processor register test is about to begin, and unblocking interrupts will be suspended the cpu register test is ongoing or failing.determine the type of diagnosis (normal or manufacturing) if

4、 the keyboard buffer contains data, it will fai1. disable non-blocking interrupts: start with a delay. cmos write/read is in or outremove 8042 keyboard controller and issue the testkbrd command (aah). rom bios check parts are ongoing or malfunction.make 8042 keyboard controller reset and verify test

5、kbrd keyboard controller soft reset/electrical test programmable interval timer tests are being performed or failedif you repeat manufacturing test 1 through 5, you can obtain 8042 control status confirm the soft reset/power; the boot rom. the dma is in or out of ordermake the circuit film initial p

6、reparation, disable video, odd-even, dma circuit, and clear dma circuit, all page register and cmos stop bytes the rom bios check sum has been activated and the keyboard buffer is checked for removal the dma initial page register reads/writes tests are being performed or failed7 processor test 2, ve

7、rify the cpu register's work rom bios check sum is normal, keyboard buffer has been cleared, and bat (basic guarantee test) commands are issued to the keyboardmake the cmos timer as the initial preparation, normal update timer cycle the bat command has been issued to the keyboard and will be wri

8、tten to the bat command the ram update test is ongoing or failingthe 2009 eprom check sum must be equal to zero. verify the basic guarantee test for the keyboard, then verify the keyboard command byte the first 64k ram test is ongoing0a prepares the video interface for initial preparation. issue the

9、 keyboard command byte code that will be written to the command byte data the first 64k ram chip or data line failsa_nd shifts.ob test 8254 channel 0. write to the keyboard controller command byte and will issue the blocking/unlock command of the pins 23 and 24. the first 64k ram chi/even logic fail

10、ed 0c test 8254 channel 1. the keyboard controller pins 23, 24 has been blocked/unlocked. the nop command has been issued the first 64k ran address line failure.0d 1, check that the cpu speed matches the system check that the control chip has been programmed to match the initial setting. the video c

11、hannel test, if failed, honking processing the nop command; then the cmos stop the register the first 64k ram has a parity failure0e to test cmos outage bytes cmos stop open register to read/write tests; the cmos check sum is calculated initialize the input/output port addressof test expanded cmos c

12、omputed cmos review total writing diagnostic bytes; cmos began to preparetest dma channel 0. cmos is initially ready for the date and time for the cmos status register. the first 64k ram zero faulttest dma channel 1.the cmos status register is ready to deactivate dma and interrupt controllers the fi

13、rst 64dk ram 1 failed.test the dma page register disable dma controller 1 and interrupt controller 1 and 2; the video display will be set and port b is ready for initial preparation. the first 64dk ram 2 failedtest 8741 keyboard con troll er interface the video display has been deactivated and port

14、b has been pre-prepared; the circuit wafer initialization/memory detection is about to begin. the first 64dk ram was the third failuretest memory update trigger circuit the circuit chip initializer/memory is automatically checked out; the 8254timer test is aboutto start. the first 64dk ram was the f

15、ourthfailure.test the beginning of 64k system memory. the second channel timer is tested in half: the 8254 channel 2 timer is about to complete the test the first 64dk ram was the fifth faultestablish the interrupt vector table used for 8259 the second channel timer test is over; the 8254 first chan

16、nel timer is about to complete the test the first 64dk ram no. 6 failedset the video input/output job, and the video bios is enabled the first channel timer test is over: the 8254 oline timer is about to complete the test the first 64dk ram was the seventh failuretest the video memory, if the instal

17、lation of the video bios is passed by, it can be bypassed. the oth channel timer test is over; the memory is being updated soon. the first 64dk ram was the eighth failure.test the interrupt controller (8259) for the first channe 1. the memory is now being updated and the memory is updated the first

18、64dk ram was the ninth failure1a test the interrupt controller (8259) of channel 2. the memory update line is being triggered to check for 15microseconds/bteaks. the first 64dk ram was the 10th faultib test cmos battery level complete memory update time 30 microsecond tests: the basic 64k memory tes

19、t is about to begin. the first 64dk ram was the 11th failure1c test cmos total the first 64dk ram was the 12th fa訂ure.id sets the cmos configuration. the first 64dk ram no. 13 failedie determines the size of the system memory and compares it to the cmos value the first 64dk ram was the 14th failurei

20、f test 64k memory to the highest 640k. the first 64dk ram was the 15th failuremeasure fixed 8259 interrupt bit start the basic 64k memory test; will test the address line dependent dma register tests are ongoing or failingmaintain an unblocking interrupt (nmi) bit (check for parity or input/output c

21、hannels) through the address line test: it's about to trigger parity. the primary dma register test is ongoing or failingtest the interrupt function of 8259 end trigger parity; the serial data read/write test will begin. the main interrupt mask registers test is being performed or failed.test pr

22、otection mode 8086 virtual mode and 8086 page mode basic 64k serial data read/write tests are normal; any adjustment before the interrupt vector initialization is about to begin the dependent interrupt mask memory test is being performed or failedmeasuring more than 1mb of extended memory. any adjus

23、tment prior to the initialization of the vector will begin the initial preparation of the interrupt vector set the es segment address register to the memory high end.test all memory after the first 64k complete the initial preparation of the interrupt vector; the input/output port of 8042 will be re

24、ad for rotary interrupter. the load interrupt vector is being performed or failedexceptions to the method of test protection. read 8042 input/output ports: it is about to start preparing the global data for a rotational interruption. open the a20 address line; let the entry in.to determine the contr

25、ol or block ram of the super-fast buffer memory. all 1 data is initially ready for completion;then any initial preparation after the interrupt vector is performed keyboard controller tests are ongoing or maifunction.determine the control of super-fast buffer memory or special 8042 keyboard controlle

26、r. the initial preparation after completing the interrupt vector; the color scheme is about to be adjusted cmos power failure/check summation is ongoing.the color scheme of the ordered color will be adjusted a review of the effectiveness of the cmos configuration is ongoing2a makes the keyboard cont

27、roller initial preparation color mode has been adjusted to trigger parity before the rom test empty 64k base memory.make the disk drive and the controller initial preparation trigger parity; you will control any adjustments required before the optional video rom. screen memory tests are ongoing or f

28、ailing2c check the serial port and prepare the origina 1. finish before the video rom control; check out the optional video rom and control it. screen initial preparation is ongoing or malfunction.2d detects parallel ports and makes the work initial ready. completed optional video rom control, which

29、 will be controlled by any other processing after the video rom restore contro1. screen rescan tests are ongoing or fai1.2e makes hard disk drives and controllers initial preparation. processing recovery from video rom control: if no ega/vga is found to be on display memory read/write tests testing

30、the video rom is ongoing2f tests the math coprocessor and prepares the work didn，t find ega/vga; will start the display memory read/write testestablish basic memory and extend memory. read/write tests on display memory. a scan is pending think that screens worktest the selection of rom from c800:0 t

31、o efff: 0, and make the work initia1. the display memory reads/writes tests or scans fail, and another display memory reads/writes tests monochrome monitors can workthe i/o chip programming for the com/ltp/fdd/sound device on the motherboard is suitable for setting values read/write tests on another

32、 monitor; another display scan will be performed the color monitor (40 columns) can work333. the video monitor is over will begin to use the adjustment switch and the actual card to check the type of display. color monitors (80 columns) can workthe display adapter has been inspected; then the displa

33、y mode is set the timer ticks off the test and the test is in or outcomplete the set up display mode; the data area for the bios rom will be examined the outage test is on or off.the bios rom data area has been checked; the cursor that is about to adjust the information a - 20 failed in the door cir

34、cuit337 the cursor that identifies the information is completed; the message is about to be displayed unexpected interruptions in the protection modecomplete the display of the electrical information; read the new cursor position. the ram test is running or the address failureread the save cursor po

35、sition and display the reference information string.3a will display < esc > information interval timer channel 2 test or malfunction3b uses the opti circuit (only 486) to make the auxiliary supercache memory initial preparation. already shown < esc > information; virtual mode, the memory

36、 test is about to start daily calendar clock tests are ongoing or malfunction3c establishes the mark that allows access to cmos settings serial port tests are ongoing or failing3d initialization keyboard/ps2 mouse/pnp device and total memory node parallel port tests are ongoing or failing.3e tries t

37、o open the l2 cache the math coprocessor test is being performed or failedstart preparing for virtual tests; it's going to be tested from the video memory.adjust the cpu speed to match the peripheral clockthe 41st interrupt is opened, and the data is initialized to detect the memory transform (i

38、nterrupt controller or memory) from the video memory test prepare the descriptor table system plugin board selection failed42 displays the window into setup the descriptor table is ready: virtual methods are about to be tested in memory. extend the cmos ram failureif the bios is plug and play, the s

39、erial port and the port are initialized. enter the virtual mode; an interrupt is about to be implemented for diagnosticsthe interrupt is implemented (for example, the diagnostic switch is on; the data is about to be initialized to check the memory in 0:0.) the bios interrupt is initialized45 initial

40、izes the math coprocessor the data is initially prepared; the memory is going to be checked at 0:0 and the size of the system memory.the test memory is returned; the memory size is computed and the page is written to test the memory. check the read-only memory rom versionwritten to the page.the basi

41、c memory is written to the page; the memory that is about to be determined over 1mb video check, cmos reconfiguration.identify and verify the memory of ibm. the memory that is about to be determined over 1mb4a find more than 1mb of memory and check it. will check the bios rom data area you initializ

42、e the video.4b the examination of the bios rom data area is over, and will check < esc > and the memory for the soft reset of 1mb4c. eliminate 1mb of memory (soft reset) to remove more than 1mb of memory.4d has cleared more than 1mb of memory (soft reset) ; will save the size of the memory.4e

43、if there is a mistake; display the error message on the display and wait for the customer to press the < fl > key to continue test of memory: (no soft reset) ; a test that will show the first 64k memory. display copyright information.4f read and write soft, hard disk data, dos boot start showi

44、ng the size of the memory and are testing the memory to update it; serial and random memory tests will be performedthe cmos value of the current bios is stored in the cmos. complete memory testing under 1mb; the size of the upcoming cache to be redefined and masked send the cpu type and speed to the

45、 screen.test more than 1mb of memory.all the isa read-only memory rom is initialized, and the initialization of the irq is eventually assigned to the pci. more than 1mb of memory testing; ready to go back to the real address enter keyboard detection.if the bios is not plug and play, the value of the

46、 serial port, parallel port, and settings is initialized save the size of the cpu register and memory, and will enter the real addresssuccessfully start the real address: the register that will be saved when the recovery is ready for downtime scanning "hit keythe register has been restored and

47、will disable the address line of the door circuit a-20.successfully disable the a-20 address line; will check the bios rom data area the keyboard test is overthe bios rom data area is half checked; to continuethe data section of the bios rom is completed; will clear the < esc > infonnation. no

48、 interrupt testing is sethas cleared the < esc > information; infonnation is displayed;the tests for dma and interrupt controllers are about tobegin. 5a. displays the settings under the f2 key5b. test the base memory address5c test 640k base memory.set up the hard disk to boot the fan area vir

49、us protection function. testing through dma page registers: the video memory will be tested test the extended memory.displays the system configuration table the video memory test is over; testing of the dma# 1 base register is pendingstart system boot with interrupt 19h. testing through the dma# 1 b

50、ase register; a test for dma# 2 registers is pending test the extended memory address linepass the dma# 2 basic register test; wi.ll check the bios rom data areathe bios rom data area is examined in half and continuesthe bios rom data area check is over; the dma devices 1 and 2 will be programmedthe

51、 dma device 1 and 2 are programmed to end; you will be using the no. 59 interrupt controller for initial preparation. the cache registry is optimized for configuration.the initial preparations for 8259 are over; the keyboard test is about to beginmake external cache and cpu internal cache work6a.tes

52、t and display the external cache values.6c.displays blocked content.6e.displays the attached configuration information.the detected error code is sent to the screen.the test configuration is incorrect.test the real-time clockscanning keyboard errors7a. . lock the keyboard.7c. set the hardware interr

53、upt vector.7e. . test the installation of a math processorthe keyboard test begins, the key is being cleared and checked, and the keyboard is about to be restored close programmable input/output devicesfind the key to the wrong keyboard a test command to issue keyboard control portsthe keyboard cont

54、roller interface test is over and will be written to the command byte and the loop buffer for initial preparation. check and install the fixed rs232 interface (serial port)having written to the command byte, the initial preparation of the global data has been completed; you are going to check for a

55、key lockcheck if there is a lock key to check whether the memory is mismatched with the cmos check and install the fixed parallel port the memory size; the soft error and password or bypass arrangement will be displayedchecking the password; the program is about to be pre-arranged re-open the programmable i/o device and detect if there is a conflict between fixed i/o.complete th