基于VHDL語言的簡(jiǎn)易電子鐘課程設(shè)計(jì)

1、 設(shè)計(jì)題目：簡(jiǎn)易數(shù)字電子鐘 專業(yè)班級(jí): 電子信息工程二班學(xué)號(hào)：姓名：指導(dǎo)教師： 引言 目錄第1章 數(shù)字電子鐘計(jì)內(nèi)容及要求 ·······································1.1 設(shè)

2、計(jì)內(nèi)容 ·················································&#

3、183;·········· 1.2功能說明 ······································

4、;······················第二章數(shù)字電子鐘系統(tǒng)框圖及工作原理·························

5、········ 2.1 系統(tǒng)框圖 ········································&#

6、183;·········· 2.2 電子鐘總體工作原理與設(shè)計(jì) ····································&#

7、183; 第3章 各功能模塊的設(shè)計(jì) 3.1正常計(jì)時(shí)模塊 3.2分頻模塊產(chǎn)生電路 3.3分時(shí)模塊產(chǎn)生電路 3.4秒模塊產(chǎn)生電路 3.5分模塊產(chǎn)生電路 3.6時(shí)模塊產(chǎn)生電路 3.7掃描模塊產(chǎn)生電路第四章系統(tǒng)調(diào)試與分析································&#

8、183;············· 4.1 系統(tǒng)調(diào)試···································

9、;·················· 4.1.1 調(diào)試方法······························

10、··················· 4.1.2 調(diào)試故障及解決方法····························&#

11、183;··········· 4.2 結(jié)果分析·····································

12、;················· 第五章 課程設(shè)計(jì)感想·······························

13、·············· 引言數(shù)字時(shí)鐘是一種用數(shù)字電路技術(shù)實(shí)現(xiàn)時(shí)、分、秒計(jì)時(shí)的裝置，數(shù)字時(shí)鐘走時(shí)精度高，穩(wěn)定性好，使用方便，不需要經(jīng)常調(diào)校，數(shù)字式時(shí)鐘用秒脈沖發(fā)生器的精度穩(wěn)定保證了數(shù)字鐘的質(zhì)量電子設(shè)計(jì)自動(dòng)化（eda）技術(shù)發(fā)展越來越迅速，利用計(jì)算機(jī)輔助設(shè)計(jì)已成為發(fā)展趨勢(shì)。vhdl語言具有強(qiáng)大的電路描述和建模能力，用vhdl開發(fā)的數(shù)字電路與開發(fā)平臺(tái)以及硬件實(shí)現(xiàn)芯片無關(guān)，可移植性、可重用性好。vhdl語言能夠在系統(tǒng)級(jí)、行為級(jí)、寄存器傳輸級(jí)、門級(jí)等各個(gè)層次對(duì)數(shù)

14、字電路進(jìn)行描述，并可以在不同層次進(jìn)行不同級(jí)別的仿真，能極大得保證設(shè)計(jì)的正確性和設(shè)計(jì)指標(biāo)的實(shí)現(xiàn)。quartus 設(shè)計(jì)軟件提供了一個(gè)完整的、多平臺(tái)的設(shè)計(jì)環(huán)境，它可以輕易滿足特定設(shè)計(jì)項(xiàng)目的要求。數(shù)字時(shí)鐘是一種用數(shù)字電路技術(shù)實(shí)現(xiàn)時(shí)、分、秒計(jì)時(shí)的裝置，數(shù)字時(shí)鐘走時(shí)精度高，穩(wěn)定性好，使用方便，不需要經(jīng)常調(diào)校，數(shù)字式時(shí)鐘用秒脈沖發(fā)生器的精度穩(wěn)定保證了數(shù)字鐘的質(zhì)量第一章 數(shù)字電子鐘計(jì)內(nèi)容及要求1.1設(shè)計(jì)內(nèi)容1學(xué)習(xí)altera公司的fpga/cpld的結(jié)構(gòu)、特點(diǎn)和性能。2學(xué)習(xí)集成開發(fā)軟件max+plus ii/quartus ii的使用及設(shè)計(jì)過程。3熟悉eda工具設(shè)計(jì)數(shù)字電路設(shè)計(jì)方法，掌握vhdl硬件描述語言設(shè)

15、計(jì)方法。4根據(jù)給定題目設(shè)計(jì)數(shù)字電路，來加深對(duì)可編程邏輯器件的理解和掌握。1.2功能要求說明1在所選擇器件內(nèi)完成簡(jiǎn)易時(shí)鐘的設(shè)計(jì)，要求設(shè)計(jì)完成后芯片具有時(shí)、分、秒的計(jì)時(shí)；譯碼；輸出七段碼；最大計(jì)時(shí)23時(shí)59分59秒；秒閃功能。2簡(jiǎn)易時(shí)鐘要求具有對(duì)時(shí)功能，具體對(duì)時(shí)的實(shí)現(xiàn)方式自行決定，要求設(shè)計(jì)合理，以操作簡(jiǎn)單為原則（根具具體的工作進(jìn)度，可以考慮增加整點(diǎn)報(bào)時(shí)等附加功能）。3在相應(yīng)的器件平臺(tái)上完成設(shè)計(jì)的輸入、編譯、綜合或適配通過。第二章 數(shù)字電子鐘系統(tǒng)框圖及工作原理2.1工作原理 系統(tǒng)主要由振蕩器、分頻器、計(jì)數(shù)器、譯碼顯示電路和校時(shí)電路組成。振蕩器產(chǎn)生穩(wěn)定的分頻脈沖信號(hào)，作為數(shù)字鐘的時(shí)間基準(zhǔn)，然后經(jīng)過分頻

16、器輸出標(biāo)準(zhǔn)秒脈沖。秒計(jì)數(shù)器滿60分向分計(jì)數(shù)器進(jìn)位，分計(jì)數(shù)器滿60后向小時(shí)計(jì)數(shù)器進(jìn)位，小時(shí)計(jì)數(shù)器按照二十四進(jìn)制計(jì)數(shù)。計(jì)數(shù)器的輸出分別由譯碼器送顯示器顯示。2.2設(shè)計(jì)內(nèi)容 數(shù)字電子鐘由振蕩器、分頻器、計(jì)數(shù)器、譯碼顯示電路和校時(shí)電路組成。振蕩器產(chǎn)生穩(wěn)定的高頻脈沖信號(hào),作為數(shù)字鐘的時(shí)間基準(zhǔn),然后經(jīng)過分頻器輸出標(biāo)準(zhǔn)秒脈沖。秒計(jì)數(shù)器滿60后向分計(jì)數(shù)器進(jìn)位,分計(jì)數(shù)器滿60后向小時(shí)計(jì)數(shù)器進(jìn)位,小時(shí)計(jì)數(shù)器按照“24翻1”規(guī)律計(jì)數(shù)。計(jì)數(shù)器的輸出分別經(jīng)譯碼器送顯示器顯示。1）時(shí)鐘產(chǎn)生電路。將開發(fā)板上的時(shí)鐘信號(hào)經(jīng)過分頻得到不同頻率的時(shí)鐘，分別作用于定時(shí)計(jì)數(shù)、led掃描。 2)控制邏輯電路。完成電子鐘的系統(tǒng)邏輯控制。

17、3)計(jì)時(shí)電路。主要按照時(shí)鐘模式完成計(jì)時(shí)功能。 4)譯碼電路。根據(jù)計(jì)時(shí)模塊的狀態(tài)輸出值來確定對(duì)應(yīng)位的數(shù)據(jù)，從而驅(qū)動(dòng)顯示電路。 5)顯示控制電路。主要執(zhí)行選擇所對(duì)應(yīng)位的數(shù)據(jù)功能，顯示正確的時(shí)間。第三章各功能模塊的設(shè)計(jì) 頂層電路設(shè)計(jì)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity zong isport( cp,rst:in std_logic; out1: out std_logic_vector(7 downto 0); out2

18、: out std_logic_vector(7 downto 0); end zong; architecture rtl of zong is component fenpin/調(diào)用分頻電路port( clk1: in std_logic; clk:out std_logic );end component;component fenshi/調(diào)用分時(shí)電路port( clks,rst: in std_logic; sl,sh,ml,mh,hl,hh:in std_logic_vector(3 downto 0); num: out std_logic_vector(3 downto 0);

19、outbit:out std_logic_vector(7 downto 0);end component;component second/調(diào)用秒電路port(clk,rst:in std_logic; enmin:out std_logic; sh:out std_logic_vector(3 downto 0); sl:out std_logic_vector(3 downto 0) );end component;component minute/調(diào)用分電路 port(clk1,rst:in std_logic; enhor:out std_logic; mh:out std_logi

20、c_vector(3 downto 0); ml:out std_logic_vector(3 downto 0) );end component;component hour/調(diào)用小時(shí)電路port(clk2,rst:in std_logic; hh:out std_logic_vector(3 downto 0); hl:out std_logic_vector(3 downto 0) ); end component; component clks/調(diào)用掃描脈沖電路port( clk1:in std_logic; clks:out std_logic); end component; co

21、mponent saomiao/調(diào)用掃描電路port( clk1: in std_logic; clks: out std_logic); end component; component saomiao2/調(diào)用翻譯電路 port( clks:in std_logic; num:in std_logic_vector(3 downto 0); outled:out std_logic_vector(7 downto 0); end component; signal clk,clk2,enmin,enhor:std_logic; signal s0,s1,m0,m1,h0,h1,num:std

22、_logic_vector(3 downto 0 ); begin u0:fenpin port map(cp,clk); u1:fenshi port map(clk2,rst,s0,s1,m0,m1,h0,h1,num,out1); u2:second port map(clk,rst,enmin,s1,s0); u3:minute port map(enmin,rst,enhor,m1,m0); u4:hour port map(enhor,rst,m1,m0); u5:clks port map(cp,clk2); u6:saomiao port map(cp,clk2); u7:sa

23、omiao2port map(clk2,num,out2); end rtl;3.1 正常掃描（分時(shí)復(fù)用脈沖）模塊產(chǎn)生電路 library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all; entity clks is port( clk1: in std_logic; clks:out std_logic);end clks; architecture a_counter of clks is signal hm: std_logic_vector(24 downto 0); signal fpb: std_l

24、ogic; begin process(clk1) begin if (clk1'event and clk1='1') then if hm=50 then hm<="0000000000000000000000000" fpb<=not fpb; else hm<=hm+1; end if; end if; end process; end a_counter;3.2分頻模塊電路設(shè)計(jì)（產(chǎn)生秒脈沖）library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigne

25、d.all; entity fenpin is port( clk1: in std_logic; clk:out std_logic );end fenpin; architecture a_counter of fenpin is signal lm : std_logic_vector(24 downto 0); signal fpa: std_logic; begin process(clk1) begin if (clk1'event and clk1='1') then if lm=24999999 then lm<="00000000000

26、00000000000000" fpa<=not fpa; else lm<=lm+1; end if; end if; end process; end a_counter; 3.2分時(shí)模塊電路電路（分時(shí)復(fù)用）library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all; entity fenshi is port( clks,rst: in std_logic; sl,sh,ml,mh,hl,hh:in std_logic_vector(3 downto 0); num: out st

27、d_logic_vector(3 downto 0); outbit:out std_logic_vector(7 downto 0);end fenshi; architecture a_counter of fenshi is signal st:std_logic_vector(2 downto 0); begin process (clks) begin if(clks'event and clks='1') then st<=st+1; end if; end process; process (st) begin case st is when &qu

28、ot;000" =>num<=sl; outbit<="00000010" when "001"=>num<=sh; outbit<="00100000" when "010"=>num<=ml; outbit<="00010000" when "011"=>num<=mh; outbit<="00001000" when "100"=>num<

29、;=hl; outbit<="00000100" when "101"=>num<=hh; outbit<="00000001" when others=>outbit<="00000000" end case; end process; end a_counter; 3.4秒模塊生成電路設(shè)計(jì)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity second is port(

30、clk,rst:in std_logic; enmin:out std_logic; sh:buffer std_logic_vector(3 downto 0); sl:buffer std_logic_vector(3 downto 0) );end second;architecture arch_tcx of second isbegin process(clk,rst) begin if rst='0' then sl<="0000" sh<="0000" enmin<='0' elsif (c

31、lk'event and clk='1') then if sl=9 then sl<="0000" if sh=5 then enmin<='1' sh<="0000" else sh<=sh+1; end if; else sl<=sl+1; end if; end if; end process; end arch_tcx;3.5 分模塊生成電路設(shè)計(jì)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsign

32、ed.all;entity minute is port(clk1,rst:in std_logic; enhor:out std_logic; mh:inout std_logic_vector(3 downto 0); ml:inout std_logic_vector(3 downto 0) );end minute;architecture arch_tcx of minute is signal en2: std_logic_vector(1 downto 0); signal sl,sh:std_logic_vector(3 downto 0); begin process(clk

33、1,rst) begin if rst='0' then ml<="0000" mh<="0000" enhor<='0' elsif (clk1'event and clk1='1') then if ml=9 then ml<="0000" if sh=5 then enhor<='1' mh<="0000" else mh<=mh+1; end if; else ml<=ml+1; end

34、if; end if; end process; end arch_tcx;3.6 時(shí)模塊生成電路設(shè)計(jì) library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity hour is port(clk2,rst:in std_logic; hh:inout std_logic_vector(3 downto 0); hl:inout std_logic_vector(3 downto 0) );end hour;architecture arch_tcx of hour is begin proce

35、ss(clk2,rst) begin if rst='0' then hl<="0000" hh<="0000" elsif (clk2'event and clk2='1') then if hl=4 then hl<="0000" if hh=2 then hh<="0000" else hh<=hh+1; end if; else hl<=hl+1; end if; end if; end process; end arch_tcx;

36、3.7 翻譯模塊生成電路設(shè)計(jì)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all; entity saomiao2 is port( clks:in std_logic; num:in std_logic_vector(3 downto 0); outled:out std_logic_vector(7 downto 0);end saomiao2; architecture a_counter of saomiao2 isbegin process(clks)begin case num is whe

37、n "0001"=>outled<="00000110" when "0010"=>outled<="01011011" when "0011"=>outled<="01001111" when "0100"=>outled<="01100110" when "0101"=>outled<="01101101" when "01

38、10"=>outled<="01111101" when "0111"=>outled<="00000111" when "1000"=>outled<="01111111" when "1001"=>outled<="01101111" when "0000"=>outled<="00111111" when "1010"=&

39、gt;outled<="01110111" when "1011"=>outled<="01111100" when "1100"=>outled<="00111001" when "1101"=>outled<="01011110" when "1110"=>outled<="01111001" when "1111"=>outled&

40、lt;="01110001" when others=>outled<="00111111" end case; end process; end a_counter; 第四章 系統(tǒng)調(diào)試與分析4.1 系統(tǒng)調(diào)試4.1.1 調(diào)試方法實(shí)驗(yàn)運(yùn)用的是vhdl語言與原理圖混合設(shè)計(jì)的方法，因此有程序調(diào)試和原理圖調(diào)試兩部分。實(shí)驗(yàn)步驟如下：1、 新建工程、vhdl文檔輸入設(shè)計(jì)模塊子程序2、 調(diào)試各個(gè)子程序是否存在語法錯(cuò)誤的問題3、 對(duì)各子模塊進(jìn)行波形仿真，驗(yàn)證輸出是否正確4、 各子模塊生成圖元文件5、 新建工程、原理圖文檔，將各個(gè)子模塊文件夾下的文檔拷貝到新建工程中6、 根據(jù)系統(tǒng)設(shè)計(jì)框圖將各個(gè)模塊圖元文件連接成原理圖7、 檢驗(yàn)原理圖是否正確8、 最后原理圖仿真，檢查波形圖是否正確4.1.2 調(diào)試故障及解決方法 在整個(gè)實(shí)驗(yàn)調(diào)試過程中，最主要出現(xiàn)的問題是對(duì)vhdl語言的不熟悉，導(dǎo)致在程序編寫