第6章Verilog HDL測(cè)試模塊

1、第6章 Verilog HDL測(cè)試模塊Verilog HDL數(shù)字系統(tǒng)設(shè)計(jì)及仿真Verilog HDL數(shù)字系統(tǒng)設(shè)計(jì)及仿真數(shù)字系統(tǒng)設(shè)計(jì)及仿真2測(cè)試模塊范例測(cè)試模塊范例module tb_add4; /頂層模塊頂層模塊wire COUT;wire 3:0 S;reg CIN;reg 3:0X,Y; /變量聲明變量聲明initialbegin X=4b0000;Y=4b0000;CIN=1; #10 X=4b0000;Y=4b1110;CIN=1; #10 X=4b0101;Y=4b1010;CIN=1; #10 X=4b0000;Y=4b0000;CIN=0; #10 X=4b0000;Y=4b11

2、10;CIN=0; #10 X=4b0101;Y=4b1010;CIN=0; /產(chǎn)生信號(hào)產(chǎn)生信號(hào) #10 $stop; /仿真控制仿真控制endinitialbegin $monitor(x=%b,y=%b,cin=%b,sum=%b,cout=%b,X,Y,CIN,S,COUT); /監(jiān)視任務(wù)監(jiān)視任務(wù)endadd4 my_add4(S,COUT,CIN,X,Y); /待測(cè)模塊的模塊實(shí)例化待測(cè)模塊的模塊實(shí)例化endmoduleVerilog HDL數(shù)字系統(tǒng)設(shè)計(jì)及仿真數(shù)字系統(tǒng)設(shè)計(jì)及仿真3測(cè)試模塊結(jié)構(gòu)測(cè)試模塊結(jié)構(gòu)模塊實(shí)例化、信號(hào)的產(chǎn)生和控制、響模塊實(shí)例化、信號(hào)的產(chǎn)生和控制、響應(yīng)監(jiān)控三個(gè)部分應(yīng)監(jiān)控三

3、個(gè)部分 Verilog HDL數(shù)字系統(tǒng)設(shè)計(jì)及仿真數(shù)字系統(tǒng)設(shè)計(jì)及仿真4時(shí)鐘信號(hào)時(shí)鐘信號(hào) 占空比占空比50%reg clock1;initial clock1=0;always #5 clock1=clock1;reg clock2;always begin #5 clock2=0; #5 clock2=1;endVerilog HDL數(shù)字系統(tǒng)設(shè)計(jì)及仿真數(shù)字系統(tǒng)設(shè)計(jì)及仿真5占空比非占空比非50%reg clock3;always begin #15 clock3=0; #5 clock3=1;endVerilog HDL數(shù)字系統(tǒng)設(shè)計(jì)及仿真數(shù)字系統(tǒng)設(shè)計(jì)及仿真6使用參數(shù)使用參數(shù)reg clock6;p

4、arameter half_cycle=10alwaysbegin #half_cycle clock6=0; #half_cycle clock6=1;endVerilog HDL數(shù)字系統(tǒng)設(shè)計(jì)及仿真數(shù)字系統(tǒng)設(shè)計(jì)及仿真7整型和寄存器型的區(qū)別整型和寄存器型的區(qū)別timescale 1ns/1nsreg clock8;parameter cycle=15;alwaysbegin #(cycle/2) clock8=0; #(cycle/2) clock8=1;endalwaysbegin #(cycle/2.0) clock9=0; #(cycle/2.0) clock9=1;endVerilog

5、 HDL數(shù)字系統(tǒng)設(shè)計(jì)及仿真數(shù)字系統(tǒng)設(shè)計(jì)及仿真8復(fù)位信號(hào)復(fù)位信號(hào) 最簡(jiǎn)單的形式最簡(jiǎn)單的形式reg reset1;initialbegin reset1=1b0; #20 reset1=1b1; #40 reset1=1b0;endVerilog HDL數(shù)字系統(tǒng)設(shè)計(jì)及仿真數(shù)字系統(tǒng)設(shè)計(jì)及仿真9檢測(cè)時(shí)鐘邊沿的復(fù)位信號(hào)檢測(cè)時(shí)鐘邊沿的復(fù)位信號(hào)reg reset2;initialbegin reset2=1b0; wait(clock=1b1); (negedge clock); reset2=1b1; repeat (2) (negedge clock); reset2=1b0;endVerilog HD

6、L數(shù)字系統(tǒng)設(shè)計(jì)及仿真數(shù)字系統(tǒng)設(shè)計(jì)及仿真10測(cè)試向量測(cè)試向量 逐個(gè)給出的形式逐個(gè)給出的形式initialbegin X=4b0000;Y=4b0000;CIN=1; #10 X=4b0000;Y=4b1110;CIN=1; #10 X=4b0101;Y=4b1010;CIN=1; #10 X=4b0000;Y=4b0000;CIN=0; #10 X=4b0000;Y=4b1110;CIN=0; #10 X=4b0101;Y=4b1010;CIN=0; #10 ; endVerilog HDL數(shù)字系統(tǒng)設(shè)計(jì)及仿真數(shù)字系統(tǒng)設(shè)計(jì)及仿真11隨機(jī)數(shù)的形式隨機(jī)數(shù)的形式integer seed1,seed2,s

7、eed3;initial begin seed1=1;seed2=2;seed3=3; /種子初始化種子初始化endalways begin #10 X=($random(seed1)/16); Y=($random(seed2)/16); CIN=($random(seed3)/2);endVerilog HDL數(shù)字系統(tǒng)設(shè)計(jì)及仿真數(shù)字系統(tǒng)設(shè)計(jì)及仿真12使用使用$readmemb 的形式的形式reg 8:0 mem0:4; /定義存儲(chǔ)器定義存儲(chǔ)器integer i=0;initial$readmemb(vec.txt,mem); /讀入數(shù)值讀入數(shù)值alwaysbegin #10 X,Y,CIN

8、=memi; /memi進(jìn)行賦值進(jìn)行賦值 i=i+1; /i要變化要變化end001000011010100100011101001010010101101010111Verilog HDL數(shù)字系統(tǒng)設(shè)計(jì)及仿真數(shù)字系統(tǒng)設(shè)計(jì)及仿真13響應(yīng)監(jiān)控響應(yīng)監(jiān)控 構(gòu)造一組黃金向量構(gòu)造一組黃金向量xxxxxxxxxxxxxx /第第1行行0000000000000001001000111010100011101011110000001010011011001010101111 /第第10行行01100000001100 /第第11行行01000011110000initial$readmemb(vec.txt,

9、mem); alwaysbegin #10 temp=memi; X,Y,CIN=temp13:5; S_ref,COUT_ref=temp4:0; i=i+1;endVerilog HDL數(shù)字系統(tǒng)設(shè)計(jì)及仿真數(shù)字系統(tǒng)設(shè)計(jì)及仿真14結(jié)果相符時(shí)結(jié)果相符時(shí)Verilog HDL數(shù)字系統(tǒng)設(shè)計(jì)及仿真數(shù)字系統(tǒng)設(shè)計(jì)及仿真15結(jié)果不符時(shí)結(jié)果不符時(shí)Verilog HDL數(shù)字系統(tǒng)設(shè)計(jì)及仿真數(shù)字系統(tǒng)設(shè)計(jì)及仿真16也可以添加任務(wù)也可以添加任務(wù)always (S,COUT) begin if(S!=S_ref | COUT!= COUT_ref ) $strobe($realtime,The result is wro

10、ng, right S=%b,COUT=%b, but current S=%b,COUT=%b,S_ref,COUT_ref,S,COUT);endVerilog HDL數(shù)字系統(tǒng)設(shè)計(jì)及仿真數(shù)字系統(tǒng)設(shè)計(jì)及仿真17更復(fù)雜的形式更復(fù)雜的形式always (S,COUT) begin if(S!=S_ref | COUT!= COUT_ref ) begin $strobe($realtime,The result is wrong, right S=%b,COUT=%b,but current right S=%b,COUT=%b,S_ref,COUT_ref,S,COUT); case(S=S_

11、ref),(COUT=COUT_ref) 2b10:$strobe(the %s is wrong!,COUT); 2b01:$strobe(the %s is wrong!,S); 2b11:$strobe(the %s is wrong!, both S and COUT); endcase endend# 100The result is wrong, right S=0111,COUT=0,but current right S=0111,COUT=1# the COUT is wrong!# 110The result is wrong, right S=0111,COUT=0,bu

12、t current right S=0110,COUT=0# the S is wrong!Verilog HDL數(shù)字系統(tǒng)設(shè)計(jì)及仿真數(shù)字系統(tǒng)設(shè)計(jì)及仿真18仿真中對(duì)信號(hào)的控制仿真中對(duì)信號(hào)的控制 wait語(yǔ)句：等待條件達(dá)成語(yǔ)句：等待條件達(dá)成initial wait(reset2)begin (posedge clock); #4 q=1; #8 qb) -sub; /a大于大于b激活激活sub事件事件 else -add; /否則激活否則激活add事件事件endalways (sub) /該事件可被該事件可被檢測(cè)，并觸發(fā)檢測(cè)，并觸發(fā)always結(jié)構(gòu)結(jié)構(gòu)out_ref=a-b;always (add

13、) /此段同理此段同理out_ref=a+b;Verilog HDL數(shù)字系統(tǒng)設(shè)計(jì)及仿真數(shù)字系統(tǒng)設(shè)計(jì)及仿真21組合邏輯的測(cè)試模塊組合邏輯的測(cè)試模塊 設(shè)計(jì)模塊：設(shè)計(jì)模塊：3-8譯碼器譯碼器module decoder3x8(din,en,dout,ex);input 2:0 din;input en;output 7:0 dout;output ex;reg 7:0 dout;reg ex;always (din or en)if(en) begin dout=8b1111_1111; ex=1b1; end else begin case(din) 3b000: begin dout=8b111

14、1_1110; ex=1b0; end 3b001: begin dout=8b1111_1101; ex=1b0; end 3b010: begin dout=8b1111_1011; ex=1b0; endVerilog HDL數(shù)字系統(tǒng)設(shè)計(jì)及仿真數(shù)字系統(tǒng)設(shè)計(jì)及仿真22設(shè)計(jì)模塊：設(shè)計(jì)模塊：3-8譯碼器譯碼器 3b011: begin dout=8b1111_0111; ex=1b0; end 3b100: begin dout=8b1110_1111; ex=1b0; end 3b101: begin dout=8b1101_1111; ex=1b0; end 3b110: begin do

15、ut=8b1011_1111; ex=1b0; end 3b111: begin dout=8b0111_1111; ex=1b0; end default:begin dout=8b1111_1111; ex=1b0; end endcase endendmoduleVerilog HDL數(shù)字系統(tǒng)設(shè)計(jì)及仿真數(shù)字系統(tǒng)設(shè)計(jì)及仿真23測(cè)試信號(hào)測(cè)試信號(hào)initialbegin #10 en=0;din=3b000; #10 en=0;din=3b001; #10 en=0;din=3b010; #10 en=0;din=3b011; #10 en=0;din=3b100; #10 en=0;din=

16、3b101; #10 en=0;din=3b110; #10 en=0;din=3b111; #10 en=0;din=3b1x1; #10 en=1;din=3b000; #10 en=1;din=3b001; #10 en=1;din=3b010; #10 en=1;din=3b011; #10 en=1;din=3b100; #10 en=1;din=3b101; #10 en=1;din=3b110; #10 en=1;din=3b111; #10 $stop;endVerilog HDL數(shù)字系統(tǒng)設(shè)計(jì)及仿真數(shù)字系統(tǒng)設(shè)計(jì)及仿真24時(shí)序邏輯的測(cè)試模塊時(shí)序邏輯的測(cè)試模塊 4位的并串轉(zhuǎn)換模塊位

17、的并串轉(zhuǎn)換模塊 module p2s(data_in,clock,reset,load,data_out,done);input 3:0 data_in;input clock,reset,load;output data_out;output done;reg done; reg 3:0 temp;reg 3:0 cnt;Verilog HDL數(shù)字系統(tǒng)設(shè)計(jì)及仿真數(shù)字系統(tǒng)設(shè)計(jì)及仿真254位的并串轉(zhuǎn)換模塊位的并串轉(zhuǎn)換模塊 always(posedge clock or posedge reset ) begin if(reset) begin temp=0; cnt=0; done=1; end

18、 else if(load) begin temp=data_in; cnt=0; done=0; endelse if(cnt=3) begin temp = temp2:0,1b0; cnt=0; done=1; end else begin temp = temp2:0,1b0; cnt=cnt+1; done=0; endendassign data_out=(done=1)?1bz:temp3; endmodule Verilog HDL數(shù)字系統(tǒng)設(shè)計(jì)及仿真數(shù)字系統(tǒng)設(shè)計(jì)及仿真26測(cè)試模塊測(cè)試模塊module tbp2s;reg 3:0 data_in;reg clock,reset,l

19、oad;wire data_out;wire done;initialbegin reset=1; #15 reset=0;endinitial clock=1;always #5 clock=clock;always (done)begin if(done=1) begin data_in=$random%16; load=1; end else begin load=0; endendVerilog HDL數(shù)字系統(tǒng)設(shè)計(jì)及仿真數(shù)字系統(tǒng)設(shè)計(jì)及仿真27always (posedge clock)if(load=1) /每次載數(shù)后判斷每次載數(shù)后判斷 begin:dis integer i; i=3

20、; repeat(4) /重復(fù)四次，即四位信號(hào)依次判斷重復(fù)四次，即四位信號(hào)依次判斷 begin (posedge clock) if(data_out=data_ini) /正確時(shí)產(chǎn)生正確輸出正確時(shí)產(chǎn)生正確輸出 $display(Output Right!); else /錯(cuò)誤時(shí)產(chǎn)生錯(cuò)誤輸出，并提示信息錯(cuò)誤時(shí)產(chǎn)生錯(cuò)誤輸出，并提示信息 $display(Bed Output!data_out= %b ,but data_in%d= %b,data_out,i,data_ini); i=i-1; end endp2s ip2s(data_in,clock,reset,load,data_out,d

21、one);endmodule Verilog HDL數(shù)字系統(tǒng)設(shè)計(jì)及仿真數(shù)字系統(tǒng)設(shè)計(jì)及仿真28仿真結(jié)果仿真結(jié)果Verilog HDL數(shù)字系統(tǒng)設(shè)計(jì)及仿真數(shù)字系統(tǒng)設(shè)計(jì)及仿真29除法器的測(cè)試模塊除法器的測(cè)試模塊 功能表功能表端口名稱(chēng)端口名稱(chēng)功能說(shuō)明功能說(shuō)明clk輸入端，時(shí)鐘信號(hào)，提供該除法器內(nèi)部運(yùn)算所需時(shí)鐘輸入端，時(shí)鐘信號(hào)，提供該除法器內(nèi)部運(yùn)算所需時(shí)鐘reset輸入端，復(fù)位信號(hào)，低電平有效輸入端，復(fù)位信號(hào)，低電平有效start輸入端，開(kāi)始信號(hào)，為高電平時(shí)開(kāi)始計(jì)算輸入端，開(kāi)始信號(hào)，為高電平時(shí)開(kāi)始計(jì)算A輸入端，輸入端，32位被除數(shù)位被除數(shù)B輸入端，輸入端，32位除數(shù)位除數(shù)D輸出端，輸出端，48位商值位商值

22、R輸出端，輸出端，32位余數(shù)位余數(shù)ok輸出端，計(jì)算完畢時(shí)輸出輸出端，計(jì)算完畢時(shí)輸出ok為高電平，此時(shí)是最終結(jié)果為高電平，此時(shí)是最終結(jié)果err輸出端，如果出現(xiàn)錯(cuò)誤則輸出高電平輸出端，如果出現(xiàn)錯(cuò)誤則輸出高電平Verilog HDL數(shù)字系統(tǒng)設(shè)計(jì)及仿真數(shù)字系統(tǒng)設(shè)計(jì)及仿真30測(cè)試模塊測(cè)試模塊參考函數(shù)參考函數(shù) function n+n+(n+m)+(n)-1:0 gen_rand_data; /函數(shù)部分，生成被除數(shù)、除數(shù)，和商與余數(shù)的參考值函數(shù)部分，生成被除數(shù)、除數(shù)，和商與余數(shù)的參考值 input integer i; reg n+m-1:0 dividend; reg n+m-1:0 divisor;

23、reg n+m-1:0 quotient; reg n+m-1:0 remainder; integer k; integer flag;Verilog HDL數(shù)字系統(tǒng)設(shè)計(jì)及仿真數(shù)字系統(tǒng)設(shè)計(jì)及仿真31begin k = (i/4) % 32 + 1; flag = 1; while(flag) begin dividend = $random, m1b0; /隨機(jī)數(shù)生成被除數(shù)，并擴(kuò)展位隨機(jī)數(shù)生成被除數(shù)，并擴(kuò)展位 divisor = m1b0, $random; /隨機(jī)數(shù)生成除數(shù)，被擴(kuò)展位隨機(jī)數(shù)生成除數(shù)，被擴(kuò)展位Verilog HDL數(shù)字系統(tǒng)設(shè)計(jì)及仿真數(shù)字系統(tǒng)設(shè)計(jì)及仿真32 divisor = divisor % ( 2 divisor) /商大于余數(shù)時(shí)報(bào)錯(cuò)商大于余數(shù)時(shí)報(bào)錯(cuò) begin $display(Bad remainder!); $s