PLL鎖相環(huán)程序

1、飛思卡爾XS128系列（一） PLL鎖相環(huán)通俗點說，設置PLL鎖相環(huán)就相當于超頻，單片機超頻的原因和PC機是一個道理。 分頻的主要原因是外設需要的工作頻率往往遠低于CPU/MEMORY，這也和PC機南北橋的原理類似。相對來說，PLL鎖相環(huán)的設置還是比較簡單的，因為東西很死，完全可以照搬。只是大家也不要太貪，設置太高相對來說不夠穩(wěn)定，進行過PC機超頻的應該很有體會，一般我們現(xiàn)在用的XS128我覺得設置在80MHz是比較合適的，相比前幾屆比賽用的DG128，這個頻率已經(jīng)蠻高的了。還有就是SYNR,REFDV只有在CLKSEL_PLLSEL=0的情況下才能寫入，不過這是系統(tǒng)默認狀態(tài)。多半大家可能還會

2、有以下幾點疑問：1.PLL鎖相環(huán)怎么設置？答：通過寫REFDV（CRG參考分頻寄存器）和SYNR（CRG合成器寄存器）進行設置2.代碼里while(!CRGFLG_LOCK);這句是干什么的？答：時鐘校正同步3.為什么代碼中會有多多少少的幾句空語句？答：鎖相環(huán)從設定到最后穩(wěn)定還是需要一點點時間的，所以需要加幾條空指令 /* - Code Warrior 5.0 Target : MC9S12XS128 Crystal: 16.000Mhz = 本程序主要包括以下功能： 設定系統(tǒng)工作在xxMHZ bus clock時鐘下; by:龐輝 */ #include /* common defines

3、and macros*/ #include /* derivative information*/ #pragma LINK_INFO DERIVATIVE mc9s12xs128 void SetBusCLK_16M(void) CLKSEL=0X00; / disengage PLL to system PLLCTL_PLLON=1; / turn on PLL SYNR=0x00 | 0x01; / VCOFRQ7:6;SYNDIV5:0 / fVCO= 2*fOSC*(SYNDIV + 1)/(REFDIV + 1) / fPLL= fVCO/(2 POSTDIV) / fBUS= f

4、PLL/2 / VCOCLK Frequency Ranges VCOFRQ7:6 / 32MHz = fVCO = 48MHz 00 / 48MHz fVCO = 80MHz 01 / Reserved 10 / 80MHz fVCO = 120MHz 11 REFDV=0x80 | 0x01; / REFFRQ7:6;REFDIV5:0 / fREF=fOSC/(REFDIV + 1) / REFCLK Frequency Ranges REFFRQ7:6 / 1MHz = fREF = 2MHz 00 / 2MHz fREF = 6MHz 01 / 6MHz fREF 12MHz 11

5、/ pllclock=2*osc*(1+SYNR)/(1+REFDV)=32MHz; POSTDIV=0x00; / 4:0, fPLL= fVCO/(2xPOSTDIV) / If POSTDIV = $00 then fPLL is identical to fVCO (divide by one). _asm(nop); / BUS CLOCK=16M _asm(nop); while(!(CRGFLG_LOCK=1); /when pll is steady ,then use it; CLKSEL_PLLSEL =1; /engage PLL to system; void SetB

6、usCLK_32M(void) CLKSEL=0X00; / disengage PLL to system PLLCTL_PLLON=1; / turn on PLL SYNR =0x40 | 0x03; / pllclock=2*osc*(1+SYNR)/(1+REFDV)=64MHz; REFDV=0x80 | 0x01; POSTDIV=0x00; _asm(nop); / BUS CLOCK=32M _asm(nop); while(!(CRGFLG_LOCK=1); /when pll is steady ,then use it; CLKSEL_PLLSEL =1; /engag

7、e PLL to system; void SetBusCLK_40M(void) CLKSEL=0X00; /disengage PLL to system PLLCTL_PLLON=1; /turn on PLL SYNR =0xc0 | 0x04; REFDV=0x80 | 0x01; POSTDIV=0x00; /pllclock=2*osc*(1+SYNR)/(1+REFDV)=80MHz; _asm(nop); /BUS CLOCK=40M _asm(nop); while(!(CRGFLG_LOCK=1); /when pll is steady ,then use it; CL

8、KSEL_PLLSEL =1; /engage PLL to system; void SetBusCLK_48M(void) CLKSEL=0X00; /disengage PLL to system PLLCTL_PLLON=1; /turn on PLL SYNR =0xc0 | 0x05; REFDV=0x80 | 0x01; POSTDIV=0x00; /pllclock=2*osc*(1+SYNR)/(1+REFDV)=96MHz; _asm(nop); /BUS CLOCK=48M _asm(nop); while(!(CRGFLG_LOCK=1); /when pll is s

9、teady ,then use it; CLKSEL_PLLSEL =1; /engage PLL to system; void SetBusCLK_64M(void) CLKSEL=0X00; /disengage PLL to system PLLCTL_PLLON=1; /turn on PLL SYNR =0xc0 | 0x07; REFDV=0x80 | 0x01; POSTDIV=0x00; /pllclock=2*osc*(1+SYNR)/(1+REFDV)=128MHz; _asm(nop); /BUS CLOCK=64M _asm(nop); while(!(CRGFLG_

10、LOCK=1); /when pll is steady ,then use it; CLKSEL_PLLSEL =1; /engage PLL to system; void SetBusCLK_80M(void) CLKSEL=0X00; /disengage PLL to system PLLCTL_PLLON=1; /turn on PLL SYNR =0xc0 | 0x09; REFDV=0x80 | 0x01; POSTDIV=0x00; /pllclock=2*osc*(1+SYNR)/(1+REFDV)=160MHz; _asm(nop); /BUS CLOCK=80M _as

11、m(nop); while(!(CRGFLG_LOCK=1); /when pll is steady ,then use it; CLKSEL_PLLSEL =1; /engage PLL to system; void SetBusCLK_88M(void) CLKSEL=0X00; /disengage PLL to system PLLCTL_PLLON=1; /turn on PLL SYNR =0xc0 | 0x0a; REFDV=0x80 | 0x01; POSTDIV=0x00; /pllclock=2*osc*(1+SYNR)/(1+REFDV)=176MHz; _asm(n

12、op); /BUS CLOCK=88M _asm(nop); while(!(CRGFLG_LOCK=1); /when pll is steady ,then use it; CLKSEL_PLLSEL =1; /engage PLL to system; void SetBusCLK_96M(void) CLKSEL=0X00; /disengage PLL to system PLLCTL_PLLON=1; /turn on PLL SYNR =0xc0 | 0x0b; REFDV=0x80 | 0x01; POSTDIV=0x00; /pllclock=2*osc*(1+SYNR)/(

13、1+REFDV)=192MHz; _asm(nop); /BUS CLOCK=96M _asm(nop); while(!(CRGFLG_LOCK=1); /when pll is steady ,then use it; CLKSEL_PLLSEL =1; /engage PLL to system; void SetBusCLK_104M(void) CLKSEL=0X00; /disengage PLL to system PLLCTL_PLLON=1; /turn on PLL SYNR =0xc0 | 0x0c; REFDV=0x80 | 0x01; POSTDIV=0x00; /p

14、llclock=2*osc*(1+SYNR)/(1+REFDV)=208MHz; _asm(nop); /BUS CLOCK=104M _asm(nop); while(!(CRGFLG_LOCK=1); /when pll is steady ,then use it; CLKSEL_PLLSEL =1; /engage PLL to system; void SetBusCLK_120M(void) CLKSEL=0X00; /disengage PLL to system PLLCTL_PLLON=1; /turn on PLL SYNR =0xc0 | 0x0d; REFDV=0x80 | 0x01; POSTDIV=0x00; /pllclock=