杭電計(jì)組實(shí)驗(yàn)4-寄存器堆設(shè)計(jì)實(shí)驗(yàn).doc

實(shí)驗(yàn)報(bào)告 2018 年 5 月 12 日 成績： 姓名陽光男學(xué)號16041321班級16052317專業(yè)計(jì)算機(jī)科學(xué)與技術(shù)課程名稱計(jì)算機(jī)組成原理與系統(tǒng)結(jié)構(gòu)試驗(yàn)任課老師張翔老師指導(dǎo)老師張翔老師機(jī)位號默認(rèn)實(shí)驗(yàn)序號4實(shí)驗(yàn)名稱實(shí)驗(yàn)四 寄存器堆設(shè)計(jì)實(shí)驗(yàn)時(shí)間2018/5/12實(shí)驗(yàn)地點(diǎn)1教211實(shí)驗(yàn)設(shè)備號個(gè)人電腦、Nexys3開發(fā)板 一、實(shí)驗(yàn)程序源代碼1.寄存器堆模塊代碼：module Register_file(R_Addr_A,R_Addr_B,W_Addr,Write_Reg,W_Data,Clk,Reset,R_Data_A,R_Data_B);input 4:0R_Addr_A;input 4:0R_Addr_B;input 4:0W_Addr;input Write_Reg;input 31:0W_Data;input Clk;input Reset;output 31:0R_Data_A;output 31:0R_Data_B;reg 31:0REG_Files0:31;reg 5:0i;initial/仿真過程中的初始化begin for(i=0;i=31;i=i+1) REG_Filesi=0;endassign R_Data_A=REG_FilesR_Addr_A;assign R_Data_B=REG_FilesR_Addr_B;always(posedge Clk or posedge Reset)begin if(Reset) for(i=0;i=31;i=i+1) REG_Filesi=0; else if(Write_Reg&W_Addr!=0) REG_FilesW_Addr=W_Data; end endmodule2.頂層電路模塊代碼：module Top_Register_file(Addr,Write_Reg,C1,C2,Clk,Reset,LED);input 4:0Addr;input 1:0C1;/C1選擇32位數(shù)據(jù)輸出哪八位字節(jié)input Write_Reg,C2,Clk,Reset;/C2選擇讀A/B端口的數(shù)據(jù)output reg 7:0LED;wire 31:0R_Data_A,R_Data_B;reg 31:0W_Data;reg4:0 A,B;Register_file reg1(A,B,Addr,Write_Reg,W_Data,Clk,Reset,R_Data_A,R_Data_B);always(Addr or Write_Reg or C1 or C2 or R_Data_A or R_Data_B)begin A=0; B=0; LED=0; W_Data=0; if(!Write_Reg)/讀操作Write_Reg=0 begin if(!C2) begin A=Addr; case(C1) 2b00:LED=R_Data_A7:0; 2b01:LED=R_Data_A15:8; 2b10:LED=R_Data_A23:16; 2b11:LED=R_Data_A31:24;endcase endelse begin B=Addr;case(C1) 2b00:LED=R_Data_B7:0; 2b01:LED=R_Data_B15:8; 2b10:LED=R_Data_B23:16; 2b11:LED=R_Data_B31:24;endcaseend end else/寫操作 begin case(C1) 2b00:W_Data=32h0000_0003; 2b01:W_Data=32h0000_0607; 2b10:W_Data=32hFFFF_FFFF; 2b11:W_Data=32h1111_1234;endcase end endendmodule3.測試代碼module test;/ Inputsreg 4:0 R_Addr_A;reg 4:0 R_Addr_B;reg 4:0 W_Addr;reg Write_Reg;reg 31:0 W_Data;reg Clk;reg Reset;/ Outputswire 31:0 R_Data_A;wire 31:0 R_Data_B;/ Instantiate the Unit Under Test (UUT)Register_file uut (.R_Addr_A(R_Addr_A), .R_Addr_B(R_Addr_B), .W_Addr(W_Addr), .Write_Reg(Write_Reg), .W_Data(W_Data), .Clk(Clk), .Reset(Reset), .R_Data_A(R_Data_A), .R_Data_B(R_Data_B);initial begin/ Initialize InputsR_Addr_A = 0;R_Addr_B = 0;W_Addr = 0;Write_Reg = 0;W_Data = 0;Clk = 0;Reset = 0;/ Wait 100 ns for global reset to finish#100;/ Add stimulus here#100;R_Addr_A = 0;R_Addr_B = 0;W_Addr = 5b00001;Write_Reg = 1;W_Data = 32h1111_1111;Clk = 1;Reset = 0;#100;R_Addr_A = 0;R_Addr_B = 0;W_Addr = 5b00001;Write_Reg = 1;W_Data = 32h1111_1111;Clk = 0;Reset = 0;#100;R_Addr_A = 0;R_Addr_B = 0;W_Addr = 5b00010;Write_Reg = 1;W_Data = 32h2222_2222;Clk = 1;Reset = 0;#100;R_Addr_A = 5b00001;R_Addr_B = 5b00010;W_Addr = 0;Write_Reg = 0;W_Data = 0;Clk = 0;Reset = 0;#100;R_Addr_A = 5b00001;R_Addr_B = 5b00010;W_Addr = 0;Write_Reg = 0;W_Data = 0;Clk = 0;Reset = 1;end endmodule二、仿真波形三、電路圖 頂層電路模塊 頂層電路內(nèi)部結(jié)構(gòu)：四、引腳配置（約束文件）NET Clk LOC = C9;NET Reset LOC = D9;NET Write_Reg LOC = T5;NET C2 LOC = C4;# PlanAhead Generated physical constraints NET LED7 LOC = T11;NET LED6 LOC = R11;NET LED4 LOC = M11;NET LED3 LOC = V15;NET LED1 LOC = V16;NET LED0 LOC = U16;NET LED2 LOC = U15;NET LED5 LOC = N11;NET Addr0 LOC = T10;NET Addr2 LOC = V9;NET Addr3 LOC = M8;NET Addr4 LOC = N8;NET C10 LOC = U8;NET C11 LOC = V8;NET Addr1 LOC = T9;五、思考與探索 (1)實(shí)驗(yàn)四實(shí)驗(yàn)結(jié)果記錄表 寄存器地址 寫入數(shù)據(jù) 讀出數(shù)據(jù) $1 32h0000_0003 32h0000_0003 $2 32h0000_0607 32h0000_0607 $3 32