PCIISA接口定義.doc

字串9Pin Name Description 引腳 名稱 含義 字串8A1 /I/O CH CK I/O channel check; active low=parity error A2 D7 Data bit 7 A3 D6 Data bit 6 A4 D5 Data bit 5 A5 D4 Data bit 4 A6 D3 Data bit 3 A7 D2 Data bit 2 A8 D1 Data bit 1 A9 D0 Data bit 0 A10 I/O CH RDY I/O Channel ready, pulled low to lengthen memory cycles A11 AEN Address enable; active high when DMA controls bus A12 A19 Address bit 19 A13 A18 Address bit 18 A14 A17 Address bit 17 A15 A16 Address bit 16 A16 A15 Address bit 15 A17 A14 Address bit 14 A18 A13 Address bit 13 A19 A12 Address bit 12 A20 A11 Address bit 11 A21 A10 Address bit 10 A22 A9 Address bit 9 A23 A8 Address bit 8 A24 A7 Address bit 7 A25 A6 Address bit 6 A26 A5 Address bit 5 A27 A4 Address bit 4 A28 A3 Address bit 3 A29 A2 Address bit 2 A30 A1 Address bit 1 字串5A31 A0 Address bit 0 B1 GND Ground B2 RESET Active high to reset or initialize system logic B3 +5V +5 VDC B4 IRQ2 Interrupt Request 2 B5 -5VDC -5 VDC B6 DRQ2 DMA Request 2 B7 -12VDC -12 VDC B8 /NOWS No WaitState B9 +12VDC +12 VDC B10 GND Ground B11 /SMEMW System Memory Write B12 /SMEMR System Memory Read B13 /IOW I/O Write B14 /IOR I/O Read B15 /DACK3 DMA Acknowledge 3 B16 DRQ3 DMA Request 3 B17 /DACK1 DMA Acknowledge 1 B18 DRQ1 DMA Request 1 B19 /REFRESH Refresh B20 CLOCK System Clock (67 ns, 8-8.33 MHz, 50% duty cycle) B21 IRQ7 Interrupt Request 7 B22 IRQ6 Interrupt Request 6 B23 IRQ5 Interrupt Request 5 B24 IRQ4 Interrupt Request 4 B25 IRQ3 Interrupt Request 3 B26 /DACK2 DMA Acknowledge 2 B27 T/C Terminal count; pulses high when DMA term. count reached B28 ALE Address Latch Enable B29 +5V +5 VDC B30 OSC High-speed Clock (70 ns, 14.31818 MHz, 50% duty cycle) 字串9B31 GND Ground C1 SBHE System bus high enable (data available on SD8-15) C2 LA23 Address bit 23 C3 LA22 Address bit 22 C4 LA21 Address bit 21 C5 LA20 Address bit 20 C6 LA18 Address bit 19 C7 LA17 Address bit 18 C8 LA16 Address bit 17 C9 /MEMR Memory Read (Active on all memory read cycles) C10 /MEMW Memory Write (Active on all memory write cycles) C11 SD08 Data bit 8 C12 SD09 Data bit 9 C13 SD10 Data bit 10 C14 SD11 Data bit 11 C15 SD12 Data bit 12 C16 SD13 Data bit 13 C17 SD14 Data bit 14 C18 SD15 Data bit 15 D1 /MEMCS16 Memory 16-bit chip select (1 wait, 16-bit memory cycle) D2 /IOCS16 I/O 16-bit chip select (1 wait, 16-bit I/O cycle) D3 IRQ10 Interrupt Request 10 D4 IRQ11 Interrupt Request 11 D5 IRQ12 Interrupt Request 12 D6 IRQ15 Interrupt Request 15 D7 IRQ14 Interrupt Request 14 D8 /DACK0 DMA Acknowledge 0 D9 DRQ0 DMA Request 0 D10 /DACK5 DMA Acknowledge 5 字串8 D11 DRQ5 DMA Request 5 D12 /DACK6 DMA Acknowledge 6 D13 DRQ6 DMA Request 6 D14 /DACK7 DMA Acknowledge 7 D15 DRQ7 DMA Request 7 D16 +5 V D17 /MASTER Used with DRQ to gain control of system D18 GND Ground Note: Direction is Motherboard relative ISA-Cards.PCI總線定義PCI是Peripheral Component Interconnect（外設(shè)部件互連標(biāo)準(zhǔn)）的縮寫，它是目前個人電腦中使用最為廣泛的接口，幾乎所有的主板產(chǎn)品上都帶有這種插槽。PCI插槽也是主板帶有最多數(shù)量的插槽類型，在目前流行的臺式機(jī)主板上，ATX結(jié)構(gòu)的主板一般帶有56個PCI插槽，而小一點(diǎn)的MATX主板也都帶有23個PCI插槽，可見其應(yīng)用的廣泛性。PCI是由Intel公司1991年推出的一種局部總線。從結(jié)構(gòu)上看，PCI是在CPU和原來的系統(tǒng)總線之間插入的一級總線，具體由一個橋接電路實現(xiàn)對這一層的管理，并實現(xiàn)上下之間的接口以協(xié)調(diào)數(shù)據(jù)的傳送。管理器提供了信號緩沖，使之能支持10種外設(shè)，并能在高時鐘頻率下保持高性能，它為顯卡，聲卡，網(wǎng)卡，MODEM等設(shè)備提供了連接接口，它的工作頻率為33MHz/66MHz。最早提出的PCI 總線工作在33MHz 頻率之下，傳輸帶寬達(dá)到了133MB/s(33MHz X 32bit/8)，基本上滿足了當(dāng)時處理器的發(fā)展需要。隨著對更高性能的要求，1993年又提出了64bit 的PCI 總線，后來又提出把PCI 總線的頻率提升到66MHz 。目前廣泛采用的是32-bit、33MHz 的PCI 總線，64bit的PCI插槽更多是應(yīng)用于服務(wù)器產(chǎn)品。由于PCI 總線只有133MB/s 的帶寬，對聲卡、網(wǎng)卡、視頻卡等絕大多數(shù)輸入/輸出設(shè)備顯得綽綽有余，但對性能日益強(qiáng)大的顯卡則無法滿足其需求。目前PCI接口的顯卡已經(jīng)不多見了，只有較老的PC上才有，廠商也很少推出此類接口的產(chǎn)品。接口卡的外觀PCI 標(biāo)準(zhǔn) 32位/64位 接口卡 -| PCI 元件側(cè) （B面） | | | | _ 32 位引腳部分 64 位引腳部分 _|_| |-|-|-| b01 b11 b14 b49 b52 b62 b63 b94PCI 5V 32/64位卡| optional | _ 32 位引腳部分 64 位引腳部分 _|_| |-|-|PCI 3.3V 32/64位卡| optional | _ 32 位引腳部分 64 位引腳部分 _|_| |-|-|引腳定義Pin+5V+3.3VUniversalDescriptionA1TRSTTest Logic ResetA2+12V+12 VDCA3TMSTest Mde SelectA4TDITest Data InputA5+5V+5 VDCA6INTAInterrupt AA7INTCInterrupt CA8+5V+5 VDCA9RESV01Reserved VDCA10+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)A11RESV03Reserved VDCA12GND03(OPEN)(OPEN)Ground or Open (Key)A13GND05(OPEN)(OPEN)Ground or Open (Key)A14RESV05Reserved VDCA15RESETResetA16+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)A17GNTGrant PCI useA18GND08GroundA19RESV06Reserved VDCA20AD30Address/Data 30A21+3.3V01+3.3 VDCA22AD28Address/Data 28A23AD26Address/Data 26A24GND10GroundA25AD24Address/Data 24A26IDSELInitialization Device SelectA27+3.3V03+3.3 VDCA28AD22Address/Data 22A29AD20Address/Data 20A30GND12GroundA31AD18Address/Data 18A32AD16Address/Data 16A33+3.3V05+3.3 VDCA34FRAMEAddress or Data phaseA35GND14GroundA36TRDYTarget ReadyA37GND15GroundA38STOPStop Transfer CycleA39+3.3V07+3.3 VDCA40SDONESnoop DoneA41SBOSnoop BackoffA42GND17GroundA43PARParityA44AD15Address/Data 15A45+3.3V10+3.3 VDCA46AD13Address/Data 13A47AD11Address/Data 11A48GND19GroundA49AD9Address/Data 9A52C/BE0Command, Byte Enable 0A53+3.3V11+3.3 VDCA54AD6Address/Data 6A55AD4Address/Data 4A56GND21GroundA57AD2Address/Data 2A58AD0Address/Data 0A59+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)A60REQ64Request 64 bit ?A61VCC11+5 VDCA62VCC13+5 VDCA63GNDGroundA64C/BE7#Command, Byte Enable 7A65C/BE5#Command, Byte Enable 5A66+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)A67PAR64Parity 64 ?A68AD62Address/Data 62A69GNDGroundA70AD60Address/Data 60A71AD58Address/Data 58A72GNDGroundA73AD56Address/Data 56A74AD54Address/Data 54A75+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)A76AD52Address/Data 52A77AD50Address/Data 50A78GNDGroundA79AD48Address/Data 48A80AD46Address/Data 46A81GNDGroundA82AD44Address/Data 44A83AD42Address/Data 42A84+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)A85AD40Address/Data 40A86AD38Address/Data 38A87GNDGroundA88AD36Address/Data 36A89AD34Address/Data 34A90GNDGroundA91AD32Address/Data 32A92RESReservedA93GNDGroundA94RESReservedB1-12V-12 VDCB2TCKTest ClockB3GNDGroundB4TDOTest Data OutputB5+5V+5 VDCB6+5V+5 VDCB7INTBInterrupt BB8INTDInterrupt DB9PRSNT1ReservedB10RES+V I/O (+5 V or +3.3 V)B11PRSNT2?B12GND(OPEN)(OPEN)Ground or Open (Key)B13GND(OPEN)(OPEN)Ground or Open (Key)B14RESReserved VDCB15GNDResetB16CLKClockB17GNDGroundB18REQRequestB19+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)B20AD31Address/Data 31B21AD29Address/Data 29B22GNDGroundB23AD27Address/Data 27B24AD25Address/Data 25B25+3.3V+3.3VDCB26C/BE3Command, Byte Enable 3B27AD23Address/Data 23B28GNDGroundB29AD21Address/Data 21B30AD19Address/Data 19B31+3.3V+3.3 VDCB32AD17Address/Data 17B33C/BE2Command, Byte Enable 2B34GND13GroundB35IRDYInitiator ReadyB36+3.3V06+3.3 VDCB37DEVSELDevice SelectB38GND16GroundB39LOCKLock busB40PERRParity ErrorB41+3.3V08+3.3 VDCB42SERRSystem ErrorB43+3.3V09+3.3 VDCB44C/BE1Command, Byte Enable 1B45AD14Address/Data 14B46GND18GroundB47AD12Address/Data 12B48AD10Address/Data 10B49GND20GroundB50(OPEN)GND(OPEN)Ground or Open (Key)B51(OPEN)GND(OPEN)Ground or Open (Key)B52AD8Address/Data 8B53AD7Address/Data 7B54+3.3V12+3.3 VDCB55AD5Address/Data 5B56AD3Address/Data 3B57GND22GroundB58AD1Address/Data