設(shè)計(jì)導(dǎo)論-第三節(jié)1方法

第三講：IC設(shè)計(jì)流程和設(shè)計(jì)方法第三講：IC設(shè)計(jì)流程和設(shè)計(jì)方法日 CircuitandsystemDesign CircuitandsystemDesign FourPhasesinCreatinga

2005-3-

[AdaptedfromMainSrivastava.CopyrightDesigningaICGoalisReduceIncreaseIncreasechancesofaworking DesigningaICChoicedrivenbyEconomicviabilityaffectedbydesignDesigntimeaffectedbytheefficiencyofarchitecturelogic/memorycircuitlayoutDesigningaICKeyistheuseofconstraints helpautomatetheprocedurebysimplifyingthedifferenttypesofconstraintsandtrade-Performance(speed,area,Sizeofdie(hencecostofdieandTimeofdesign(hencecostofengineering&EasyoftestgenerationandCollapsedetailandarriveatasimplerproblemtodeal CircuitandsystemDesign CircuitandsystemHighlyautomatedtechniquesnowexistfortakingveryhighleveldescriptionsofsystembehaviorandconvertingthedescriptionintoaformthateventuallymaybeusedtospecifyhowachipismanufacturedAdesignisexpressedintermsofthethreedistinct:Specifieswhatasystem SpecifieshowentitiesareconnectedtogethertoperformtheprescribedbehaviorPhysicalSpecifieshowtoactuallybuildastructurethathastherequiredconnectivitytoimplementtheprescribedbehavior Levelsof Eachdesign maybespecifiedatavarietyoflevelsof Moduleorfunctional Levelsof +

G 2005-3- AdaptedfromIrwin&i’sSlidesfromPSU.Copyright2002J.RabaeyetDesignDesignprocesstraversesiterativelybetweenbehavior,structure,andgeometryEDAtoolsprovidingmoreandmore CircuitandsystemDesignCMOSchipdesignDesign BehavioralBehaviorBooleanequations（對低級別的描述TableofinputandoutputAlgorithmswritteninstandardhighlevelcomputerlanguagesC，C++orHDLLanguages Verilog Verilog Verilog 行為描述(算法描述 BehavioralrepresentationHDLforthecarrymodulecarryco,a,b,coutputco;inputa,b,c;

assignco=(a&b)|(a&c|(b&c) CircuitandsystemDesign StructuralLevel ionRTL(registerTransferLevel)門級(Gate開關(guān)級(SwitchLevel)和電路級(Circuit Four-bit Thecascadingof1-bitadderstoform4-bitmoduleinputci;output[3:0]s;outputc4; adda0adda1 ExampleStructuraloutput bsums1bcarryamodule inputoutput wireand andand

22modulecarry(co,a,b,c);inputa,b,c;outputwireil,i2,i3,i4,i5,i6;nmosnl(i3,i4,a);nmosn2(i4,vss,b);nmosn3(i3,i5,b);nmosn4(i5,vss,c);nmosn5(i3,i6,a);nmosn6(i6,vss,c);nmosn7(co,vss,i3);pmospi(il,vdd,a);

pmosp2(i2,il,pmosp3(i3,i2,c);pmosp4(il,vdd,b);pmosp5(i2,il,c);pmosp6(i3,i2,a);pmosp7(co,vdd,i3);end modulecarry(co,a,b,c);inputa,b,c;outputwireil,i2,i3,i4,en;nmosnl(il,vss,a);nmosn2(il,vss,b);nmosn3(cn,il,cn);nmosn4(i2,vss,b);nmosns(cn,i2,a);pmosp2(cn,i3,pmosp3(cn,i4,

pmosp4(i4,vdd,b);pmosp5(i4,vdd,a);pmosp6(co,vdd,cn);pmosn6(co,vss,cn);endmodule CircuitandsystemDesign 定義硅表面的物 moduleinputa[3:0],b[3:0];inputci;outputs[3:0],outpuc4;boundary[0,0,100,400];porta[0]aluminumwidth=lorigin=[0,25];portb[0]aluminumwidth=lorigin=[0,75];portcipolysilicon

origin=[50,ports[0]aluminumwidth=lorigin=[100,50];addaoorigin=[0,0]adda1origin=[0,100]endmodule CMOSIC的設(shè)計(jì)包含了行為、結(jié)構(gòu)和物理面 SimplifiedCircuitandsystemDesign Design DesignDivideamoduleintosubmodulesandthenrepeatingthisoperationonthesubmodulesuntilthecomplexityofthesmallerparts esmanageableMeansthatthehierarchical positionofalargesystemshouldresultinnotonlysimple,butalsosimilarblocks,asmuchaspossible.Meansthatthevariousfunctionalblockswhichmakeupthelargersystemmusthavewell-definedfunctionsandEnsuresthatconnectionsaremostlybetweenneighboringmodules,avoidinglong-distanceconnectionsasmuchas2005-3-

CircuitandsystemDesign Divideamoduleintosubmodulesandthenrepeatingthisoperationonthesubmodulesuntilthecomplexityofthesmallerparts esmanageableHierarchycanbetherein Behavior,structural,Thehierarchyindifferent smaynote.g.astructuralhierarchymaynotmapwellto ExampleofStructuralafour-bitaddercircuit,showingthehierarchydowntogateStructuralinput[3:0]a,b;inputci;output[3:0]s;outputc4;wire[2:0]co;adda0adda1 StructuralRepresentationinputa,b,c;outputsums1moduleinputa,b,c;outputco;wirex,y,z;andandandor6 ExampleofPhysicalafour-bitadderinphysicaldescribestheexternalgeometryoftheadderthelocationsofinputandoutput2005-3- Layoutofa16-bitadder,andthesub-blocksofitsphysicalPhysicallayoutofthetrianglegenerator HierarchybreaksasystemintoButthismaynotsolvethecomplexityTheremaynotbeanyregularityintheWejustendupwithalarge#ofdifferent CircuitandsystemDesign 規(guī)則設(shè)計(jì)RegularityhelpsinmanyCorrectbyReuseofSimplifyverificationof 規(guī)則設(shè)計(jì)（典型、規(guī)則）和版圖形式（等高不等寬、引線腳等 A2-1D-typeedgetriggeredOne-bitfullAlldesignedusinginvertersandtristateiCircuitandsystemDesign 條件選擇：PLA“與陣列”“或陣列”根據(jù)功能要求 ModularityBadUseoftransmissiongatesasInternalsignalsnowdependonsourceDynamicCMOSlogicbutfailtolatchorregistertheBecauseexternalinputsmightarrivedatvarioustimeswithrespecttothetime.Erroneousresultsmightoccurunlessthetimingofeachinputisindividuallychecked ExampleofPoorCircuitandsystemDesign Ensuresthatconnectionsaremostlybetweenneighboringmodules,avoidinglong-distanceconnectionsasmuchaspossibleModulesseeacommonclock,andhencesynchronous-timingmethodsapplyCriticalpaths,ifpossible,shouldbekeptwithinmoduleboundaries.EnsuringtimelocalityisfirsttopayattentiontotheclockgenerationanddistributionnetworkPlacementsothatglobalwiringis 作 Thislectureno