數(shù)字邏輯設(shè)計(jì) - 觸發(fā)器 Flip-Flops

觸發(fā)器

Flip-Flops數(shù)字系統(tǒng)設(shè)計(jì)2Spring

2015

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#7復(fù)習(xí)

時(shí)序電路的基本概念觸發(fā)器本節(jié)內(nèi)容

組合電路和Verilog語(yǔ)言測(cè)試數(shù)字系統(tǒng)設(shè)計(jì)3Spring

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#7測(cè)試（補(bǔ)充）

測(cè)試是一個(gè)專(zhuān)門(mén)用來(lái)給電路的HDL模型施加的一個(gè)激勵(lì)的HDL程序，目的是測(cè)試和觀察其在激勵(lì)下的響應(yīng)。典型的測(cè)試模塊沒(méi)有輸入和輸出，加到設(shè)計(jì)模塊用于模擬的輸入信號(hào)在激勵(lì)模塊中定義為局部reg型數(shù)據(jù)。顯示設(shè)計(jì)模塊的測(cè)試輸出在激勵(lì)模塊中定義為局部wire型數(shù)據(jù)。用局部的標(biāo)識(shí)來(lái)例化測(cè)試的模塊。測(cè)試模塊的HDL格式：

module

test_module_name;

//Declare

local

reg

and

wire

identifiers.

//Instantiate

the

design

module

under

test.

//Specify

a

stopwatch,

using

$finish

to

terminate

the

simulation

//Generate

stimulus,

using

initial

and

always

statements.

//Display

the

output

response

(text

or

graphics

(or

both)).

endmodule數(shù)字系統(tǒng)設(shè)計(jì)4Spring

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#7Sequential

Logic

時(shí)序邏輯

Sequential

Circuits

時(shí)序電路

Simple

circuits

with

feedback

Latches

(level

sensitive)

–

Storage

elements

that

operate

with

signal

levels

(rather

than

signal

transitions)

are

referred

to

as

latches.

Flip-flops

(edge

sensitive)

(abbreviated

FF)

–

A

flip-flop

is

a

binary

storage

device

capable

of

storing

one

bit

of

information.Timing

Methodologies定時(shí)

Cascading級(jí)聯(lián)

flip-flops

for

proper

operation

Clock

skew時(shí)鐘偏移數(shù)字系統(tǒng)設(shè)計(jì)5C3

value

C1comparatorequal

C2multiplexerreset

open/closedSpring

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#7newmuxcontrolclock

equalcomb.

logic

stateSequential

Circuits

Circuits

with

Feedback

Outputs

=

f(inputs,

past

inputs,

past

outputs)

Basis

for

building

"memory"

into

logic

circuits

Door

combination

lock

is

an

example

of

a

sequential

circuit

–

State

is

memory

–

State

is

an

"output"

and

an

"input"

to

combinational

logic

–

Combination

storage

elements

are

also

memory數(shù)字系統(tǒng)設(shè)計(jì)6Spring

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#7X1X2

?

?

?Xnswitching

networkZ1Z2

?

?

?ZnCircuits

with

Feedback

How

to

control

feedback?

What

stops

values

from

cycling

around

endlessly數(shù)字系統(tǒng)設(shè)計(jì)7Spring

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#7"load""data""stored

value"

Simplest

Circuits

with

Feedback

Two

inverters

form

a

static

memory

cell

Will

hold

value

as

long

as

it

has

power

applied

"1"

"stored

value"

"0"

How

to

get

a

new

value

into

the

memory

cell?

Selectively

break

feedback

path

Load

new

value

into

cell

"remember"數(shù)字系統(tǒng)設(shè)計(jì)8Spring

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#7RSQ

Q'RSQS'R'QQ

Q'S'R'

Memory

with

Cross-coupled

Gates

Cross-coupled

NOR

gates

Similar

to

inverter

pair,

with

capability

to

force

output

to

0

(reset=1)

or

1

(set=1)

Cross-coupled

NAND

gates

Similar

to

inverter

pair,

with

capability

to

force

output

to

0

(reset=0)

or

1

(set=0)數(shù)字系統(tǒng)設(shè)計(jì)Setting

the

Latch

(FF)

Pulsing

the

SET

input

to

the

0

state

when

(a)

Q

=

0

prior

to

SET

pulse;(b)

Q

=

1

prior

to

SET

pulse.

Note

that,

in

both

cases,

Q

ends

up

HIGH.9Spring

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#7數(shù)字系統(tǒng)設(shè)計(jì)Resetting

the

Latch

(FF)

Pulsing

the

RESET

input

to

the

LOW

state

when

(a)

Q

=

0

prior

to

RESETpulse;

(b)

Q

=

1

prior

to

RESET

pulse.

In

each

case,

Q

ends

up

low.10Spring

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#711Spring

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#7ResetHoldSetSetResetRace

R

S

Q

\Q數(shù)字系統(tǒng)設(shè)計(jì)100Timing

BehaviorRSQ

Q'數(shù)字系統(tǒng)設(shè)計(jì)12Spring

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#7S00R01Qhold011011unstableState

Behavior

of

R-S

latch

Truth

table

of

R-S

latch

behaviorQ

Q'

0

1Q

Q'

1

0Q

Q'0

0Q

Q'1

1數(shù)字系統(tǒng)設(shè)計(jì)13Spring

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#7Theoretical

R-S

Latch

Behavior

State

Diagram

States:

possible

values

Transitions:

changesbased

on

inputsQ

Q'

0

1Q

Q'

1

0Q

Q'

0

0Q

Q'

1

1SR=00SR=11SR=00SR=10SR=01SR=00SR=10SR=00SR=01SR=11SR=11SR=10SR=01SR=01SR=10SR=11possible

oscillationbetween

states

00

and

11數(shù)字系統(tǒng)設(shè)計(jì)14Observed

R-S

Latch

Behavior

SR=00SR=00Q

Q'

0

1Q

Q'

1

0Very

difficult

to

observe

R-S

latch

in

the

1-1

state

One

of

R

or

S

usually

changes

firstAmbiguously

returns

to

state

0-1

or

1-0

A

so-called

"race

condition"

Or

non-deterministic

transition

SR=10SR=01SR=00SR=10SR=00SR=01SR=01SR=10

SR=11

Q

Q'

0

0SR=11

SR=11

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#700X110X1數(shù)字系統(tǒng)設(shè)計(jì)15Spring

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#7RQQ'Q(t+?)RSQ(t)SSRQ(t)Q(t+?)000001010011110001010011111101XXholdresetsetnot

allowedcharacteristic

equation

Q(t+?)

=

S

+

R’

Q(t)R-S

Latch

Analysis

Break

feedback

pathQ(t)RS16Spring

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#7

QQ'

R'enable'

S'R

SGated

R-S

Latch

Control

when

R

andS

inputs

matter

Otherwise,

the

slightest

glitch

on

R

or

S

while

enable

is

low

could

causechange

in

valuestoredSetReset

S'

R'

enable'

Q

Q'數(shù)字系統(tǒng)設(shè)計(jì)100數(shù)字系統(tǒng)設(shè)計(jì)17

periodSpring

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#7Clocks

Used

to

keep

time

Wait

long

enough

for

inputs

(R'

and

S')

to

settle

Then

allow

to

have

effect

on

value

storedClocks

are

regular

periodic

signals

Period

(time

between

ticks)

Duty-cycle

(time

clock

is

high

between

ticks

-

expressed

as

%

of

period)

duty

cycle

(in

this

case,

50%)Q'數(shù)字系統(tǒng)設(shè)計(jì)18

clockSpring

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#7R'

and

S'Clocks

(cont’d)

Controlling

an

R-S

latch

with

a

clock

Can't

let

R

and

S

change

while

clock

is

active

(allowing

R

and

S

to

pass)

Only

have

half

of

clock

period

for

signal

changes

to

propagate

Signals

must

be

stable

for

the

other

half

of

clock

period

Qstable

c

hanging

stable

c

hanging

stable

R'clock'

S'R

S19Spring

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#7

clock數(shù)字系統(tǒng)設(shè)計(jì)RSQ'

QRSQ'

QRSCascading

Latches

Connect

output

of

one

latch

to

input

of

anotherHow

to

stop

changes

from

racing

through

chain?

Need

to

control

flow

of

data

from

one

latch

to

the

next

Advance

from

one

latch

per

clock

period

Worry

about

logic

between

latches

(arrows)

that

is

too

fast20Spring

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#7Master-Slave

Structure

Break

flow

by

alternating

clocks

(like

an

air-lock)

Use

positive

clock

to

latch

inputs

into

one

R-S

latch

Use

negative

clock

to

change

outputs

with

another

R-S

latchView

pair

as

one

basic

unit

master-slave

flip-flop

twice

as

much

logic

output

changes

a

few

gate

delays

after

the

falling

edge

of

clock

but

does

not

affect

any

cascaded

flip-flopsmaster

stageslave

stageP'P

CLK數(shù)字系統(tǒng)設(shè)計(jì)RSQ'

QRSQ'

QRSRRQ'21Set

1scatch

S

R

CLK

P

P'

Q

Q'數(shù)字系統(tǒng)設(shè)計(jì)Reset

Master

Outputs

Slave

OutputsSpring

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#7The

1s

Catching

Problem

In

first

R-S

stage

of

master-slave

FF

0-1-0

glitch

on

R

or

S