數(shù)字系統(tǒng)設(shè)計(jì) - 可編程邏輯器件

1Winter2009ZDMC–Lec.#09數(shù)字系統(tǒng)設(shè)計(jì)

DigitalSystemDesign------編程器件2Winter2009ZDMC–Lec.#09課程結(jié)構(gòu)

數(shù)字理論知識(shí)(必備)數(shù)字系統(tǒng)和編碼、邏輯代數(shù)、門電路數(shù)字電路分析與設(shè)計(jì)組合邏輯電路觸發(fā)器、半導(dǎo)體存貯器、可編程器件時(shí)序邏輯電路脈沖電路與接口控制器與數(shù)字系統(tǒng)狀態(tài)機(jī)控制器微碼控制器測(cè)試和驗(yàn)證微處理器簡(jiǎn)介3Winter2009ZDMC–Lec.#09存儲(chǔ)器復(fù)習(xí)隨機(jī)存取存儲(chǔ)器（RAM）在計(jì)算機(jī)及數(shù)據(jù)處理系統(tǒng)中需要存放大量數(shù)據(jù)、中間結(jié)果、表格等設(shè)備，這就是隨機(jī)存取存儲(chǔ)器SRAM。RAM可分為單極型和雙極型：雙極型工作速率高，但是集成度不如單極型的高，目前，由于工藝水平的不斷提高，單極型RAM的速率已經(jīng)可以和雙極型RAM相比，而且單極型RAM具有功耗低的優(yōu)點(diǎn)。單極型RAM又可分為靜態(tài)SRAM與動(dòng)態(tài)DRAM：靜態(tài)RAM是用MOS管觸發(fā)器來存儲(chǔ)代碼，所用MOS管較多、集成度低、功耗也較大。動(dòng)態(tài)RAM是用柵極分布電容保存信息，它的存儲(chǔ)單元所需要的MOS管較少，因此集成度高、功耗也小。靜態(tài)RAM使用方便，不需要刷新。4Winter2009ZDMC–Lec.#09SRAM結(jié)構(gòu)一、外部特性二、內(nèi)部組織地址譯碼器分行譯碼器和列譯碼器，只有行及列共同選中的單元才能進(jìn)行讀、寫。這種尋址的方式所需要行線和列線的總數(shù)較少。---例如要存儲(chǔ)256字×1位的容量，采用一元尋址就需要256條字線，若采用二元尋址只需A=16，B=16，共32條線也就可以了。5Winter2009ZDMC–Lec.#09SRAM的存儲(chǔ)單元

RAM中的存儲(chǔ)單元可由雙極型管組成，也可由MOS管組成。6Winter2009ZDMC–Lec.#09動(dòng)態(tài)隨機(jī)存儲(chǔ)器（DRAM）動(dòng)態(tài)存儲(chǔ)單元是利用MOS管柵極電容可以存儲(chǔ)電荷的原理柵極電容保留信息只有一段時(shí)間，需定期地給它刷新，以免信息丟失，所以在每一行上設(shè)有刷新電路。7Winter2009ZDMC–Lec.#09（二）動(dòng)態(tài)MOS存儲(chǔ)單元如下圖這是一動(dòng)態(tài)存儲(chǔ)單元，靠柵極電容C1及C2存儲(chǔ)電荷。如要寫入“1”，只需在數(shù)據(jù)線D上作用“1”便可以給C2充上足夠的電荷，而C1則不被充電，表示記入了“1”當(dāng)刷新端加高電壓時(shí)，負(fù)載管T3、T4導(dǎo)通，同時(shí)行線加高電壓使T6、T5也導(dǎo)通，構(gòu)成R-S觸發(fā)器，觸發(fā)器的狀態(tài)由C1及C2中的電壓決定柵極電容保留信息只有一段時(shí)間，需定期地給它刷新，以免信息丟失，所以在每一行上設(shè)有刷新電路。當(dāng)X、Y線均為高電平時(shí)，T5、T6、T7及T8都導(dǎo)通，此單元接至數(shù)據(jù)線，8Winter2009ZDMC–Lec.#09RAM的擴(kuò)展當(dāng)使用一片RAM器件不能滿足存儲(chǔ)量的需要時(shí)，可以將若干片RAM組合到一起，接成一個(gè)容量更大的RAM。位擴(kuò)展方式將各片的地址線、讀寫線、片選線并聯(lián)即可字?jǐn)U展方式/地址擴(kuò)展方式RAM的片選信號(hào)用譯碼器實(shí)現(xiàn)，每一片RAM的數(shù)據(jù)端I/O1～I(xiàn)/O8都有三態(tài)緩沖器，而它們的片選信號(hào)又不會(huì)同時(shí)出現(xiàn)低電平，可將它們的數(shù)據(jù)端并聯(lián)起來，作為整個(gè)RAM的八位數(shù)據(jù)輸入/輸出端。先進(jìn)行位位擴(kuò)展，再進(jìn)行字?jǐn)U展9Winter2009ZDMC–Lec.#09TypicalSRAMTimingWriteTiming:DReadTiming:WE_LAWriteHoldTimeWriteSetupTimeADOE_L2NwordsxMbitSRAMNMWE_LDataInWriteAddressOE_LHighZReadAddressJunkReadAccessTimeDataOutReadAccessTimeDataOutReadAddressOEdeterminesdirection

Hi=Write,Lo=Read

Writesaredangerous!Becareful!

Doublesignaling:OEHi,WELo10Winter2009ZDMC–Lec.#09存儲(chǔ)器的HDL描述1024個(gè)字的存儲(chǔ)器，每個(gè)字是16位reg[15:0]memword[0:1023];modulememory(Enable,ReadWrite,Address,DataIn,DataOut);inputEnable,ReadWrite;input[3:0]DataIn;input[5:0]Address;output[3:0]DataOut;reg[3:0]DataOut;reg[3:0]Mem[0:63]//64x4memoryalways@(EnableorReadWrite)if(Enable)if(ReadWrite)DataOut=Mem[Address];//ReadelseMem[Address]=DataIn;//WriteelseDataOut=4'bz//Highimpedancestateendmodule11Winter2009ZDMC–Lec.#09第八章可編程邏輯器件

Today,programmablelogicdevices,whichcontainthecircuitrynecessarytocreatelogicfunctions,arebeingusedtoimplementdigitalsystems.

WhyhavePLDstakenoversomuchofthemarket?Withprogrammabledevices,thesamefunctionalitycanbeobtainedwithoneICratherthanusingseveralindividuallogicchips.Thischaracteristicmeanslessboardspace,lesspowerrequired,greaterreliability,lessinventory,andoveralllowercostinmanufacturing.12Winter2009ZDMC–Lec.#09第八章可編程邏輯器件

（PLD,ProgrammableLogicDevice）8.1概述一、PLD的基本特點(diǎn)1.數(shù)字集成電路從功能上有分為通用型、專用型兩大類2.PLD的特點(diǎn)：是一種按通用器件來生產(chǎn)，但邏輯功能是由用戶通過對(duì)器件編程來設(shè)定的數(shù)字系統(tǒng)13Winter2009ZDMC–Lec.#09ProgrammableLogicRegularlogicProgrammableLogicArraysMultiplexers/DecodersROMsFieldProgrammableGateArraysXilinxVertex“RandomLogic”FullCustomDesign“RegularLogic”StructuredDesignDIGITALSYSTEMSFAMILYTREE14Winter2009ZDMC–Lec.#0915Winter2009ZDMC–Lec.#09二、PLD的發(fā)展和分類PROM是最早的PLDPAL可編程邏輯陣列FPLA現(xiàn)場(chǎng)可編程陣列邏輯GAL通用陣列邏輯EPLD可擦除的可編程邏輯器件FPGA現(xiàn)場(chǎng)可編程門陣列ISP-PLD在系統(tǒng)可編程的PLD16Winter2009ZDMC–Lec.#09三、LSI中用的邏輯圖符號(hào)17Winter2009ZDMC–Lec.#098.2現(xiàn)場(chǎng)可編程邏輯陣列FPLA

FieldProgrammableLogicArray組合電路和時(shí)序電路結(jié)構(gòu)的通用形式1970s

邏輯函數(shù)

與或表達(dá)式

與邏輯+或邏輯

最小項(xiàng)之和

部分最小項(xiàng)與EPROM很相似時(shí)序型FPLAA0~An-1W0W(2n-1)D0DmAlthoughtheFPLAismoreflexiblethanthePALarchitecture,ithasnotbeenaswidelyacceptedbyengineers.FPLAsareusedmostlyinstate-machinedesignwherealargenumberofproducttermsareneededineachSOPexpression.18Winter2009ZDMC–Lec.#098.2FPLA結(jié)構(gòu)組合電路和時(shí)序電路結(jié)構(gòu)的通用形式19Winter2009ZDMC–Lec.#098.3PAL（ProgrammableArrayLogic）8.3.1PAL的基本電路結(jié)構(gòu)，1970s，曾大規(guī)模應(yīng)用，采用雙極型熔絲工藝，工作速度較高。一、基本結(jié)構(gòu)形式

可編程“與”陣列+固定“或”陣列+輸出電路 最簡(jiǎn)單的形式為：二、編程單元出廠時(shí)，所有的交叉點(diǎn)均有熔絲三、輸出有限、減少單元數(shù)20Winter2009ZDMC–Lec.#098.3.2PAL的輸出電路結(jié)構(gòu)和反饋形式PAL器件的輸入、輸出結(jié)構(gòu)以及輸入、輸出的數(shù)目是由集成電路制造商根據(jù)實(shí)際設(shè)計(jì)情況大致估計(jì)確定。一.專用輸出結(jié)構(gòu)用途：產(chǎn)生組合邏輯電路21Winter2009ZDMC–Lec.#09二.可編程輸入/輸出結(jié)構(gòu)用途：組合邏輯電路，有三態(tài)控制可實(shí)現(xiàn)總線連接可將輸出作輸入用當(dāng)最上面的乘積項(xiàng)為高電平時(shí)，三態(tài)門開通，I/O可作為輸出或反饋；乘積項(xiàng)為低電平時(shí)，三態(tài)門關(guān)斷，是輸入。22Winter2009ZDMC–Lec.#09三.寄存器輸出結(jié)構(gòu)、時(shí)序結(jié)構(gòu)用途：產(chǎn)生時(shí)序邏輯電路或門的輸出通過D觸發(fā)器，在CP的上升沿時(shí)到達(dá)輸出。觸發(fā)器的Q端可以通過三態(tài)緩沖器送到輸出引腳觸發(fā)器的反相端反饋回與陣列，作為輸入信號(hào)參與更復(fù)雜的時(shí)序邏輯運(yùn)算23Winter2009ZDMC–Lec.#09四.帶異或輸出結(jié)構(gòu)時(shí)序邏輯電路還可便于對(duì)“與-或”輸出求反兩個(gè)和項(xiàng)在觸發(fā)器的輸入端異或之后，在時(shí)鐘上升沿到來時(shí)存入觸發(fā)器內(nèi)把乘積項(xiàng)分割成兩個(gè)和項(xiàng)24Winter2009ZDMC–Lec.#09五.運(yùn)算反饋結(jié)構(gòu)時(shí)序邏輯電路可產(chǎn)生A、B的十六種算術(shù)、邏輯運(yùn)算由8個(gè)寄存器型輸出結(jié)構(gòu)組成的PAL器件命名為PAL16R8，由8個(gè)可編程I/O結(jié)構(gòu)組成的PAL器件則命名為PAL16L8。25Winter2009ZDMC–Lec.#09O3=AB+CD+0+026Winter2009ZDMC–Lec.#09ROMvs.PLAROMDesigntimeisshort(noneedtominimizeoutputfunctions)Mostinputcombinationsareneeded(e.g.,codeconverters)LittlesharingofproducttermsamongoutputfunctionsSizedoublesforeachadditionalinputCan'texploitdon'tcaresCheap(high-volumecomponent)CanimplementanyfunctionofninputsMediumspeedPLADesigntoolsareavailableformulti-outputminimizationTherearerelativelyfewuniquemintermcombinationsManymintermsaresharedamongtheoutputfunctionsMostcomplexindesign,needmoresophisticatedtoolsCanimplementanyfunctionuptoaproducttermlimitSlow(twoprogrammableplanes)27Winter2009ZDMC–Lec.#098.3.3PAL的應(yīng)用舉例邏輯函數(shù)EDA軟件設(shè)計(jì)自學(xué)：P397例8.3.1P399例8.3.228Winter2009ZDMC–Lec.#098.4通用邏輯陣列GAL8.4.1電路結(jié)構(gòu)形式1985采用E2CMOS工藝和靈活的輸出結(jié)構(gòu)，有電擦寫反復(fù)編程的特性。可編程“與”陣列+固定“或”陣列+可編程輸出電路

OLMC編程單元采用E2CMOS可改寫統(tǒng)一型號(hào)輸出邏輯宏單元OLMC（OutputLogicMacroCell）適當(dāng)?shù)貫镺LMC進(jìn)行編程，GAL就可以在功能上代替前面討論過的PAL各種輸出類型以及其派生類型29Winter2009ZDMC–Lec.#09GAL16V8由OLMC編程決定inputorOE由OLMC編程決定inputorouput由OLMC編程決定inputorCLKGAL16V8：16表示陣列的輸入端數(shù)量，8表示輸出端數(shù)量，V則表示輸出形式可以改變的普通型30Winter2009ZDMC–Lec.#09GAL器件結(jié)構(gòu)和特點(diǎn)GAL16V8的基本結(jié)構(gòu)8個(gè)輸入緩沖器8個(gè)輸出反饋緩沖器一個(gè)共用時(shí)鐘CLK8個(gè)輸出緩沖器8個(gè)OLMC31Winter2009ZDMC–Lec.#098.4.2OLMC輸出邏輯宏單元數(shù)據(jù)選擇器工作模式：由結(jié)構(gòu)控制字決定AC0,AC1(n),XOR(n)編程信息：存于狀態(tài)控制字中。32Winter2009ZDMC–Lec.#09狀態(tài)控制字：存放編程信息編程方法：通過對(duì)狀態(tài)控制字編程，便可決定OLMC的工作模式

。SYN（8個(gè)OLMC各共用）：決定CP接入方法：

SYN=0，CP同步接入。

SYN=1，CP作I/O端口33Winter2009ZDMC–Lec.#09輸出邏輯宏單元OLMC組態(tài)

輸出邏輯宏單元由對(duì)AC1(n)和AC0進(jìn)行編程決定PTMUX、TSMUX、OMUX和FMUX的輸出，共有5種基本組態(tài)：

專用輸入組態(tài)、專用輸出組態(tài)、復(fù)合輸入/輸出組態(tài)、寄存器組態(tài)和寄存器組合I/O組態(tài)。8個(gè)宏單元可以處于相同的組態(tài)，或者有選擇地處于不同組態(tài)。(1)專用輸入組態(tài)：如下圖所示：此時(shí)AC1(n)＝1，AC0＝0，使TSMUX輸出為0，三態(tài)輸出緩沖器的輸出呈現(xiàn)高電阻，本單元輸出功能被禁止，I/O可以作為輸入端，提供給相鄰的邏輯宏單元。本級(jí)輸入信號(hào)卻來自另一相鄰宏單元。34Winter2009ZDMC–Lec.#09(2)專用輸出組態(tài)：如下圖所示：AC1(n)＝0，AC0＝0，四路反饋數(shù)據(jù)選擇器FMUX輸出接在低電平，本單元的反饋信號(hào)和相鄰單元的信號(hào)都被阻斷由于或非門，使異或門的輸出不經(jīng)過D觸發(fā)器，直接由處于使能狀態(tài)的三態(tài)門輸出由于與非門輸出使第一條乘積項(xiàng)經(jīng)過乘積項(xiàng)數(shù)據(jù)選擇器作為或門的輸入35Winter2009ZDMC–Lec.#098.4.3GAL的輸入和輸出特性GAL是一種較為理想的高輸入阻抗器件CMOS輸入不可懸空Actually,theGAL16V8hasonlythreedifferentmodes:(1)simplemode,whichisusedtoimplementsimpleSOPcombinationallogicwithouttristateoutputs;(2)complexmode,whichimplementsSOPcombinationallogicwithtristateoutputsthatareenabledbyanANDproductexpression;(3)registeredmode,whichallowsindividualOLMCstooperateinacombinationalconfigurationwithtristateoutputs(similartothecomplexmode)orinasynchronousmodewithclockedDFFssynchronizedtoacommonclocksignal.36Winter2009ZDMC–Lec.#09GAL輸出緩沖級(jí)三態(tài)N-MOS高速大電流37Winter2009ZDMC–Lec.#098.5可擦除的可編程邏輯陣列EPLD一、結(jié)構(gòu)特點(diǎn)相當(dāng)于“與-或”陣列（PAL）+OLMC二、采用EPROM工藝集成度提高高密度復(fù)雜的可編程邏輯陣列CPLD38Winter2009ZDMC–Lec.#098.7現(xiàn)場(chǎng)可編程門陣列FPGA一、基本結(jié)構(gòu)1.IOB輸入輸出2.CLB邏輯3.互連資源IR4.SRAM編程數(shù)據(jù)SimplifiedversionofFPGAinternalarchitectureBasicidea:two-dimensionalarrayoflogicblocksandflip-flopswithameansfortheusertoconfigure:

1.theinterconnectionbetweenthelogicblocks, 2.thefunctionofeachblock.39Winter2009ZDMC–Lec.#09WhyFPGAs?Bytheearly1980’smostofthelogiccircuitsintypicalsystemswhereabsorbedbyahandfulofstandardlargescaleintegratedcircuits(LSI).Microprocessors,bus/IOcontrollers,systemtimers,...Everysystemstillhadtheneedforrandom“gluelogic”tohelpconnectthelargeICs:generatingglobalcontrolsignals(forresetsetc.)dataformatting(serialtoparallel,multiplexing,etc.)SystemshadafewLSIcomponentsandlotsofsmalllowdensitySSI(smallscaleIC)andMSI(mediumscaleIC)components.40Winter2009ZDMC–Lec.#09WhyFPGAs?CustomICssometimesdesignedtoreplacethelargeamountofgluelogic:reducedsystemcomplexityandmanufacturingcost,improvedperformance.However,customICsareveryexpensivetodevelop,anddelayintroductionofproducttomarket(timetomarket)becauseofincreaseddesigntime.Note:needtoworryabouttwokindsofcosts:1.costofdevelopment,sometimescallednon-recurringengineering(NRE)2.costofmanufactureAtradeoffusuallyexistsbetweenNREcostandmanufacturingcosts41Winter2009ZDMC–Lec.#09WhyFPGAs?CustomICapproachviableforproductsthatare…veryhighvolume(whereNREcouldbeamortized),nottime-to-marketsensitive.FPGAsintroducedasanalternativetocustomICsforimplementinggluelogic:improveddensityrelativetodiscreteSSI/MSIcomponents(withinaround10xofcustomICs)withtheaidofcomputeraideddesign(CAD)toolscircuitscouldbeimplementedinashortamountoftime(nophysicallayoutprocess,nomaskmaking,noICmanufacturing),relativetoASICs.lowersNREsshortensTTMBecauseofMoore’slawthedensity(gates/area)ofFPGAscontinuedtogrowthroughthe80’sand90’stothepointwheremajordataprocessingfunctionscanbeimplementedonasingleFPGA.42Winter2009ZDMC–Lec.#09PLAs:100sofgateequivalentsFPGAs:1000-10000sgates

upto10,000,000gatesLogicblocksImplementcombinational

andsequentiallogicInterconnectWirestoconnectinputsand

outputstologicblocksI/OblocksSpeciallogicblocksat

peripheryofdevicefor

externalconnectionsKeyquestions:Howtomakelogicblocksprogrammable?Howtoconnectthewires?Afterthechiphasbeenfabbed

Field-ProgrammableGateArrays43Winter2009ZDMC–Lec.#091.IOB可以設(shè)置為輸入/輸出；輸入時(shí)可設(shè)置為：同步（經(jīng)觸發(fā)器） 異步（不經(jīng)觸發(fā)器）44Winter2009ZDMC–Lec.#092.CLB本身包含了組合電路和觸發(fā)器，可構(gòu)成小的時(shí)序電路將許多CLB組合起來，可形成大系統(tǒng)----陣列45Winter2009ZDMC–Lec.#09TheXilinx4000CLB46Winter2009ZDMC–Lec.#093.互連資源47Winter2009ZDMC–Lec.#09Xilinx4000Interconnect48Winter2009ZDMC–Lec.#09XilinxFPGAs(interconnectdetail)49Winter2009ZDMC–Lec.#094.SRAM

分布式

每一位觸發(fā)器控制一個(gè)編程點(diǎn)

50Winter2009ZDMC–Lec.#09DetailsofVirtex-ESliceLUT4-inputfun16x1sram32x1or16x2inslice16bitshiftregisterStorageelementDflipfliplatchCombinationaloutputs5and6inputfunctionsCarrychainarithmeticalongroworcol51Winter2009ZDMC–Lec.#09二、編程數(shù)據(jù)的裝載數(shù)據(jù)可先放在EPROM或PC機(jī)中通電后，自行啟動(dòng)FPGA內(nèi)部的一個(gè)時(shí)序控制邏輯電路，將在EPROM中存放的數(shù)據(jù)讀入FPGA的SRAM中“裝載”結(jié)束后，進(jìn)入編程設(shè)定的工作狀態(tài)?。∶看瓮ｋ姾?，SRAM中數(shù)據(jù)消失下次工作仍需重新裝載52Winter2009ZDMC–Lec.#09XilinxFPGAAdderExampleExample2-bitbinaryadder-inputs:A1,A0,B1,B0,CIN

outputs:S0,S1,CoutFullAdder,4CLBdelaystofinalcarryout2xTwo-bitAdders(3CLBseach)yields2CLBstofinalcarryoutFPGAarchitecture53Winter2009ZDMC–Lec.#0954Winter2009ZDMC–Lec.#09Virtex-EFamilyofParts55Winter2009ZDMC–Lec.#09WhyareFPGAsInteresting?Technicalviewpoint:Forhardware/system-designers,likeASICsonlybetter!“Tape-out”newdesigneveryfewminutes/hours.Doesthe“reconfigurability”or“reprogrammability”offerotheradvantagesoverfixedlogic?Dynamicreconfiguration?In-fieldreprogramming?Selfmodifyinghardware,evolvablehardware?FPGAshavetrackedMoore’sLawbetterthananyotherprogrammabledevice.Staggeringlogiccapacitygrowth(10000x):56Winter2009ZDMC–Lec.#09WhyareFPGAsInteresting?Logiccapacitynowonlypartofthestory:on-chipRAM,high-speedI/Os,“hard”functionblocks,...ModernFPGAsare“reconfigurablesystems”Havebeenanarchetypeforthesemiconductorindustryasawhole:But,theheterogeneityerodesthe“purity”argument.Mappingismoredifficult.Introducesuncertaintyinefficiencyofsolution.57Winter2009ZDMC–Lec.#09WhyareFPGAsInteresting?Haveattractedanhugeamountofinvestmentfornewventures:Moststartupshavefailed.Why?BusinessdominatedbyXilinxandAlteraFPGAsattheleadingedgeofICprocessing:XilinxV7outnextyearwith28nmTSMCprocessingFoundarieslikeFPGAs-regularityhelpgetprocessupthe“l(fā)earningcurve”High-volumecommitmentgetsinterestoffoundry(GivesFPGAsacompetitiveedgeoverASICs,whichusuallyarebuiltonanolderprocess.)FPGAshavebeenwildlysuccessfuleventhoughtheyareinefficientinsiliconarea,