Vivado從此開始（第2版）課件 11-Some-Tips-About-Design-Flow - - 15-Setting-Output-Delay

Lauren

GaoSomeTipsAboutVivadoDesign

FlowTipsofuserdesignsourcefiles

managementTipsofIPmanagementTipshardware

managementAgendaDesignFilesArchitecturein

VivadoFilesetssources_1constrs_1sim_1UserRTLsourcefiles:.v.vhd

.svSystemGeneratormodels:.mdl.slxIPcorefiles:.xci.dcpIPintegratorblockdiagramfiles:.bdTimingconstraintsfiles:.xdcPhysicconstraintsfiles:

.xdcUsertestbenchfiles:.v.vhd.svIPsimulationfiles:.v

.vhdAdddesignfilestotheprojecteasilyand

quicklyAddthesourcestotheprojectasreferencedsourcesinstead

ofimportingthemintothe

projectUserDesignSourceFiles

ManagementsrcsimPutdifferenttypeoffilesintodifferent

foldersRTLTestbenchWhyxdcConstraintsAddUserDesignFilestoProject

Efficientlyadd_files-scan_for_includes

F:/Vivado/ug937/sourcesadd_files-scan_for_includes

F:/Vivado/ug937/sourcesimport_filesF:/Vivado/ug937/sourcesadd_files-norecurse

F:/Vivado/ug937/sourcesIP

ManagementItmakesrevisioncontrolmore

straightforwardItallowsforeaseofsharingcustomizedIPwith

othersCheckIP

statusUpgrade?IPversionhas

changedIs

locked?Designparthas

changedGetPART&TARGET_LANGUAGEofcurrent

projectChangePART&TARGET_LANGUAGEofcurrent

projectManageIPin

managed_ip_projectreport_ip_status–nameip_status_1upgrade_ip[get_ips

sine_high]get_propertyPART[current_project]get_propertyTARGET_LANGUAGE

[current_project]set_propertyPARTxc7k325tffg900-2

[current_project]set_propertyTARGET_LANGUAGEVHDL

[current_project]IfPARTIs

Changed…AfterPART

changedReset

all

IPs

→

Upgrade

all

IPs

→

Regenerate

all

IpsOnebyone?fartooinefficient

!DoitwithTclscript

automatically!TclResetandRegenerateallIpswith

TclWhat’sthefunctionofupgrade_ip

here?ManageIPproject

structureEachIPhasitsowndirectoryWhichtypeofIPgeneratedfilescanbeaddedtothe

projectxci(XilinxCore

Instance)dcp(Design

Checkpoint)Howtoaddxciordcpfilestocurrentproject

efficientlyFindxcioneby

one?TclWhat’sthedifferencebetweenaddingxciandaddingdcpto

currentprojectAddthesourcestotheprojectasreferencedsourcesinsteadofimportingthemintothe

projectAddIPstothe

ProjectDesign

FilesUserdesignsourcefiles:Verilog,VHDL,SystemVerilog,

XDCIPfiles:xci,

dcpProject

propertiesProject

ManagementPART&

TARGET_LANGUAGEChangeProject

Propertiesset_propertyPARTxc7k325tffg900-2

[current_project]set_propertyTARGET_LANGUAGEVHDL

[current_project]SOURCE_MGMT_MODEset_propertysource_mgmt_modeAll[current_project]set_propertysource_mgmt_modeDisplayOnly[current_project]set_propertysource_mgmt_modeNone

[current_project]get_files[-regexp][-nocase][-filterarg][-of_objects

args][-compile_orderarg][-used_inarg][-all][-quiet][-verbose]

[patterns]-of_objectsAsingle

filesetAsub-design:IPcore,BlockdesignorDSP

design-compile_ordersources|constraints-used_insynthesis,simulation,

implementationThisoptionmustbeusedwiththe-compile_order

optionPopularTclCommand:

get_filesGetallconstraintfilesofanIP

core?Examplesof

get_filesGetallRTLfilesinsources_1

filesetsetrtl_files[get_files

-of_objectsllength$rtl_files[get_filesetssources_1]]GetallVHDLfilesinsources_1

filesetsetvhd_files[get_files

-of_objects-filter{NAME=~

*.vhd}]llength

$vhd_files[get_filesetssources_1]\GetallsimulationfilesofanIP

coresetsim_files[get_files-of_objects[get_ips

sine_high]\-compile_ordersources-used_in

simulation]llength

$sim_filesreport_compile_order[-of_objectsargs][-fileset

arg][-missing_instances][-constraints][-sources][-used_inarg][-filearg][-append][-quiet]

[-verbose]Example

:CheckconstraintscompileorderChecksimulationcompile

orderChecksynthesiscompile

order?CheckCompile

Orderreport_compile_order

-constraintsreport_compile_order-used_in

simulationThreeTypesofDesigninVivado(Project

Mode)ElaboratedDesignSynthesized

DesignImplemented

Designsynth_design-rtl-name

rtl_1open_runsynth_1-namenetlist_1open_runimpl_1HardwareManager:.bit&

.ltxTwofilesare

necessary.bitdebug_nets.ltx:probesinformation

files.ltxcanbegeneratedbywrite_debug_probesTcl

commandset_propertyPROGRAM.FILE{C:/design.bit}[lindex[get_hw_devices]0]set_propertyPROBES.FILE{C:/design.ltx}[lindex[get_hw_devices]

0]SavingCapturedILADatatoa

FileRestoringCapturedILADatafroma

FileSaveandRestoreILA

Datawrite_hw_ila_datamy_hw_ila_data_file.zip[upload_hw_ila_data

hw_ila_1]display_hw_ila_data[read_hw_ila_data

my_hw_ila_data_file.zip]Lauren

GaoBasicConceptandTerminologyofTiming

AnalysisLaunchedgevs.Capture

edgeTiming

pathDataarrivaltimevs.Datarequired

timeSetupslackvs.Hold

slackAgendaLaunchvs.Capture

EdgesD QTsuThTCOD QTsuThTCOBUFGclkDataPath

DelayregaregbLaunch

EdgeCapture

EdgeData

ValidLaunchEdge:theedgewhich“l(fā)aunches”thedatafromsourceregisterCaptureEdge:theedgewhich“captures”thedataatdestinationregister(withrespecttothelaunchedge,selectedbytiminganalyzer;typically1

cycle)NextLaunch

EdgeFourTypesofTiming

PathD QD QTsuThTCOD QTsuThTCOBoard

ClockBoard

ClockBoardBoardDevice

BD QdinaclkdinbdincdoutadoutbdoutcBUFGInputDelayDataPath

DelayInternal

DelayDataPath

DelayOutputDelayDevice

A Internal

Delay regaregbInputPorttoInternalSequentialCell

PathInternalPathfromSequentialCelltoSequential

CellInternalSequentialCelltoOutputPort

PathInputPorttoOutputPort

PathFPGA

DeviceSSSSEEEEDeviceA/clkrega/clkregb/clkinputrega/Dregb/DDeviceB/DoutputStart

pointEnd

pointTimingPath

SectionsD QTsuThTCOD QTsuThTCODataPath

DelayregaregbBUFGclkaclkbSourceClock

PathData

PathDestinationClock

PathClkinput

portClkpinoflaunch

regClkinput

portClkpinoflaunch

regDatainputpinofcapture

regClkpinofcapture

regPathStart

PointEnd

PointDataArrival

TimeclkBUFGTdataregaregbTclkaData

ValidLaunch

EdgeD QD QTCOData

Validclkrega/clkrega/Qregb/DTclkaTcoTdataDataArrivalTime=LaunchEdge+Tclka+Tco+

TdataThedataarrivaltimeforsetupanalysisisthetimeittakesfor

thedatatobestableatthepathendpointafterbeinglaunchedbythesource

clockClockArrival

TimeclkBUFGregaD QD QregbTclkbclkregb/clkTclkbCapture

EdgeClockArrivalTime=CaptureEdge+

TclkbThetimeforclocktoarrivedestinationregister’sclockinput

pinDataRequiredTime–Set

upclkBUFGregaD QregbTheminimumtimerequiredforthedatatogetcapturedby

thedestination

registerTclkbD QTsuclkregb/clkTclkbCapture

EdgeTsuDatamustbevalid

hereData

ValidDataRequiredTime=ClockArrivalTime–Tsu–Setup

UncertaintyDataRequiredTime–

HoldclkBUFGregaD QD QregbTheminimumtimerequiredforthedatatoremainstableaftercapturedbythedestination

registerTclkbThclkregb/clkTclkbCapture

EdgeThDatamustremainvaliduntil

hereData

ValidDataRequiredTime=ClockArrivalTime+Th+Hold

UncertaintySetup

SlackclkBUFGregaregbTclkbD QTsuTclkaD QTCOTdataData

ValidData

Validclkrega/clkrega/Qregb/DTclkaTcoTdataregb/clkTclkbTsuSetup

SlackThemarginbywhichthesetuptimingrequirementismet.Itensureslauncheddataarrivesintimetomeetthecapturing

requirementLaunch

EdgeCapture

EdgeHold

SlackThemarginbywhichtheholdtimingrequirementismet.Itensurescapturedataisnotcorruptedbydatafromanotherlaunchedge.Italsoprevents

"double-clocking"clkBUFGregaregbD QTclkbTclkaD QTCOTdataclkrega/clkTclkaTcoCurrentData

Validrega/QTcoCurrentData

Validregb/Dregb/clkTclkbTdataThThNextData

ValidTdataNextData

ValidHold

SlackCapture

EdgeNextLaunch

EdgeTclkaSetup&Hold

SlackThemarginbywhichtheholdtimingrequirementismet.Itensurescapturedataisnotcorruptedbydatafromanotherlaunchedge.Italsoprevents

"double-clocking"clkBUFGregaregbD QTclkbTclkaD QTCOTdataclkrega/clkTclkaTcoCurrentData

Validrega/QTcoCurrentData

Validregb/clkNextData

ValidTdataNextData

ValidTdataThThHold

SlackCapture

EdgeNextLaunch

EdgeTclkaTsuTclkbSetup

SlackDataRequired

Time(H)regb/DData

RequiredTime(Su)Slack

EquationsDataRequiredTime(Setup)=ClockArrivalTime–Tsu–Setup

UncertaintyDataRequiredTime(Hold)=ClockArrivalTime+Th+Hold

UncertaintySetupSlack=DataRequiredTime(Setup)–DataArrivalTime

(Setup)HoldSlack=DataArrivalTime(Hold)–DataRequiredTime

(Hold)Positiveslack:TimingrequirementmetNegativeslack:Timingrequirementnot

metEquationsworkforalltimingpath:Interal,I/O&asynchronous

controlWhyIsSlack

Negative?SetupSlack=DataRequiredTime(Setup)–DataArrivalTime

(Setup)HoldSlack=DataArrivalTime(Hold)–DataRequiredTime

(Hold)clkrega/clkTclkaTcoCurrentData

Validrega/QTcoCurrentData

Validregb/clkNextData

ValidTdataNextData

ValidTdataThHold

SlackTclkaTsuTclkbSetup

SlackDataRequired

Time(H)regb/DData

RequiredTime(Su)SystemFrequencyTdata

Tlog

ic

TnetTs

T

TLaunchedgetimeisusedasreferencepointduringtiming

analysisNormally,captureedgetime=launchedgetime+1clockcycleTsuandTharedependentonthedevicewhichcannotbe

changedSummaryLauren

GaoCreateBasicClockPeriod

ConstraintOrganizingYour

ConstraintsXilinxrecommendsthatyouseparatetimingconstraintsand

physicalconstraintsbysavingthemintotwodistinct

filesConstrs_1Timingconstraints:.xdcPhysicconstraints:

.xdcsetmyxdc[get_files-of_objects

\[get_filesets

constrs_1]]set_propertyUSED_IN{synthesisimplementation}\[lindex$myxdc0]set_propertyUSED_IN{synthesis}[lindex$myxdc

0]Clock

Description0 258 1015

16ns50%50%25%75%clk0clk1Clock

periodDuty

cyclePhaseclk0:period=10,waveform={0

5}Clk1:period=8,waveform={2

8}Primary

ClockD QTsuThTCOD QTsuThTCOsysclkIBUFDataPath

DelayregaregbBUFGRecommendedprimary

clocksource

pointcreate_clock-period10[get_ports

sysclk]Aprimaryclockisaboardclockthatentersthedesign

through:Aninput

portAgigabittransceiveroutputpin(forexample,arecovered

clock)Primaryclocksmustbedefinedfirst,sinceothertiming

constraintsoftenreferto

them50%50%sysclk0 510Primary

Clock50%50%rxclk01.663.33create_clock-namerxclk-period3.33[get_pins

gt0/RXOUTCLK]Generated

ClockUserDefinedGenerated

ClocksDefinedbythecreate_generated_clock

commandAttachedtoanetlistobject,preferablytheclocktreeroot

pinAutomaticallyDerived

Clocksalsocalledauto-generated

clocksTheirconstraintisautomaticallycreatedbytheVivadoIDEontheoutputpinsoftheClockModifyingBlocks

(CMB)TheCMBsareMMCMx,PLLxorBUFR

primitivescreate_generated_clock[-namearg][-sourceargs][-edges

args][-divide_byarg][-multiply_byarg][-combinational][-duty_cycle

arg][-edge_shiftargs][-add][-master_clockarg][-quiet][-verbose]

objectsThe-sourceoptionacceptsonlyapinorportnetlistobject.Itdoesnotacceptclock

objectsUserDefinedGenerated

ClocksD QTsuThTCOD QTsuThTCOIBUFregaregbBUFGData

PathPrimaryclocksource

pointGeneratedclockdefinition

pointclkincreate_clock-nameclkin-period10[get_ports

clkin]#Option1:masterclocksourceistheprimaryclocksourcepointcreate_generated_clock-nameclkdiv2-source[get_portsclkin]-divide_by2\[get_pinsREGA/Q]#Option2:masterclocksourceistheREGAclock

pincreate_generated_clock-nameclkdiv2-source[get_pinsREGA/C]-divide_by2\[get_pinsREGA/Q]UserDefinedGenerated

ClocksD QTsuThTCOD QTsuThTCOclkinIBUFregaregbBUFGData

PathPrimaryclocksource

pointGeneratedclockdefinition

point123456Edge

numclkinclkdiv2#waveformspecifiedwith-edgesinsteadof-divide_bycreate_generated_clock-nameclkdiv2-source[get_pinsREGA/C]

\-edges{135}[get_pins

REGA/Q]AutomaticallyDerived

ClockD QTsuThTCOregbData

PathclkinIBUFBUFGCLKFBOUTCLKFBINCLKINCLKOUTMMCMBUFGBUFGclkipclkip/mmcm0Hierarchynet

nameclkip/cpuclkPrimaryclock

source

point Generatedclockdefinition

pointWhat’sthegeneratedclockname

here?cpuclkHowtomakeyourconstraintindependentoftheclockname

changes?get_clocks–of_objects[get_pinsclkip/mmcm0/CLKOUT]get_clocks–of_objects[get_nets

clkip/cpuclk]RenameTool-Generated

Clockscreate_generated_clock-nameclk_rx

\[get_pinsclk_gen_i0/clk_core_i0/inst/mmcm_adv_inst/CLKOUT0]create_generated_clock-nameclk_tx

\[get_pinsclk_gen_i0/clk_core_i0/inst/mmcm_adv_inst/CLKOUT1]create_generated_clock-nameclkfbout

\[get_pins

clk_gen_i0/clk_core_i0/inst/mmcm_adv_inst/CLKFBOUT]Clock

Groupclkaandclk0are

synchronous.Allthegeneratedclocksare

synchronousOSC1clk0clkaclkbclkcclkdOSC2clk1clkeclkfclkgclkhAsynchronousSynchronousSynchronousTheVivadoIDEassumesthatallclocksarerelatedby

default?Clock

Categories?Synchronous

Clocks?Asynchronous

Clocks?Unexpandable

ClocksMMCMMMCMUnexpandable

Clocksclk0launchedge(source

clock)clk1captureedge(destination

clock)0 2 4 6 8 10 12 nsCommon

periodSetup

(1)Setup

(2)Therearetwouniquesourceanddestinationclockedgesthatqualifyforsetupanalysis:setup(1)and

setup(2)Twoclocksarenotexpandablewhenthetimingengine

cannotdeterminetheircommonperiodover1000

cyclesExample:clk0hasa5.125ns

periodPathrequirementbetween

twoclk1hasa6.666nsperiodclocksarenotreasonable

(0.01ns)AsynchronousClock

GroupsMMCMOSC1clk0clkaclkbclkcclkdMMCMOSC2clk1clkeclkfclkgclkhAsynchronousset_clock_groups–nameasync_clk0_clk1–asynchronous

\–group[get_clocks–include_generated_clocksclk0]

\–group[get_clocks–include_generated_clocks

clk1]TheVivadoIDEassumesthatallclocksarerelatedby

defaultTheset_clock_groupscommanddisablestiminganalysisbetween

groupsofclocksthatyou

identifyCaution:Disablingtiminganalysisbetweentwoclocksdoesnotmeanthatthepathsbetweenthemwillworkproperlyin

hardwareWiththeVivadoIDE,severaltimingclockscanexistonaclocktreeatthesametime,whichisconvenientforreportingonalltheoperationmodesatonce,butisnotpossiblein

hardware.ExclusiveClock

GroupsMMCMOSC1BUFGMUXclk0clk1exclusive

clocksset_clock_groups–nameexclusive_clk0_clk1–physically_exclusive

\–groupclk0–groupclk1Allclocksarerelatedby

defaultOppositeofUCF

defaultsClockperiodisexpandabletofindacommon

multipleAsynchronousclockdomainsremove

analysisXDCcommand:

set_clock_groupBecareful!Thesepathsarevalid–need

synchronizationUnexpandable

clocksTimingtoolcouldnotfindcommonperiodwhenexpandingtwo

clocks.Needtobefixedbyuser(changefrequencyor

false-path)Reportedin

check_timingClock

RelationshipsMigratefromUCFto

XDCPeriodconstraintin

UCFNET"clk_ref_p"TNM_NET=

TNM_clk_ref;TIMESPEC"TS_clk_ref"=PERIOD"TNM_clk_ref"5ns

;Periodconstraintin

XDCcreate_clock-nameclk_ref_p-period5[get_ports

clk_ref_p]Lauren

GaoSettingInputDelay?Copyright2012XilinxXilinxDesignConstraints-2DifferentPathsUsingDifferent

ConstraintsD QTsuThTCOD QTsuThTCOBoard

ClockBoard

ClockBoardDevice

AD QBoardDevice

BD QdinaclkdinbdincdoutadoutbdoutcBUFGInternal

DelayDataPath

DelayInternal

DelayDataPath

Delayregaregbset_max_delayset_input_delayset_output_delaycreate_clock?Copyright2012XilinxXilinxDesignConstraints-3Input

DelayclkD QTsuThTCOTsuThTCOUpstream

DeviceD QFPGAdinclkinTrace

DelayInputDelaymax=Tcomax+TDmaxInputDelaymin=

Tcomin+TDminReferencePoint(OppositeofOffset

In)create_clock–namesysclk–period10[get_ports

clkin]set_input_delay–clocksysclk4[get_ports

din]UCFXDCUpstream/clkInput

Delay OffsetInNETdinOFFSET=IN6nsBEFORE

clkin04ns5Current

Data6ns10Valid?Copyright2012XilinxXilinxDesignConstraints-4CompleteInputStaticTiming

PathclkTsuThTCOUpstream

DeviceD QsysclkSource

ClockDelayDestinationClock

DelayDataPath

DelayTrace

Delaycreate_clock–namesysclk–period

10[get_portsclkin]set_input_delay-clocksysclk-max

4[get_portsain]set_input_delay-clocksysclk-min

2[get_portsain]?Copyright2012XilinxXilinxDesignConstraints-5InputSetupTimingReport

Summary?Copyright2012XilinxXilinxDesignConstraints-6InputSetupTimingReportDetailed

PathsSourceClock

DelayDataPathDelayDestinationClock

DelaySlack

Calculation?Copyright2012XilinxXilinxDesignConstraints-7InputHoldTimingReport

Summary?Copyright2012XilinxXilinxDesignConstraints-8InputHoldTimingReportDetailed

PathsSourceClock

DelayData

PathDelayDestinationClock

DelaySlack

Calculation?Copyright2012XilinxXilinxDesignConstraints-9set_input_delayset_input_delay[-clockargs][-reference_pinargs]

[-clock_fall][-rise][-fall][-max][-min][-add_delay][-network_latency_included][-source_latency_included][-quiet][-verbose]delay

objects-clockIndicatesthattheinputdelayisrelativetothespecifiedclock.Bydefaultthe

risingedgeis

usedHoweverthe-clock_fallargumentcanbeusedtoindicatethatthefalling

edgeshouldbeused

insteadBydefault,eachinputportcanhaveonemaximumdelayandone

minimumdelayMaximumdelayisusedforsetup

checkMinimumdelayisusedforhold

checkWithoutthe–maxor–minoption,thevaluesuppliedisusedfor

both?Copyright2012XilinxXilinxDesignConstraints-10InputSetupandHoldXDC

ExamplesUpstream/clk4nsCurrentData

Valid8nsValid

WindowPreviousData2ns10nsmax_delayisusedforsetupcheckcalculationattheFPGA

inputset_input_delay–clocksysclk–max4[get_portsdin]min_delayisusedforholdcheckcalculationattheFPGAinputset_input_delay–clocksysclk–min2[get_ports

din]?Copyright2012XilinxXilinxDesignConstraints-11DDRInputDelay

ExampleData

RiseData

Fall2ns10nsclkdin1nsClktoIn

Timing1ns2ns4ns 4nsUse-clock_falloptiontospecifyfallingclock

edgeUsadd_delayoptionneededtopreventfallingedgemaxminconstraintsoverridingexistingmaxmindelayconstraints(forlaunchclockrising

edge)set_input_delay1

–min–clockClk[get_portsData_In]set_input_delay2

–max–clockClk[get_portsData_In]set_input_delay1

–min–clockClk[get_portsData_In]\-clock_fall

–add_delayset_input_delay2

–max–clockClk[get_portsData_In]\-clock_fall

–add_delay?Copyright2012XilinxXilinxDesignConstraints-12Statictimingpathsstartatclockedelementsandendat

clockedelementsPathsfrominternalflip-floptointernalflip-flopareconstrainedbyclocksInputsandoutputsoftheFPGAarenotstartpoints/endpointsofstatic

timingpathsBydefault,anylogicbetweenaprimaryI/Oandaninternalclockedelementarenotpartofacompletestatictiming

pathWithoutadditionalcommands,nosetup/holdchecksaredoneon

logicassociatedwithI/OStaticTiming

Path?Copyright2012XilinxXilinxDesignConstraints-13Tocompletethestatictimingpathweneedtodescribethe

externalelementstotheVivadostatictiming

engineInputportWhatclockisusedbytheexternal

deviceThedelaybetweentheexternaldevice'sclockandthearrivalattheinputportoftheFPGAIncludestheCLK-Qtimeoftheexternaldeviceandtheboard

delayOutput

portThedelaybetweenoutputportoftheFPGAandtheexternaldevice's

clockIncludestherequiredtimeoftheexternaldeviceandtheboard

delayCompletetheStaticTiming

Path?Copyright2012XilinxXilinxDesignConstraints-14AssumeTclk=10ns,Tcomax=2ns,TDmax=3ns,thenwecanconstrain

theinputportas

belowThismeanstheinternaldelay

fromdintoFF/DinFPGAplusTsu

mustbelessthan

10-2-3=5nsInputDelay

SummarysetTco_max

2.0setTD_max

3.0setTco_min

0.0setTD_min

0.0create_clock–namesysclk–period10[get_ports

clkin]set_input_delay–clocksysclk–max[expr

{$Tco_max+$TD_max}]\[get_ports

din]set_input_delay–clocksysclk–min[expr

{$Tco_min+$TD_min}]\[get_ports

din]clkD QTsuThTCOD QTsuThTCOUpstream

DeviceFPGAdinclkinTrace

DelayLauren

GaoSettingOutput

Delay?Copyright2012XilinxXilinxDesignConstraints-2DifferentPathsUsingDifferent

ConstraintsD QTsuThTCOD QTsuThTCOBoard

ClockBoard

ClockBoardDevice

AD QBoardDevice

BD QdinaclkdinbdincdoutadoutbdoutcBUFGInternal

DelayDataPath

DelayInternal

DelayDataPath

Delayregaregbset_max_delayset_input_delayset_output_delaycreate_clock?Copyright2012XilinxXilinxDesignConstraints-3Output

DelaysysclkD QTsuThTCOTsuThTCODownstream

DeviceFPGAD QdinTrace

DelayOutputDelaymax=

TDmax+TsuOutput

Delaymin

=

Td -Tmin hReferencePoint(OppositeofOffset

Out)create_clock–namesysclk–period10[get_ports

clkin]set_output_delay–clocksysclk6[get_ports

din]UCFXDCDownstream/clkOffset

Out OutputDealyNETdinOFFSET=OUT4nsAFTER

clkin04ns5Current

Data6ns10Validclkin?Copyright2012XilinxXilinxDesignConstraints-4ExternalSetupandHold

RequirementsTsu=2ns Th=1nsData

ValidExternaldevicesneedasetupandholdtimearoundthe

clockset_output_delay-maxspecifiestherequiredsetup

timeset_output_delay-minspecifiedthenegativeoftherequiredhold

timeCapture

Edge(Downstream

Device)create_clock–namesysclk–period10[get_portsclkin]set_output_delay–clocksysclk–max2[get_portsdout]set_output_delay–clocksysclk–min-1[get_ports

dout]?Copyright2012XilinxXilinxDesignConstraints-5CompleteOutputStaticTiming

PathD QTsuThTCODownstream

DeviceTrace

DelaySourceClock

DelayDestinationClock

DelayDataPath

DelaysysclkOutputstatictimingpathissegmentedslightly

differentlyDatapathdelayendsattheportofthe

FPGADesgination