i2c24c02 design cn1BYTE數據然后讀出這個地址并

I2I2C24C0224LC021BYTE數據，然后，讀出這個地址的數據，并Figure1:I2C24C02Table1:T24LC02ModuleFunctionSystemSystem74hc595Latch74hc595Serial74hc595Shift74hc595Table2:UartRxdModuleFunction

Figure2:I2CSystemSystemReceiveddatawhenfrom0toI2CserialI2CserialRead1:StartSenddata0:StopSend1:RestartSend1:WriteAckResetRestart processhavebeen processisResetFigure3:24LC02Table3:UartTxdModuleFunctionA0~A2IAddressSerialdataSerialclockdataFigure4:I2cFigure5:24LC02ByteFigure6:24LC02RandomreadReadFigure7:24LC02WriteReadModulemodule output outputoutputoutputoutput parameterSclC1_HIGH=parameter =parameter = parameterDATA_HOLD= =27parameter = 28 T=29parameter =30parameter =4'b0000; 32parameter =34parameterMScl_IDLE=35parameterMScl_HIGH=36parameter =parameter = = =parameterRCV_DATA=parameterACK_DATA= =parameter =50reg52reg53reg55reg56reg58reg59reg61reg63reg64reg65reg66reg68wire69wire70wire73reg74wire75wire77wire[7:0] 78reg81reg82reg84reg85reg86reg87reg89wire90wire91reg92reg93wire94wire96assignSclUp=(!SclIn)&&(Scl!=97assignSclNp=( SclIn)&&(Scl==1'b0);99assign =(MScl==1'b0)?1'b0:100assignSda =(RSda==1'b0)?1'b0:1'bz;102assignIsBusy= always@(posedgeClk)if(!Rst)beginRdData<=1'b0;IsDone<=1'b0;elseif(BitC1==4'd8)beginRdData<=DataOut;IsDone<=1'b1;endelsebeginRdData<=RdData;IsDone<= 112/*******Busbuyalways@(posedgeClk)if(!Rst Busy<=1'b0;BusyD1<=1'b0;elseBusyD1<= always@(posedgeClkif(!Rst)beginIsABL<=1'b0;elseif(IsABLRst)IsABL<=0;elseif((BusyD1&&GenSta)||((DetcStpD1)&&(!GenStp)))IsABL<= 129/*******GenerateStartorStopbit always@(posedgeClkif(!Rst)beginGenSta<=1'b0;GenStp<=1'b0;DetcStpD1<=1'b0elseDetcStpD1<=if((!IsStaD1)&&(IsSta))GenSta<=1'b1;elseif(DetcSta)GenSta<=if((IsStaD1)&&(!IsSta))GenStp<=1'b1;elseif(DetcStp)GenStp<= always@(posedgeClkif(!RstbeginSdaIn<=1'b1;SclIn<=1'b1;IsStaD1<=1'b0;elseif(Scl==1'b0)SclIn<=1'b0;elseSclIn<=if(Sda==1'b0)SdaIn<=1'b0;elseSdaIn<=IsStaD1<= always@(posedgeClkif(!Rst||DetcSta)beginDetcStp<=1'b0;elseif((!SdaIn)&&(Sda!=1'b0beginif(Scl!=1'b0)DetcStp<=1'b1;elseDetcStp<=1'b0;always@(posedgeClkif(!Rst||s1==HEADER)beginDetcSta<=1'b0;elseif((SdaIn)&&(Sda==1'b0beginif(Scl!=1'b0)DetcSta<=1'b1;elseDetcSta<=1'b0;168if(!Rsts1<=IDLE;IsRstaRst<=1'b0;SdaC1En<=1'b0;RSda<=1'b1;AckErr<=elseIsRstaRst<=case(s1if((GenSta||IsRsta)&(RSda<=1;SdaC1En<=1'b1;if(SdaC1==8'd100)beginSdaC1En<=0;s1<=START; StartbeginIsRstaRst<=1'b1;RSda<=0;if(SclNp)s1<=HEADER;HEADER://ShiftEightBitsif(BitC1<4'd8)RSda<=MSda;elses1<=ACK_HEADER;if(GenStp)s1<=RSda<=1'b1;if(SclUp)SdaC1En<=beginSdaC1En<=1'b0;if(Sda==1'b0)AckErr<=1'b0;elseAckErr<=1'b1;if(SclNp)if(!AckErr elsebegins1<=STOP;beginRSda<=1'b1;if(GenStp)s1<=STOP;elseif(BitC1==4'd8)s1<=ACK_DATA;beginRSda<=MSda;if(SclNp)beginif(IsRsta)s1<=IDLE;elses1<=RCV_DATA;endif(BitC1<4'd8)RSda<=MSda;elses1<=if(GenStp)s1<=elseif(IsRsta)beginSdaC1En<=1'd0;s1<=IDLE;if(SclUp)SdaC1En<=SdaC1En<=1'b0;if(Sda==1'b0)AckErr<=1'b0;elseAckErr<=if(SclNpSdaC1En<=if(!AckErr)beginif(IsRsta)s1<=IDLE;elses1<=XMIT_DATA;elses1<=if(SclUp)SdaC1Enif(SclUp)SdaC1En<=1'b1;if(SdaC1<elseif(SdaC1==STOP_HOLD_2)RSda<=elseif(SdaC1==STOP_HOLD)beginSdaC1En<=1'b0;s1<=IDLE;//masterSclalways@(posedgeClkif(!Rsts2<=MScl_IDLE;MScl<=1'b1;SclC1En<=elsecase(s2MScl<=1'b1;if(DetcSta)s2<=

SclC1En<=1'b1;MScl<=if(SclC1==SclC1_HIGH)beginif(s1==IDLE)s2<=MScl_IDLE;elses2<= SclC1En SclC1En<=1'b1;MScl<=if(SclC1==SclC1_LOW)beginSclC1En<=1'b0;s2<=MScl_HIGH;always@(posedgeif(!Rst)beginMSda<=1'b1;elseif(s1==HEADER||s1==XMIT_DATA)MSda<=elseMSda<=wirewire 268wire269assign SlClk=(s1==RCV_DATA)?SclUp:SclNp;271SHIFT8 assignBitC1Ld=!BitC1En T 290PULLUPU0(.O291PULLUPU1(.O292Module outputoutput output[7:0] output14 15 16 18 20 21 22 25wire26wire28 29wire31assign32assign33always@(posedgeClk)SckD1<=Sck; 35parameterBIT8=37always@(posedgeClk)//countshifted38if(SckEn&&SckUp)BitC<=BitC+1'b1;elseif(BitC==BIT8)BitC<=4'd0; 40assignMosi=DirSet?SftOut:1'b1;42always@(posedgeClk)//main43 s<=1'b0;IsDone<=1'b0;SckEn<=else0://IDLEbeginIsDone<=1'b0;IsDone<=1'b0;SckEn<=1'b0;if(IsSta)s<=1'b1; SckEn<=1'b1;if(BitC==BIT8)beginRdData<=DataOut;SckEn<=1'b0;IsDone<=1'b1;s<=57//spiclockgenerator59parameterTSET=7'd1;always@(posedgeClk)//ShiftClockif(!Rst)beginSckC<=7'd0;Sck<=1'b0;SckState<=elsecase(SckStatebeginSckC<=7'd0;Sck<=1'd0;if(SckEn)SckState<=2;Sck<=1'b1;if(SckC>=TSET)beginSckState<=2;SckC<=7'd0;endelseSckC<=SckC+Sck<=if(SckC>=TSET) SckC<=7'd0;if(SckEn)SckState<=1;elseSckState<=0;elseSckC<=SckC+80wire81 82 SlClk=DirSet?SckNp:83assignIsSpiLd=84SHIFT8 97Modulemodule output outputoutputoutput parameterIDLE=parameterHEADERw=parameterADDRw=parameterSTOPw=parameterHEADERr=parameterADDRr=parameterXMITr=parameterHEADERrr=parameterREADr=parameterWAIT=4'd10;25 [3:0]26 27 [8:0]28 [7:0]29 [7:0]30 [7:0]32 33 34 35 36 37 39 40 42 43 44 43 44 47wire48assignRst=Cinit[8];50always@(posedge Clk)if(!Cinit[8])Cinit<=Cinit+1'b1;52wire53assignIsDoneUp=!IsDoneD1&&IsDone54always@(posedgeClk)IsDoneD1<=IsDone;56always if(!Rst) C1<=19'd0;s<=4'd0;read_buf<=8'd0;DirSet<=1'b0;WrData<=IsSta<=1'b0;IsAck<=1'b0;IsRsta<=elseif(IsRstaRst)IsRsta<=case(s IsSta<=1'b0;IsRsta<=1'b0;IsAck<=1'b0;if(!Sw1)s<= Led1<=4'd0;Led2<=4'd0;1://timemust>if(C1[18]!=1'b1)C1<=C1+1'b1;elsebeginC1<=19'd0;s<= if(!IsBusy)beginDirSet<=1'b1;WrData<=8'b1010_0010;IsSta<=1'b1;s<=4'd3;Led1<=4'd2; if(IsDoneUp)beginWrData<=8'b0000_1000;s<=4'd4;Led1<=4'd3; //Writeif(IsDoneUp)beginWrData<=8'b0001_0011;s<=4'd5;Led1<=4;5://WriteDataif(IsDoneUp)beginIsSta<=1'b0;s<=4'd6;Led1<=4'd5;if(C1[18]!=1'b1)C1<=C1+1'b1;elsebeginC1<=