quartus使用timequest時(shí)序分析TimeQuest需要讀入布局布線后網(wǎng)表才能進(jìn)行

Nets：同一個(gè)Cell中，從輸入Pin到輸出Pin經(jīng)過(guò)的邏輯。特別注意：網(wǎng)表中雖然連接兩個(gè)相鄰Cell的連線不被看作Net，但是這個(gè)連線還是有其物理意義的，等價(jià)于 Clockpaths：ClockPortclockPinCellPin。PinCellPin。LaunchEdge：LatchEdge：后級(jí)寄存器捕獲數(shù)據(jù)對(duì)應(yīng)的時(shí)鐘沿，使時(shí)序分析的終點(diǎn)。有了上述的諸多概念，我們就可以得到時(shí)序分析的基本項(xiàng)了DataArrivalTime：LaunchEdgeClockpathCellPinPinNet（uTco）DatapathDataRequiredTime：LatchEdge+Clockpath（uTh）或（-uTsuClockArrivalTime：LatchEdge+后級(jí)寄存器ClockpathClockysis部分。DataRequiredTime（Slack）。當(dāng)時(shí)序余量為負(fù)值時(shí)，就發(fā)生了時(shí)序（TimingViolation）（SetupTime）Launchedge的數(shù)據(jù)輸入Pin的速度不能太慢，時(shí)間不能太長(zhǎng)，否則會(huì)后級(jí)寄存器數(shù)據(jù)輸入Pin相對(duì)LatchedgeDataRequirededge）。顯然，在建立時(shí)間檢查中，DataArrivalTimeDataRequiredTime，否則就會(huì)造成建立時(shí)間。也就是說(shuō)，DataRequiredTime是DataArrivalTime的最ClockSetupSlack=DataRequiredTime–DataArrivalDataArrivalTime=LaunchEdge+ClockNetworkDelaySourceRegister+Register-to-RegisterDataRequiredTime=ClockArrivalTime–μtsu–SetupClockArrivalTimeLatchEdgeClockNetworkDelaytoDestinationRegisterClockSetupSlackTime=DataRequiredTime–DataArrivalumDelayofPin+Pin-to-RegisterDelayDataRequiredTime=ClockArrivalTime–ClockArrivalTime=LatchEdge+ClockNetworkDelaytoDestination3)（Register-to-Pin）ClockSetupSlackTime=DataRequiredTime–DataArrival+Register-to-PinDataRequiredTime=ClockArrivalTime–OutputumDelayofPinClockArrivalTime=LatchEdge+ClockNetworkDelaytoDestinationRegister的第一項(xiàng)是相同的；ClockArrivalTime的是相同的。所以，第一組可以歸納如下：ClockSetupSlackTime=DataRequiredTime–DataArrivalDataArrivalTimeDataRequiredTime其中，后兩個(gè)的第二項(xiàng)在其他情況下適當(dāng)修改即可。這就和一些書中講到時(shí)序分析時(shí)采用的一致了report_timing-from[get_registersreg1]-to[get_registersreg2]--npaths1-panel_name"Report（HoldTime）LatchedgeDataDataTime，否則就會(huì)造成保持時(shí)間。也就是說(shuō)，DataRequiredTime是DataArrivalTime晚了，會(huì)造成下一個(gè)時(shí)鐘沿的建立時(shí)間，當(dāng)前時(shí)鐘沿發(fā)送的數(shù)據(jù)不能被下一個(gè)時(shí)鐘沿捕獲；早了，會(huì)造成上一個(gè)時(shí)鐘沿發(fā)送的數(shù)據(jù)保持時(shí)間，上一個(gè)時(shí)鐘沿發(fā)送的數(shù)據(jù)不能被二者在計(jì)算上的區(qū)別在于Slack計(jì)算中減數(shù)與被減數(shù)關(guān)系ClockHoldSlack=DataArrivalTime–DataRequired+RegistertoRegisterDataRequiredTime=ClockArrivalTime+μtH+HoldClockArrivalTimeLatchEdgeClockNetworkDelaytoDestinationRegisterClockSetupSlackTime=DataArrivalTime–DataRequiredMinimumDelayofPin+PintoRegisterDelayDataRequiredTime=ClockArrivalTime+ClockArrivalTime=LatchEdge+ClockNetworkDelaytoDestination3)（Register-to-Pin）ClockSetupSlackTime=DataArrivalTime–DataRequired+RegistertoPinDataRequiredTime=ClockArrivalTime–OutputMinimumDelayofPinClockArrivalTimeLatchEdgeClockNetworkDelaytoDestinationRegister需要注意的是，上面中的LatchEdge實(shí)際對(duì)應(yīng)的是上一個(gè)LaunchEdge。所以，當(dāng)LaunchClock和LatchClock是同一個(gè)時(shí)鐘時(shí)，上述中的LatchEdge等于0；當(dāng)前LatchEdge1-panel_name"ReportTiming"（RecoveryTime）Latchedge和相應(yīng)的建立時(shí)間之間，否則會(huì)導(dǎo)致寄存器的建立時(shí)間，數(shù)據(jù)輸出進(jìn)入亞穩(wěn)態(tài)。即從前級(jí)寄存器的Launchedge開始計(jì)時(shí)，經(jīng)過(guò)一系列的時(shí)序路徑，前級(jí)寄存器數(shù)據(jù)輸出到達(dá)后級(jí)寄存器異步從上述定義，可以得到和建立時(shí)間檢查類似的RecoverySlackTime=DataRequiredTime–DataArrival+RegistertoRegisterDataRequiredTime=ClockArrivalTime–ClockArrivalTimeLatchEdgeClockNetworkDelaytoDestinationRegisterRecoverySlackTime=DataRequiredTime–DataArrivalDataArrivalTime=LaunchEdge+umInputDelay+PorttoRegisterDelayDataRequiredTime=ClockArrivalTime–μtSUClockArrivalTime=LatchEdge+ClockNetworkDelaytoDestinationreport_timing-from[get_portsasync_rst]-to[get_registersreg2]--npaths1-panel_name"Report（RemovalTime）Latchedge和相應(yīng)的保持時(shí)間之間，否則會(huì)導(dǎo)致寄存器的保持時(shí)間，數(shù)據(jù)輸出進(jìn)入亞穩(wěn)態(tài)。即從前級(jí)寄存器的Launchedge開始計(jì)時(shí)，經(jīng)過(guò)一系列的時(shí)序路徑，前級(jí)寄存器數(shù)據(jù)輸出到達(dá)后級(jí)寄存器異步從上述定義，可以得到和保持時(shí)間檢查類似的RemovalSlackTime=DataArrivalTime–DataRequiredofSourceRegister+RegistertoRegisterDataRequiredTime=ClockArrivalTime+ClockArrivalTime=LatchEdge+ClockNetworkDelaytoDestinationRemovalSlackTime=DataArrivalTime–DataRequiredDataArrivalTime=LaunchEdge+InputMinimumDelayofPin+MinimumPintoRegisterDelayDataRequiredTime=ClockArrivalTime+ClockArrivalTime=LatchEdge+ClockNetworkDelaytoDestinationreport_timing-from[get_portsasync_rst]-to[get_registersreg2]--npaths1-panel_name"Report五、多周期路徑（MulticyclePaths）獲；LaunchedgeLatchedgeLauchedgeLatchedge。這一設(shè)計(jì)意圖不照單周期路徑檢查的方式執(zhí)行，往往會(huì)誤報(bào)出時(shí)序。不設(shè)置多周期路徑約束的有兩種一是按照單周期路徑檢查的結(jié)果虛報(bào)時(shí)序；本應(yīng)該多個(gè)周期完成的操作，造成過(guò)約束（Over-Constrain）。過(guò)約束會(huì)本應(yīng)該讓位于其他邏輯的布局布線資源，有可能造成其他關(guān)鍵路徑的時(shí)序或時(shí)序余量變小。在多周期路徑的建立時(shí)間（SetupTime）檢查中，TimeQuestDataRequiredTime，放松對(duì)相應(yīng)數(shù)據(jù)路徑的時(shí)序約束，從而得到正確的時(shí)序余量計(jì)算結(jié)果；在保持時(shí)間（HoldTime）檢查中，TimeQuestDataRequiredTime，仍時(shí)間對(duì)應(yīng)的多周期個(gè)數(shù)。TimeQuest計(jì)算HoldTime的缺省不同于PrimeTime。在有些并多會(huì)造成保持時(shí)間檢查，需要用戶指定保持時(shí)間檢查對(duì)應(yīng)的時(shí)鐘沿為L(zhǎng)aunchedge最近的時(shí)鐘沿。（西電《數(shù)字IC系統(tǒng)設(shè)計(jì)》p189）隨文附上一 ，可以采用上面令執(zhí)行并觀察結(jié)果。該實(shí)例改編 multicycle_exception。TechnologyMapViewer面的一篇文章中，給出了建立時(shí)間檢查的基本ClockSetupSlack=DataRequiredTime–DataArrivalDataArrivalTime=LaunchEdge+ClockNetworkDelaySourceRegister+μtcoRegister-to-RegisterDataRequiredTime=ClockArrivalTime–μtsu–SetupClockArrivalTimeLatchEdgeClockNetworkDelaytoDestinationRegisterClockSetupSlackTime=DataRequiredTime–DataArrivalDataArrivalTime=LaunchEdge+ClockNetworkDelaytoSourceRegister+InputumDelayofPin+Pin-to-RegisterDelayDataRequiredTime=ClockArrivalTime–ClockArrivalTime=LatchEdge+ClockNetworkDelaytoDestination3)（Register-to-Pin）ClockSetupSlackTime=DataRequiredTime–DataArrivalDataArrivalTime=LaunchEdge+ClockNetworkDelaytoSourceRegister++Register-to-PinDataRequiredTime=ClockArrivalTime–OutputumDelayofClockArrivalTime=LatchEdge+ClockNetworkDelaytoDestination兩組中，DataRequiredTime計(jì)算的第二項(xiàng)都是-uTsuTimeQuestreport_timing-from[get_portsdata_in]to[get_registersreg1]setupnpaths1panel_name"ReportTiming"DataRequiredTimereg1uTsu在Incr一列中，reg1的uTsu取值為0.036ns，在計(jì)算中作為正數(shù)值計(jì)入了DataRequiredTime計(jì)算正確，但是TimeQuest計(jì)算錯(cuò)誤我一直傾向于后一種可能，畢竟TimeQuest是Al 后一種可能雖然更合理，但是又沒(méi)有充足的證明這一點(diǎn)，這一數(shù)據(jù)是Al TimeQuest下面，讓我們通過(guò)輸出引腳的建立時(shí)間檢查（3）來(lái)證明一下：仍然以兩級(jí)級(jí)聯(lián)寄存器為例，計(jì)算重寫如下：3)（Register-to-Pin）ClockSetupSlackTime=DataRequiredTime–DataArrivalDataArrivalTime=LaunchEdge+ClockNetworkDelaytoSourceRegister++Register-to-PinDataRequiredTime=ClockArrivalTime–OutputumDelayofClockArrivalTime=LatchEdge+ClockNetworkDelaytoDes