數(shù)字邏輯5章-英文課件

Chapter5HardwareDescriptionLanguages5.1HDL-BasedDigitalDesign5.1.1WhyHDLs?Inpreviousdecades,usedblockdiagramsandschematics.Reason:Synthesizable.Thedevelopmentofprogrammablelogicdevicesandvery-large-scaleASICtechnology.Synthesistoolscansupportmuchlargersystemdesigns.5.1.2HDLToolSuitesTexteditorCompilerSynthesizerSimulatorTemplategeneratorSchematicviewerTranslatorTiminganalyzerBackannotator5.1.3HDL-BasedDesignFlowStepsinanHDL-baseddesignflow:5.4TheVerilogHardwareDescriptionLanguageVersion:Verilog-1995Verilog-2001Features:Designsmaybedecomposedhierarchically.Eachdesignelementhasawell-definedinterfaceandaprecisefunctionalspecification.Concurrency,timing,andclockingcanallbemodeled.Thelogicaloperationandtimingbehaviorofadesigncanbesimulated.5.4.1ProgramStructureBasicunitofdesignandprogramming:ModuleModuleDeclarationStatementEx.—Verilogprogramforan“inhibit”gateDeclarationStatementNote:Keywordsandidentifierarecasesensitivity.SyntaxofaVerilogmoduledeclaration:SyntaxofaVeriloginput/outputdeclarations:5.4.2LogicSystem,Nets,Variables,andConstants1.LogicSystemThepossiblevaluesofa1-bitsignal:0Logical0,orfalse1Logical1,ortrueXAnunknownlogicalvalueZHighimpedance,asinthree-statelogicBitwisebooleanoperatorsinVerilog’slogicsystem:2.NetsNet:Providesconnectivitybetweenmodulesandotherelements.Verilognettypes:Note:Wireisthedefaultnettype.SyntaxofVerilogwireandtrinetdeclarations:3.VariablesRegandInteger:Themostcommonlyused.SyntaxofVerilog

regandintegervariabledeclarations:Avariable’svaluecanbechangedonlywithinproceduralcodewithinamodule.4.ConstantsLiteralFormat:n'Bdd…dn:Adecimalnumberthatgivethesizeoftheliteralinbits.B:Asingleletterspecifyingthebase.b(binary),o(octal),h(hexadecimal),d(decimal)dd…d:Astringofoneormoredigitsinthespecifiedbase.Parameter:ConstantswithinamoduleSyntaxofVerilogparameterdeclarations:5.4.3VectorsandOperators1.Vectorreg[a:b]word;/*aistheleftmostbitofword,bistherightmostbitofword.*/Ex.

reg[7:0]byte1,byte2,byte3;

reg[15:0]word1,word;

reg[1:16]Zbus;Bit-select:bytel[7],Zbus[16].Part-select:Zbus[1:8],Zbus[9;16].Concatenation:{2'b00,2'b11}4'b0011{2{byte1},2{byte2}}{byte1,byte1,byte2,byte2}2.OperatorsShiftoperators:Vacatedpositionsfilledwith0s.ArithmeticandshiftoperatorsinVerilog:Treatvectorsasunsignedintegers.regsigned[15:0]A;outputsigned[15:0]A;8'bs11111111;//signedlettersEx.8'b11010011<<38'b10011000Verilog-2001:Provideforsignedandunsignedarithmetic.Ex.5.4.4ArraysSyntaxofVerilogarraydeclarations:Ex.reg[7:0]byte1,recent[1:5],mem1[0:255],mem2[0:511];

/*byte1:an8-bitvector,others:arrayscontaining5,256,and5128-bitvectors,respectively.*/5.4.5LogicalOperatorsandExpressionsVeriloglogicaloperators“==”and“!=”:Abit-by-bitcomparison.Evaluatethetruthorfalsehoodofeachoperandfirstly.Ex.4'b0100&&4'b1011true4'b0100&4'b1011falsePrecedencePrecedence!~*/%+-<<>><<=>>===!====!==&^^~|&&||?:ThemostprecedenceThelowestprecedence5.4.6CompilerDirectives`includefilenameThenamedfileisreadimmediatelyandprocessedasifitscontentswerepartofthecurrentfile.Readindefinitionsthatarecommontomultiplemodulesinaproject.Nestingisallowed.`defineidentifiertextNoendingsemicolon.Replaceeachappearanceofidentifierwithtext.5.4.7StructuralDesignElementsThreedesignstylesThecorrespondingcurrentstatementStructuraldesignInstancestatementDataflowdesignContinuous-assignmentstatementBehavioraldesignAlwaysblocksTheabovedesignstylesandthecorrespondingstatementscanbeintermixedwithinaVerilogmoduledeclaration.Verilogbuilt-ingates:SyntaxofVeriloginstancestatements:ThefirstformatThesecondformatThefirstformatNote:Thebuilt-ingatescanbeinstantiatedonlyusingthefirstformat.Thelocalexpressionsarelistedinthesameorderastheportstowhichthey’resupposedtoconnect.Ex.1—StructuralVerilogprogramforan“inhibit”gateThesecondformatNote:Librarycomponentsanduser-definedmodulescanbeinstantiatedwitheitherthefirstorthesecondformat.Portsassociationscanbelistedinanyorder.LogicdiagramcorrespondingtotheVrSillyXORmodule:Ex.2—StructuralVerilogprogramforanXORfunction5.4.8DataflowDesignElementsContinuous-assignmentstatement:Describeacombinationalcircuit.SyntaxofVerilogcontinuous-assignmentstatements:Ex.—

Prime-number-detectorcodeusingaconditionaloperator.5.4.9BehavioralDesignElements(ProceduralCode)Thekeyelementofbehavioraldesign:alwaysblock.SyntaxofVerilogalwaysblocks:SensitivitylistNote:Whenanysignalinitssensitivitylistchangesvalue,alwaysblockexecution.Proceduralstatementinanalwaysblockexecutesequentially.Allofthesignalsthataffecttheoutcomesoftheproceduralstatementsshouldbelisted.Proceduralstatementsthatareusedwithinanalwaysblock:Blockingassignmentnonblockingassignmentbegin-endblocksifcasewhilerepeat1.BlockingandNonblockingassignmentstatementsBlocking?

Blocktheexecutionofsubsequentproceduralstatementsinthesamealwaysblock.Nonblocking?Assignthevaluetothelefthandsideuntiltheentirealwaysblockhascompletedexecution.Note:Alwaysuseblockingassignments(=)inalwaysblocksintendedtocreatecombinationallogic.Alwaysusenonblockingassignments(<=)inalwaysblocksintendedtocreatesequentiallogic.Donotmixblockingandnonblockingassignmentsinthesamealwaysblock.Donotmakeassignmentstothesamevariableintwodifferentalwaysblocks.Ex.—Prime-numberdetectorusinganalwaysblockThesignalthatappearsonthelefthandsideofanassignmentstatementinanalwaysblockmustbedeclaredasaregvariable.2.Begin-endblocksNote:Theproceduralstatementswithinabegin-endblockexecutesequentially.Thebegin-endblockmustbenamedwhentheblockhasitsownlocalparametersorvariables.Ex.—Prime-numberdetectorusingmultiplestatementsin

analwaysblock3.IfstatementEx.—Prime-numberdetectorusinganifstatementIfstatementcanbenested!4.CasestatementNote:Avoidnonparallelcasestatementandnot“all-inclusive”case.Ex.—Bus-selectormoduleusingcasestatement5.ForstatementForsynthesis!Ex.—Prime-numberdetectorusingaforstatementCan’tbesynthesizable!6.Repeat,whileandforeverstatementNote:Theabovestatementscan’tbeusedtosynthesizecombinationallogic,onlysequentiallogic.5.4.10FunctionsandTasksFunction:Acceptsanumberofinputsandreturnsasingleresult.Note:Afunctionmaynothaveanyoutputorinoutdeclarations.Butitmaynotdeclareanynetsornestedfunctionsandtasks.Afunctionexecutesinzerosimulatedtime,andthereforcan’tcontainanydelayorothertiming-relatedstatements.Thevaluesofanylocalvariablesarelostfromonefunctioncalltothenext.Ex.—VerilogprogramforanXORgateusingan“inhibit”

function2.TaskNote:Taskdoesnotreturnaresult.Built-insystemtasksandfunctionsthatareusedintestbenchesandsimulation:$display,$write,$monitor,$monitoroffand$monitoron,$time,$stop.5.4.11TheTimeDimensionTimedelaystatement: