數(shù)字集成電路設(shè)計(jì)new

1.1Introduction

Designingefficient,reliable,robustdigitalcircuitsrequiresadherencetotheprinciplesofgooddesignpractice.Forthemostparttheseareapplicableregardlessofwhethertheimplementationisdiscreteorcustomised.Badlydesigneddigitalcircuitryhasatendencytogeneratetiminghazardssuchasspikesandglitches.Whilstadesignmayexhibitcorrectfunctionalitymanyoftheproblemsassociatedwithpoorreliabilityareattributedtothewayinwhichthesehazardsarehandled.ItisvitallyimportantthatdesignsintendedforimplementationonASICsmustconformtoalltheacceptedrulesofbestpracticefordigitaldesign.Failuretodosocanresultindesignsthatareunsafe,difficulttotestandwhoseoperationcannotbeguaranteed.Maskprogrammabledevicesinparticulararehighriskwhenattemptingtoachievearightfirsttimedesign.Forthisreasonthesiliconfoundrywillinsistthatthedesignercompletesasign-offformindicatingcompliancewithallthefoundrydefinedrecommendations.Incaseswherenon-complianceoccursthesemustbediscussedwiththefoundrydesigncentreandappropriateauthorisationobtainedbeforethedesigncanbeaccepted.Thisunitreviewstheprinciplesofbestpracticeandidentifiesanyadditionalconsiderationsthatarespecificallyrelevanttorealisationonsilicon.

Itisassumedthatthereaderisalreadyfamilarwiththebasiccombinationalandsequentiallogicelementsandtheiruseintheconstructionofstandarddigitalfunctions.

Digitaldesignisrarelytaughtfromthepracticalpointofview.

Someessentialinformationthatiscertaintoberelevanttoeveryoneiscontainedinanotherpagethatweexpectyouwillfindusefulthroughoutthismodule.

PleaserefertotheDigitalDesigner'sGuidenow,beforecontinuingwiththisunit.

DigitalDesigner'sGuide

1.2DigitalCircuitStructures

Digitalcircuitscanbeclassifiedascomprisingtwodistinctfunctionalstructures,dataflowandcontrol.Dataflowelementsprocessdatawhilstcontrolelementsdefinethemannerinwhichthisprocessingisperformed.Designscanbeexclusivelydatafloworcontrolbutgenerallycompriseamixofbothasshownbelow.

Figure1.1DigitalCircuitStructures

ControlelementsprovideControlandStatussignalstoandfromtheDataflow.ControlsignalsaregeneratedfromdefinedcontrolsequenceswhilstStatussignalsareusedtomodifytheflowofsuchsequences.InterfaceSignalsareoftenneededtofacilitatecommunicationwithotherpartsofthedesignorcomponentsexternaltothechip.

Exampleswouldbeinputsfromsensors,outputstocontrolledelements,protocolsignalssuchasDataAvailable&DataAcceptedetc.TheinclusionofsequentiallogicelementsinControlStructuresrequirestheprovisionofasystemClocktosynchroniseactivitywiththerestofthedesignandageneralResettoinitialisethesystemtoaknownstartingconditionforbothnormalandtestoperatingmodes.

Designingcontrolelementsisoftenthemostdifficultpartofadigitalsystemimplementation.Asdesignshavegrowninsizeandcomplexitytherehasbeenamovetowardsreplacingintuitivedesigntechniquesandresultingcustomisedcircuitrywithmoreformaldesignmethodologiesandstandardiseddesignstructures.TheFiniteStateMachineisanexampleofastandardcontrolstructureimplementationthatcanbedesignedbyatechniqueknownastheAlgorithmicStateMachine(ASM)method.BoththesearecomprehensivelyexplainedinUnit2ofthismodule.

Dataflowelementsinput,logicallymanipulateandthenoutputdata.Typicallytheycomprisearrangementsofcombinationalandsequentiallogiccomponents.Controlsignalsareappliedtomovedatathroughthedataflowinaspecificway,eg.theadd/subtractsignalonanaddercomponentwhilststatussignalsprovideinformationrelatingtospecificconditionsarising,eg.azerovalueonacountercomponent.Dataflowdesignisgenerallylessformalisedthancontrolbutanumberofstandardstructuresexistforthemainlogicfunctionseg.adders,counters,shifters,multiplexorsetc.

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1.3

DigitalLibraryComponents

AnASICdesignerwillbeprovidedwithaCellLibrarycontainingavarietyofcombinationalandsequentiallogiccomponents.Thesecanbecategorisedasfollows:

PrimitiveComponents

Theseofferthelowestleveloffunctionality,typicallyAND,OR,NOTgates,FLIP-FLOPSetc.thatarethebasicelementsoflogiccircuits.TheMietecStandardCellLibrary,forexample,comprisesalargeproportionoftheseelements.Clickonacategorytoseethecomponentsavailable.

Category

Description

SimpleGates

Basiclogicfunctions

ComplexGates

Basiclogiccombinations

Latches

Leveltriggeredstorageelements

Flip-Flops

Edgetriggeredstorageelements

Definingcomponentsattheprimitivelevelprovidesanumberofadvantages:

Theflexibilitytoconstructtherandomlogicusuallyrequiredaroundhigherlevelfunctions.

Theabilitytodefinenon-standardcomponentsnotavailableinthecelllibrary.Forexampletherewilltypicallybearangeof4bitand8bitcountersinthelibrarybutnootherbitlengths.

Theopportunitytodefinesiliconefficientstructures.Forexampleacountercomponentfromthecelllibrarymayhavealoadfacilitynotrequiredbythedesign.Utilisingaprimitivelevelimplementationwillnotincludethisfeature.

Aprimitivelevelcircuitwillgenerallyprovidethemostefficientimplementationintermsofchipareaandspeed.ForthisreasonalogicsynthesisercompilingdownfromahighlevelfunctionallanguagesuchasVHDLorVerilogwilltendtogenerateaprimitivecomponentimplementation.

Designingmanuallywiththesecomponents,however,willinevitablylengthenthedesigntimeandincreasetheriskofdesignerrors.

MacroComponents

Thesearehigherlevelfunctions,typicallyadders,comparators,multiplexors,counters,shiftersetc.thatarethebasicfunctionsoflogiccircuits.TheAlteraProgrammableLogicDevicelibrary,forexample,providesacomprehensivesetofmacrocomponents.

Figure1.2MacroComponents

WithineachcategorythereisasetofASICequivalent

implementationsforstandard74seriescomponentsasintheDecodercategoryshownbelow.

Figure1.3DecoderMacrofunctions

Definingcomponentsatthemacrolevelprovidesanumberofadvantages:

Shorterdesigntimes

GuaranteedcorrectfunctionalitybytheASICvendor

Easymigrationtosiliconofdesignsconstructedfromdiscretestandardcomponents

Amacrolevelcircuitcanbedesignedmorequicklywithlesspotentialfordesignerrorsbutcouldbelessefficientinutilisingsilicon.Oftentherewillbefeaturesavailableonamacrocomponentthatarenotrequiredandwillneedtoberenderedinactivebytyingoffrelatedinputstotheappropriatelogiclevels.

GeneratedComponents

AnumberofASICdesignsystemsincorporateafacilityforgeneratinguserdefinedlogicfunctions.ThesecanrangefromcustomisedmacrocomponentstohighlevelfunctionalblockssuchasRAM(RandomAccessMemory),ROM(ReadOnlyMemory)andPLA(ProgrammableLogicArray).

ThefollowingisaXilinxmenuforgeneratingacustomisedcounterwithvariousoptionsfordefiningclock,reset,countdirection,bitlengthetc.

Figure1.4GeneratedComponents

Generatedcomponentsoffertheshortestdesigntimesandthemostefficientutilisationofsiliconarea.

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1.4

UnusedInputsandOutputs

Oftenwhenconstructingaschematicforadigitalcircuittherewillbecomponentpinstowhichnothingneedstobeconnected,asintheflip-flopexamplebelow.

Figure1.5UnusedInputsandOutputs

TherearespecificconnectionsfortheD(Data),CLK(Clock),R(Reset)andQpinsbutnonerequiredfortheS(Set),EN(Enable)andNQpins.Therulesareasfollows:

UnusedInputs

NEVEREVERLEAVEUNUSEDINPUTSOPENCIRCUIT.Theymustalwaysbetiedofftoappropriatelogiclevels.SomeASICtopologieswillhavepullup/pulldowndeviceswithinthecomponentcircuit,otherswillnot.Inbothcasesleavinganinputopencircuitwillrenderitsusceptibletopickingupsignalsfromadjacentmetaltrackingonthesiliconcausingthecomponenttologicallymalfunction.Anadditionalproblemoccurswithcomponentsthathavenopullup/pulldowndevices.Sinceaninputisnoweffectivelyfloatingitcanassumeeitherlogiclevelmakingtheoperationofthecomponentunpredictable.

Atthesiliconlevelanunusedinputwillbeconnectedtooneorotherofthepowersupplyrails,power(VDD)foralogic1andground(GND)foralogic0.Thisisdenotedontheschematicinoneoftwowaysdependingonthedesignsystembeingused.

1)

Thecelllibrarysuppliessymbolsforthepowersupplylevels.ThismethodisillustratedontheENinputoftheexample.

2)

Thewireconnectingtothecomponentpincanbenamedwiththeappropriatepowersupplylabel.ThismethodisillustratedontheSinputintheexample.

Inallcasesthecorrectlogiclevelmustbespecifiedtoachievetherequiredlogicfunctionality.Intheexample,theENinputneedstobealogic1toenablethecomponenttofunctionbuttheSinputmustbeatlogic0toavoidthecomponentsetfunctionbeingactivated.

UnusedOutputs

UnusedoutputscanbesafelyleftopencircuitaswiththeNQoutputintheexamplebutNEVERATTEMPTTOCONNECTTWOORMOREOUTPUTSTOGETHER.InexperienceddesignersassumethatthiswillprovideanANDoranORfunction.Itsimplyshortstheoutputstogetherproducinganoutputvoltagethatcorrespondstoneitherofthedefinedlogiclevels.Usetheappropriatelogicelementforthefunctionrequired.

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1.5

FanoutsandLoading

Signalssuchasclocksandresetsthatareheavilyloadedandothersignalswhosetimingiscriticalneedspecialattention.InTTLtechnologiesincreasingtheloadingonasignalresultsinadeteriorationofthelogiclevels.InMOStheresultistoaddcapacitancewhichslowsdowntheedges,increasesthepotentialformetastability(flip-flopscapturingasynchronousdata),introducesclockskewandcanquicklyturnasynchronousdesignintoanasynchronousone.TheeffectisdemonstratedbelowforaCMOScircuitcontainingbothanunloadedandaloadedinverter.

Figure1.6Composer-SchematicEditing:inverterloadedlogicschematic

Theunloadeddeviceexhibitsasmallexponentialedgedeteriorationonitsoutputduetothecharginganddischargingofitsintrinsiccapacitance.Theloadeddevice,however,drivestheadditionalinputcapacitanceofitsloaddevicesandtheirassociatedtrackinterconnectandassuchexhibitsamuchmorepronouncedeffect.

Figure1.7WaveformWindow

Logicsimulatorsallowforthiseffectbycalculatingtheoverallpropagationdelayofacomponentwithreferencetoadditionaldelaydataasintheexamplebelow.

CellType

Transition

UnloadedDelay(ns)

LoadValue

Delay/UnitLoad(ns)

Loads

TrackDelay(ns)

TotalDelay(ns)

INVERTER

low-high

1

1

0.4

6

0.1

3.5

high-low

0.7

1

0.25

6

0.1

2.3

Thesimulatorperformsthefollowingcalculation:

TotalDelay(low-high)=Unloadeddelay+(UnitLoadsxDelay/UnitLoadsxLoads)+TrackDelay

=1ns+(1x0.4nsx6)+0.1ns

=3.5ns

TotalDelay(high-low)=0.7ns+(1x0.25nsx6)+0.1ns=2.3ns

TheLoadValueindicatestheloadingeffectacomponentinputexertsontheoutputofanothercomponentfromwhichitisbeingdriven.Typicallyaninvertercircuitistakenasthereferencesinceitcomprisestheminimumnumberoftransistors(1PMOSand1NMOS)withtheinputsignalconnectedtothegatesofbothdevices.Morecomplexfunctionswillhavehigherloadvalues.ForexampleanEXCLUSIVEORcomponentimplementingthefunctionA'B+AB'asacomplexgatewillhavealoadvalueof2,eachinputfeeding1PMOSand1NMOStransistorintheAND/OR

structureplus1PMOSand1NMOStransistorconfiguredasainvertertoprovidetheNOTfunction.Thusintheexampleaninverterfeeds6similarcomponentssotheloadingis6x1.Ifitwerefeeding6EXCLUSIVEORgatestheloadingwouldbe6x2.

TheDelay/UnitLoadisavalueprovidedbythesiliconfoundry,usuallyobtainedfromparametrictestingofcircuitsamples.

TheLoadsfigureisobtainedfromtheschematic.

TheTrackDelayisobtainedafterlayouthasbeencompletedsowillnotbepresentindesignsimulationsbutwillbeincorporatedintoafinalpost-layoutsimulation.

Thesimulatorwillindicatetheeffectofsignalloading.SomeCADsystemsimposealimitonthenumberofloadsthatcanbeconnectedtoasignalandcheckforthisduringthedesignprocess.Othersleaveittothedesigner.Agoodruleofthumbistolimitthenumberofloadsto10.Notonlywillthisminimisetiminghazardsbutwillalsoassisttherouterduringthelayoutprocesssinceashortlengthofinterconnectiseasiertoroutethanalongone.

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1.6

BufferingStrategies

Toeliminateorminimisetheeffectsofsignalloading,designersshouldconsideranappropriatesignalbufferingstrategybothtoequalisetheloadandprovideincreaseddrivecapability.

Non-RecommendedBuffering

Shownherearetwoexamplesofnon-recommendedbuffering.Inthelefthandexamplesomeclocklinesarebuffered,othersarenot.Clocksignalstravellingthroughthebufferedlineswillbedelayedrelativetothosethatarenot.Consequentlysomeofthelogicelementsbeingfedfromthecircuitwillreceivetheclockbeforeothers,aneffectknownas'clockskew'.

Intherighthandexampleunequalloadinginthebufferingcircuitwillagainproducedifferentialdelaysintheclocklinesresultinginclockskew.

Figure1.8Non-RecommendedBuffering

RecommendedBuffering

Acorrectlydesignedbufferingcircuitwillprovidethesamedepthofbufferingineachlineandthesamefanoutonallbuffers.ThisisknownasBalancedTreeBuffering.Moreover,inordertokeepsignaledgessharpbuffersmustbelightlyloaded.ThisarrangementisreferredtoasGeometricTreeBuffering.Note,however,thatevenwhentheseprincipleshavebeenappliedatthecircuitdesignstage,thelayoutprocesscanproducedifferingtrackingcapacitanceswhichwillintroduceimbalanceintothefanout.Forthisreasonisitessentialthatafinalpost-layoutsimulationthatincludestheseadditionaldelaysisperformedandthedesigntimingchecked.

ThecircuitbelowshowsanexampleofBalancedTreeBufferinginwhichallclocklinesareequallyloaded.

Figure1.9RecommendedBuffering

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1.7

SystemResets

DesignsimplementedonASICsarerequiredtobebroughttoaknownstatewithinagivennumberofclockcycles.Thisisnecessarybothfornormaloperationwhereacircuithastobeinitialisedtoagivenstartingconditionandalsoduringtestingbeforeasequenceoftestpatternscanbeapplied.Therecommendedmethodofachievingthisistoapplyanasynchronoussystemresettoallsequentialelementsinthecircuit.

RecommendedSystemReset

Hereanexternalsystemresetisappliedviaaninputpintotheresetinputsofallsequentialelementssothattheentirecircuitcanbeinitialisedsimultaneously.Theresetsignalcanbeprovidedbyanexternalpower-oncircuitorresetbuttonorboth.AlternativelysomeASICtopologiesprovideapower-onresetperipheralpadspecificallyforthispurpose.Whenthisfacilityisusedaseparateresetmustalsobeincorporatedfortestpurposessinceitisusuallynecessarytore-initialisethecircuitseveraltimesduringatestrun.

Figure1.10RecommendedSystemReset

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1.8

LocalResets

SynchronousdesignsarealwaysrecommendedforimplementationonASICs.Anyasynchronousoperationimmediatelyincreasesthepotentialfortiminghazardsandmakestestingdifficult.Insituationswheresectionsofsequentiallogicrequirealocalresetthisshouldalwaysbedonesynchronously.

Non-RecommendedLocalReset

Thecircuitbelowdetailsacommontechniqueemployedtoasynchronouslyresetsequentialelementssuchascounters.

Thecircuitviolatestherulesofsynchronousdesign.Thesecondflip-flopcanchangestateatatimeotherthantheactiveclockedge.Thereisalsoapotentialraceconditionbetweentheclockandtheresetofthisflip-flop.

Figure1.11Non-RecommendedLocalReset

Non-RecommendedLocalReset

Similarproblemsoccurwhencombinationallogicisusedtogenerateareset.Acommonapplicationofthisdesignstyleistheuseof

decodinglogicontheoutputsofacounter.

TypicallyAND/ORgateswillbeusedtodetectarequiredstateinthecountingsequenceandprovideanasynchronousresetbacktothecounterresetinputs.

Figure1.12Non-RecommendedLocalReset

RecommendedLocalReset

Therecommendedalternativetoprovidingasynchronousresetstothesetypeofcircuitsistoclocktheflip-floptotherequiredzerostate.Thiseffectivelyproducesasynchronousreset.

Inthiscircuitallflip-flopsaresynchronisedtotheclock.Aresetrequiredonthesecondflip-flopasaresultofsignalrgoingactivewillnowoccuronthenextrisingedgeoftheclock.

Figure1.13RecommendedLocalReset

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1.9

SystemClocks

Greatcarehastobetakenwhenhandlingclocksinsequentialdesigns.Unwantedspikes,glitches,clippedpulsewidthsandadditionalclockpulsesallprovidepotentialforcircuitfailure.Feedingclocksintocombinationallogicforfurtherprocessingcausesnoendoftiminghazards.Herearetwoexamplesofthistechnique.

Non-RecommendedGatedClocks

Inthelefthandcircuittheintentionwasprobablytoinhibit/enabletheclock.Theensignal,however,arriveslateattheANDgateinputandtheresultisanunwantedglitch.

Intherighthandcircuittheintentionwastoswitchbetweenck1andck2.Thectrlsignaloccurringasitdoesclipsthebeginningofbothclocksresultingintwounwantedglitches.

Figure1.14Non-RecommendedGatedClocks

Therearemanymoreeffectsthatcanoccurdependingonthestateandtimingofthesignalsinvolved.

Furthermoretheinclusionofcombinationalprocessinglogicaddsdelaytotheresultantsignalsresultinginvariableamountsofclockskew.Nowwehaveasituationwherethesequentialelementsinthecircuitarebeingclockedatdifferingtimesrelativetotheinitialmasterclock.

RecommendedGatedClocks

Incircumstanceswhereclockshavetobegatedwithenablesignalstheuseofasequentialelementwithabuilt-inenableinputisrecommended.Ifthisisnotavailablethecircuitoppositeachievesthesamefunctionality.

InthisarrangementthegatingfunctionpreviouslyprovidedbytheANDgateisnowimplementedbythemultiplexor.Thecircuit,however,isnowcompletelysynchronouswiththemasterclockfeedingdirectlyintotheflip-flop.Withtheenablesignalensetlowthecurrentstateoftheflip-flopisretainedonarisingclockedge;withensethighnewdataisloaded.

Figure1.15RecommendedGatedClocks

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1.10

LocalClocks

Aswithresetsitispossibletogenerateasynchronousclocksignalsfromsectionsofsequentiallogicandthesecanviolatetheprinciplesofsynchronousdesign.

Non-RecommendedLocal

Clocks

Acommontechniqueincounterdesignistogenerateaclockfromtheoutputtransitionofanothersequentialelement.Thefollowingripplecounterprovidesanexampleinwhichageneratedclockfromonestageimplementsatogglefunctioninthenext.Thesecondflip-flopisclockedonlywhenthefirstflip-flopchangesfromalogic1toalogic0.

Therearetwoproblemswiththisarrangement.Thegeneratedclocktothesecondflip-flopisskewedbytheclock-to-qpropagationdelayofthefirstflip-flopandalsothesecondflip-flopcannotbeclockedoneveryedgeofthemasterclock.Againthiswillcauseproblemswithtestingmethodologies.

Figure1.16Non-RecommendedLocal

Clocks

RecommendedLocalClocks

Thecircuitbelowprovidestheequivalentfunction.Againthecircuitisfullysynchronous.Whenthetoggleinputislowtheflip-flopretainsitscurrentstate;whenthetoggleinputishightheflip-flopassumesitsoppositestate.

Incounterdesignthetoggleinputcanbeprovidedfromtheqoutputofthepreviousstageflip-flop.

Figure1.17Non-RecommendedLocal

Clocks

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1.11

ClockingStrategies

Whenspeediscriticalinadigitalsystem,designersoftenresorttodubiousclockingstrategiesinanefforttomaximiseperformance.

AnapparentlyattractivetechniqueforincreasingtherateofdatathroughputinacircuitisthatofDoubleEdgedClockinginwhichflip-flopsinacircuitcanbeclockedoneithertherisingorfallingedgeoftheclock.

Non-RecommendedStrategy

Thecircuitbelowshowsafirstflip-flopactivatedbythetrueversionoftheclockwhilstaninverterfeedsasecondflip-flopelsewhereinthecircuitwithaninvertedversion.

Bothdevicesaresensitivetorisingclockedgesbuttheoveralleffectistoclockthefirstflip-flopatthebeginningoftheclockpulseandthesecondattheend.

Figure1.18Non-RecommendedStrategy

Theproblemswithemployingthiskindoftechniquerelatetosynchronousresetting,setupandholdtimeviolations,determinationofcriticalpathsandimplementationoftestmethodologies.Synchronousresetting(ie.whereflip-flopsareresetonthecoincidentoccurrenceofaclockedgeandaresetsignal)isimpossiblesincenotalldevicesareclockedonthesameedge.Setuptimes(ie.thetimebeforeaclockedgethatdatahastobepresent)andholdtimes(ie.thetimeafteraclockedgethatdatahastoremain)areindangerofbeingviolatedastimingbecomesfinelytuned.Criticaldelaypathsthroughthecircuitaredifficulttoassesswithmultipletimingregimespresent.Testmethodologiessuchasscanpathinwhichpatternsareinsertedintoacircuitviaitsflip-flopelementsareimpossibleagainbecauseallflip-flopshavetobeclockedatthesametime.

Ingeneralthistechniquerarelyworkswellinadesign.Attemptsto'borrowtime'inonepartofacircuitoftenresultincomplicationsoccurringsomewhereelse.Abettersolutionistouseasingleedgedclockingschemewithahigherclockfrequency.

Non-RecommendedStrategy

Similarproblemsoccurwhendoubleedgedclockingtechniquesareusedinmoreformaldesignarrangements.Thiscircuitdetailsapipelinedstructureinwhichdatafromafirststoragelevelisprocessedbycombinationallogicforsubsequenttransmissiontoasecondstoragelevel.

Thearrangementsuggestsadesignthatisvery'edgy'.Anyincrease,forexampleinthepropagationdelaysofthecombinationallogic,couldresultincircuitfailure.

Figure1.19Non-RecommendedStrategy

RecommendedStrategy

Againabettersolutionistorevertbacktoasingleedgedclockingschemeasshownopposite.

Thecircuitisclockedattwicethefrequencyofthedoubleedgedversiontoachievethesamethroughput.

Figure1.20RecommendedStrategy

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1.12

DelayCircuits

DigitaldesignersoftenutiliselogiccomponentssuchasinvertersandbufferstoachievesomerequireddelayandassumethatthiscanbedoneonASICs.Examplesincludetheaddingofdelaysincombinationalcircuitrytoequalisepropagationdelaysandremoveglitchesorthedelayingofaclockedgetoaflip-flopinordertoallowmoretimeforthedatainputtosettle.Itisalsotemptingtotryandreproducethefunctionalityofpulsegenerators,monostablesandmultivibratorsonsiliconusingdelayelements.Thesepracticesarenotgenerallyrecommended.ThedelayofanylogiccomponentonanASICcannotbeguaranteed.Itwillvarywithtemperature,powersupplyvoltageanddifferentfabricationruns.Logicsimulatorsenabletheeffectsofthesevariationstobeobservedbyallowingthesimulationtobeimplementedatminimum,typicalandmaximumoperatingconditions.Typicalreferstonominaloperatingtemperatureandpowersupplyvoltage.Minimumwillmultiplyallthecomponentdelaysonthechipbyascalingfactorofaround0.5todefinetheshortestcircuitdelayswhilstmaximumwilluseafactorofaround1.5todefinethelongestdelays.Inthiswaythedesignercantolerancethecircuitovertheentireoperatingrangeofthefabricationprocess.Agooddesignwillbestablethroughout.Abaddesignthatpassedasimulationundertypicalconditionsislikelytofailatthispointwhenthevariabledelaysmovetiminghazardsintocontention.

Non-RecommendedPulseGenerator

ThecircuitbelowusesinverterstoimplementadelayontheInputTriggersignal.Thesettledstatewiththissignalsetlowproducesalogic1onthetopinputtotheANDgate,alogic0onthebottominputandalogic0onthePulseoutput.WhentheInputTriggergoeshighbothinputstotheANDgatewillbemomentarilyhigh,producingalogic1onthePulseoutput.AfteratimeequaltothepropagationdelayofthedelaylinethetopinputoftheANDgatewillgolowandthepulseisterminated.

Themainproblemwiththiscircuitisthatvariationsintheinverterdelayspreviouslydescribedwillaffectthewidthoftheoutputpulseandthiscannotnowbeconsistentlyguara