北科自動化數(shù)電pp6

CHAPTER6FunctionsofCombinationalLogic6-1BasicAdders6-2ParallelBinaryAdders并行二進(jìn)制加法器

6-3Comparators比較器6-4Decoders譯碼器6-5Encoders編碼器6-6CodeConverters代碼轉(zhuǎn)換器

6-7Multiplexers(DataSelectors)數(shù)據(jù)選擇器/多路復(fù)用（MUX）6-8Demultiplexers多路分用器/解雙工器（DEMUX）

6-9ParityGenerator/Checker奇偶校驗(yàn)器IntroductiontoSeveralMSICombinationalCircuits介紹幾種常用的中規(guī)模組件 Inthischapteryoushouldknow:TheinternalfunctionalprincipleofeveryMSIchips(inbrief)ThoseMSIchipsarecombinationalcircuit(thatmeanstheyarecomposedoflogicgates);youshouldlearnhowtousethemFocusonthesetwoblocksnameddecoderanddataselectorwhichcanbeusedtoproducesomegivenlogicfunction6-1BasicAdders

(implementing1-bitaddition)

基本加法器6-1-1Half-Adder半加器6-1-2Full-Adder全加器

6-1-3Fulladderfromtwohalf-addercircuitsGeneralrulesofbinaryaddition：a.Produceacarrybitwheneverwehave2b.LSBaddition:withoutconsideringthecarrybit。c.Whenprocessingtheotherbits,weshouldacceptthreenumbers(twoinputbitsandacarrybit)d.Anytwobitswillproduceasumbitandaoutputcarrywhenbeadded.Half-adderFull-adder6-1-1Half-Adder(半加器)Howcouldweimplementthisfunctionusinglogiccircuit?Ahalf-adderisacombinationallogiccircuitthataddtogethertwoone-bitvaluesandproducesasumandacarryoutput.Thehalfpartofthenamecomesfromthelackofacarryinput.0+0=00+1=11+0=11+1=10ZeropluszeroequalszeroZeroplusoneequalsoneOnepluszeroequalsoneOneplusoneequalszerowithacarryofoneSimpleBinaryAdditionAfull-adderisacombinationallogiccircuitthataddstwoone-bitvaluesplusacarrybitandproducesasumandacarryoutput.Thefullpartofthenamecomesfromthecarryinputbit.6-1-2Full-Adder全加器

TruthtableSketchtheinternallogiccircuitoffull-adderaccordingtothebooleanexpression.6-1-3Fulladderfromtwohalf-addercircuits

6-2ParallelBinaryAdders

(implementingmore-bitaddition)

并行二進(jìn)制加法器

6-2-1Two-bitparallelbinaryadder6-2-2Four-bitparallelbinaryadder

Howcouldan-bitparalleladderbeconstructed?An-bitadderrequiresn-1full-addersandonehalf-adder.Howcouldafull-adderbefunctionedasahalf-adder?6-2-1Two-bitparallelbinaryadderUsingtwofull-adderstoimplementA2A1+B2B1

thepinsofdouble-full-adderSN74LS183114SN74LS1831an1bn1cn-11cn1sn2cn-12cn2sn2an2bnUccGND6-2-2Four-bitparallelbinaryadder

四位并行二進(jìn)制加法器ripplecarry（串行進(jìn)位）addershowing“worst-case”carrypropagationdelays.

CascadingFull-Adders串行全加器Look-AheadCarryadder:超前進(jìn)位加法器：Carrygeneration:CgCarrypropagation:CpP191fourfull-addersoutputequation.4位超前進(jìn)位加法器74LS283內(nèi)部結(jié)構(gòu)Anotherapplicationofadder:Avotingsystem6-3Comparators

數(shù)值比較器Acomparatorsisacombinationallogiccircuitthatcomparestwobinaryinputvaluesandproducesresultsthatspecifytherelativevalueofoneinputwithrespecttotheother.OutputsofsomecomparatorsspecifywhetherA=B,othersmayspecifyA=B,A>BandA<B.Wewillfocusonthesecondcomparators.BinaryComparators二進(jìn)制比較器Functiondescription1-BitComparator&&1ABA<BA>BA=BABA>BA<BA=BLogicdiagramLogicsymbolComparingprinciple：1.先從高位比起，高位大的數(shù)值一定大。2.若高位相等，則再比較低位數(shù)，最終結(jié)果由低位的比較結(jié)果決定。more-BitComparatorTruthtableforfour-bitcomparatora3>b3

100a3=b3a2=b2a1=

b1a0=b0

010a3=b3a2=b2a1=

b1a0<b0

001a3=b3a2=b2a1=

b1a0>b0

100a3=b3a2=b2a1<b1

001

a3=b3a2=b2a1>

b1

100a3=b3a2<b2

001a3=b3a2>b2

100a3<b3

001

input

output

a3b3a2b2a1b1a0b0

LES

(A>B)(A=B)(A<B)根據(jù)比較規(guī)則，可得到四位數(shù)值比較器邏輯式：A=B:A<B:AB:Pindiagramandlogicsymbolforthe74HC854-bitmagnitudecomparator.A=B:A<B:AB:例1：七位二進(jìn)制數(shù)比較器。（采用兩片85）“1”必接好（A>B）L（A<B）LA>BA=BA<BA1B1A0B0A3B3A2B2（A=B）L74LS85（A>B）L（A<B）LA>BA=BA<BA1B1A0B0A3B3A2B2（A=B）L74LS85(1)(2)a3a2a1a0a6a5a4Ab3b2b1b0b6b5b4B高位片低位片6-5Encoders

編碼器EncodersAnencoderisacombinationallogiccircuitthataccepts2n

binaryinputsandproducesndataencodedoutputvalues.An8-to-3encoderhaseightinputlinesandthreeoutputlines.Whenoneofthedatainputsisactive,theoutputcodethatrepresentsthatvalueisgenerated.8-line-to-3-lineencoder（8線-3線編碼器）

2priorityencoder(優(yōu)先編碼器)3Decimal-to-BCDencoder（二－十進(jìn)制編碼器）8-line-to-3-lineencoder設(shè)八個(gè)輸入端為I1I8，八種狀態(tài)，與之對應(yīng)的輸出設(shè)為F1、F2、F3，共三位二進(jìn)制數(shù)。設(shè)計(jì)編碼器的過程與設(shè)計(jì)一般的組合邏輯電路相同，首先要列出狀態(tài)表（即真值表），然后寫出邏輯表達(dá)式并進(jìn)行化簡，最后畫出邏輯圖。Truthtable(active-lowinput)I1I2I3I4I5I6I7I8&&&F3F2F1LogicdiagramPriorityencoder(優(yōu)先編碼器)Logicdiagramof74LS148選通輸入端選通輸出端擴(kuò)展端Functiondescription1XXXXXXXX11111

01111111111101

0XXXXXXX0

00010

0XXXXXX01

00110

0XXXXX011

01010…………

001111111

11110Functiontableof74LS148Example:用兩片74LS148接成16線－4線優(yōu)先編碼器二十進(jìn)制編碼器的作用：將十個(gè)狀態(tài)（對應(yīng)于十進(jìn)制的十個(gè)代碼）編制成BCD碼。十個(gè)輸入需要幾位輸出？四位輸入：I0I9輸出：F4

F1Decimal-to-BCDencoderLogicsymbolforadecimal-to-BCDencoder.

TruthtableActive-lowinputPindiagramandlogicsymbolforthe74HC147decimal-to-BCDpriorityencoder(HPRImeanshighestvalueinputhaspriority).

Application:Asimplifiedkeyboardencoder.

Assignments:(duetonextMonday)P2326、8、12補(bǔ)充作業(yè)題：用4片74LS148組成32線－5線優(yōu)先編碼器，允許附加必要的門電路。6-4Decoders

譯碼器6-4-1Binarydecoder（二進(jìn)制譯碼器）6-4-2BCD-to-decimaldecoder（BCD碼-十進(jìn)制譯碼器）6-4-3BCD-to-7-segementdecoder（BCD碼-七段顯示驅(qū)動譯碼器）6-4-1Binarydecoder二進(jìn)制譯碼器的作用：將n種輸入的組合譯成2n種電路狀態(tài)。也叫n2n線譯碼器。譯碼器的輸入——一組二進(jìn)制代碼譯碼器的輸出——一組高低電平信號Binaryinputs

Active-lowoutputs4-line-to-16-linedecoderWhatdoyoufigureoutfromtheabovetruthtable?n-2n

線譯碼器，包含了n變量所有的最小項(xiàng)。加上或門或與非門，可以組成任何形式的輸入變量小于n的組合邏輯函數(shù)。若要產(chǎn)生多輸出邏輯函數(shù)時(shí),使用譯碼器+門電路較有利。tip例：用2-4線譯碼器產(chǎn)生一組多輸出函數(shù)。接線圖11Z2Z1練習(xí)題：用74LS138譯碼器和門電路產(chǎn)生如下多輸出邏輯函數(shù)。3-line-to-8-line74LS138decoder譯碼器的多片擴(kuò)展利用譯碼器的使能控制端可以將多片n-2n線譯碼器組成（n+1）-2（n+1）線譯碼器或更大的譯碼器。例：用兩片74LS138接成4線－16線譯碼器6-4-2BCD-to-decimaldecoder二十進(jìn)制編碼顯示譯碼器顯示器件在數(shù)字系統(tǒng)中，常常需要將運(yùn)算結(jié)果用人們習(xí)慣的十進(jìn)制顯示出來，這就要用到專門的顯示譯碼器。顯示器件：常用的是七段顯示器件。6-4-3BCD-to-7-segementdecoderLED:light-emittingdiode發(fā)光二極管LCD:liquidcrystaldisplay液晶顯示器Arrangementsof7-segmentLEDdisplays.

abcdfgabcdefg111111001100001101101e七段顯示器件的工作原理：Step1.The1saremappeddirectlyfromtheabovetable.Step2.Allofthe“don’tcare”areplacedonthemap.Step3.The1saregroupedasshownP144figure4-46MinimumSOPlogicexpressionforthesegment-a.顯示譯碼器：11474LS49BCBIDAeabcdfgUccGND74LS49的管腳圖消隱控制端74LS49的功能表（簡表）輸入輸出顯示DABIag10XXXX0000000消隱8421碼譯碼顯示字型74LS49與七段顯示器件的連接：74LS49是集電極開路，必須接上拉電阻bfacdegbfacdegBIDCBA+5V+5V關(guān)于OC門的介紹：/shudian/netpages/dig2_2.htm6-8Multiplexers(DataSelectors)

多路復(fù)用器/數(shù)據(jù)選擇器（MUX）AMUXisadevicethatallowsdigitalinformationfromseveralsourcestoberoutedontoasinglelinefortransmissionoverthatlinetoacommondestination.Thebasicmultiplexerhasseveraldata-inputlinesandasingleoutputline.從一組數(shù)據(jù)中選擇一路信號進(jìn)行傳輸?shù)碾娐?，稱為數(shù)據(jù)選擇器。6-7-14-inputmultiplexer6-7-2Expandedmultiplexers6-7-3Multiplexerasalogicfunctiongenerator控制信號輸入信號輸出信號數(shù)據(jù)選擇器類似一個(gè)多路開關(guān)。選擇哪一路信號由相應(yīng)的一組控制信號控制。A0A1D3D2D1D0W6-7-14-inputmultiplexer4-inputmultiplexerWaveform

雙4選1數(shù)據(jù)選擇器74LS153功能表控制端：為或，低電平有效。選擇端A1A0

：為兩個(gè)4選1數(shù)據(jù)選擇器共用。其中例：用一片74LS153組成8選1:A2=0:(1)工作；A2=1:(2)工作。D1D7D0D2D3D4D5D6Y1D01D11D21D32D02D12D22D374LS153(1)(2)BAA2(低位）(高位）A0A1選擇信號（三位）16-7-2Expandedmultiple