第7章 數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例

第7章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例7.1半整數(shù)分頻器的設(shè)計(jì)7.2音樂發(fā)生器7.32FSK/2PSK信號(hào)產(chǎn)生器7.4實(shí)用多功能電子表7.5交通燈控制器7.6數(shù)字頻率計(jì)習(xí)題

7.1半整數(shù)分頻器的設(shè)計(jì)在數(shù)字系統(tǒng)設(shè)計(jì)中，分頻器是一種基本電路。分頻器的實(shí)現(xiàn)非常簡(jiǎn)單，可采用標(biāo)準(zhǔn)的計(jì)數(shù)器，也可采用可編程邏輯器件來實(shí)現(xiàn)一個(gè)整數(shù)分頻器。分頻器通常用來對(duì)某個(gè)給定頻率進(jìn)行分頻，得到所需的頻率。在某些場(chǎng)合下，用戶所需要的頻率與頻率時(shí)鐘源不是整數(shù)倍關(guān)系，此時(shí)可采用小數(shù)分頻器進(jìn)行分頻。7.1.1小數(shù)分頻的基本原理設(shè)有一個(gè)5MHz的時(shí)鐘源，但電路中需要產(chǎn)生一個(gè)2MHz的時(shí)鐘信號(hào)，由于分頻比為2.5，因此整數(shù)分頻器將不能勝任。采用可編程邏輯器件實(shí)現(xiàn)分頻系數(shù)為2.5的分頻器，可采用以下方法：設(shè)計(jì)一個(gè)模3的計(jì)數(shù)器，再設(shè)計(jì)一個(gè)扣除脈沖電路，加在模3計(jì)數(shù)器輸出之后，每來兩個(gè)脈沖就扣除一個(gè)脈沖(實(shí)際上是使被扣除的脈沖變成很窄的脈沖，可由異或門實(shí)現(xiàn))，就可以得到分頻系數(shù)為2.5的小數(shù)分頻器。采用類似方法，可以設(shè)計(jì)分頻系數(shù)為任意半整數(shù)的分頻器。小數(shù)分頻的基本原理為脈沖吞吐計(jì)數(shù)法：設(shè)計(jì)兩個(gè)不同分頻比的整數(shù)分頻器，通過控制單位時(shí)間內(nèi)兩種分頻比出現(xiàn)的不同次數(shù)，從而獲得所需的小數(shù)分頻值。例如設(shè)計(jì)一個(gè)分頻系數(shù)為10.1的分頻器，可以將分頻器設(shè)計(jì)成9次10分頻，1次11分頻，這樣總的分頻值為(9×10+1×11)/(9+1)=10.1

從這種實(shí)現(xiàn)方法的特點(diǎn)可以看出，由于分頻器的分頻值在不斷改變，因此分頻后得到的信號(hào)抖動(dòng)較大。當(dāng)分頻系數(shù)為N-0.5(N為整數(shù))時(shí)，可控制扣除脈沖的時(shí)間，使輸出為一個(gè)穩(wěn)定的脈沖頻率，而不是一次N分頻，一次N-1分頻。7.1.2電路組成設(shè)需要設(shè)計(jì)一個(gè)分頻系數(shù)為N-0.5的分頻器，其電路可由一個(gè)模N計(jì)數(shù)器、一個(gè)二分頻器和一個(gè)異或門組成，如圖7-1所示。在實(shí)現(xiàn)時(shí)，模N計(jì)數(shù)器可設(shè)計(jì)成帶預(yù)置的計(jì)數(shù)器，這樣就可以實(shí)現(xiàn)任意分頻系數(shù)為N-0.5的分頻器。

圖7-1通用半整數(shù)分頻器7.1.3VHDL程序LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYdeccountISPORT(inclk:INSTD_LOGIC; --時(shí)鐘源

preset:INSTD_LOGIC_VECTOR(3DOWNTO0);

--預(yù)置分頻值Noutclk1:OUTSTD_LOGIC;outclk2:BUFFERSTD_LOGIC --輸出時(shí)鐘);ENDdeccount;

ARCHITECTUREdeccount_archOFdeccountISSIGNALclk,divide2:STD_LOGIC;SIGNALcount:STD_LOGIC_VECTOR(3DOWNTO0);BEGINclk<=inclkXORdivide2; --inclk與divide2異或后作為模N計(jì)數(shù)器的時(shí)鐘outclk1<=inclk;PROCESS(clk)BEGINIF(clk'eventANDclk='1')THENIF(count="0000")THEN

count<=preset-1; --置整數(shù)分頻值Noutclk2<='1';ELSEcount<=count-1; --模N計(jì)數(shù)器減法計(jì)數(shù)

outclk2<='0';ENDIF;ENDIF;ENDPROCESS;

PROCESS(outclk2)BEGINIF(outclk2'eventANDoutclk2='1')THENdivide2<=NOTdivide2; --輸出時(shí)鐘二分頻

ENDIF;ENDPROCESS;ENDdeccount_arch;圖7-2半整數(shù)分頻器外部接口以上程序?qū)崿F(xiàn)對(duì)時(shí)鐘源inclk進(jìn)行分頻系數(shù)為N-0.5的分頻，得到輸出頻率outclk2。preset輸入端口是預(yù)置分頻值N，本例中preset設(shè)為4位寬的位矢量，也即分頻系數(shù)為16以內(nèi)的半整數(shù)值。若分頻系數(shù)大于16，需同時(shí)增大preset和count的位寬，兩者的位寬則要求始終一致。本設(shè)計(jì)的外部接口如圖7-2所示，程序中設(shè)置outclk1是為了方便觀察輸入信號(hào)的波形,以與輸出信號(hào)outclk2比較。7.1.4仿真結(jié)果上述半整數(shù)分頻器的仿真波形如圖7-3所示。圖7-3半整數(shù)分頻器仿真波形圖7.1.5下載驗(yàn)證鎖定引腳時(shí)將inclk連至CLK1，preset連至K0～K3，outclk1連至TESTOUT1(測(cè)試1腳)，outclk2連至TESTOUT2(測(cè)試2腳)，綜合適配后將配置數(shù)據(jù)下載入EDA實(shí)驗(yàn)平臺(tái)(技術(shù)資料詳見附錄)的FPGA中(有關(guān)CLK1等引腳在FPGA芯片引腳中的序號(hào),請(qǐng)參見附錄的附圖1)，通過改變K0～K3狀態(tài)觀察測(cè)試1腳和測(cè)試2腳上的波形，測(cè)試結(jié)果與仿真結(jié)果一致。7.2音樂發(fā)生器本設(shè)計(jì)利用可編程邏輯器件配以一個(gè)小揚(yáng)聲器設(shè)計(jì)了一個(gè)音樂發(fā)生器，其結(jié)構(gòu)如圖7-4所示。本例產(chǎn)生的音樂選自“梁?！逼?。圖7-4音樂產(chǎn)生器原理框圖7.2.1音名與頻率的關(guān)系音樂的十二平均率規(guī)定：每?jī)蓚€(gè)八度音(如簡(jiǎn)譜中的中音1與高音1)之間的頻率相差一倍。在兩個(gè)八度音之間，又可分為十二個(gè)半音，每?jī)蓚€(gè)半音的頻率比為。另外，音名A(簡(jiǎn)譜中的低音6)的頻率為440Hz，音名B到C之間、E到F之間為半音，其余為全音。由此可以計(jì)算出簡(jiǎn)譜中從低音1至高音1之間每個(gè)音名的頻率如表7-1所示。表7-1簡(jiǎn)譜中的音名與頻率的關(guān)系音名頻率/Hz音名頻率/Hz音名頻率/Hz低音1261.63中音1523.25高音11046.50低音2293.67中音2587.33高音21174.66低音3329.63中音3659.25高音31318.51低音4349.23中音4698.46高音41396.92低音5391.99中音5783.99高音51567.98低音6440中音6880高音61760低音7493.88中音7987.76高音71975.52由于音階頻率多為非整數(shù)，而分頻系數(shù)又不能為小數(shù)，故必須將計(jì)算得到的分頻數(shù)四舍五入取整。若基準(zhǔn)頻率過低，則由于分頻系數(shù)過小，四舍五入取整后的誤差較大。若基準(zhǔn)頻率過高，雖然誤碼差變小，但分頻結(jié)構(gòu)將變大。實(shí)際的設(shè)計(jì)應(yīng)綜合考慮兩方面的因素，在盡量減小頻率誤差的前提下取合適的基準(zhǔn)頻率。本例中選取4MHz的基準(zhǔn)頻率。若無4MHz的時(shí)鐘頻率，則可以先分頻得到4MHz或換一個(gè)新的基準(zhǔn)頻率。實(shí)際上，只要各個(gè)音名間的相對(duì)頻率關(guān)系不變，C作1與D作1演奏出的音樂聽起來都不會(huì)“走調(diào)”。本例需要演奏的是“梁?！逼?，此片段內(nèi)各音階頻率及相應(yīng)的分頻比如表7-2所示。為了減小輸出的偶次諧波分量，最后輸出到揚(yáng)聲器的波形應(yīng)為對(duì)稱方波，因此在到達(dá)揚(yáng)聲器之前，有一個(gè)二分頻的分頻器。表7-2中的分頻比就是從4MHz頻率二分頻得到的2MHz頻率基礎(chǔ)上計(jì)算得出的。表7-2各音階頻率對(duì)應(yīng)的分頻值音名分頻系數(shù)初始值音名分頻系數(shù)初始值低音360672124中音234054786低音551023089中音330345157低音645453646中音525515640低音740504141中音622735918中音138224369高音119116280由于最大的分頻系數(shù)為6067，故采用13位二進(jìn)制計(jì)數(shù)器已能滿足分頻要求。在表7-2中，除給出了分頻比以外，還給出了對(duì)應(yīng)于各個(gè)音階頻率時(shí)計(jì)數(shù)器不同的初始值。對(duì)于不同的分頻系數(shù)，只要加載不同的初始值即可。采用加載初始值而不是將分頻輸出譯碼反饋，可以有效地減少本設(shè)計(jì)占用可編程邏輯器件的資源，這也是同步計(jì)數(shù)器的一個(gè)常用設(shè)計(jì)技巧。對(duì)于樂曲中的休止符，只要將分頻系數(shù)設(shè)為0，即初始值為213-1=8191即可，此時(shí)揚(yáng)聲器將不會(huì)發(fā)聲。7.2.2音長的控制本例演奏的“梁?！逼?，最小的節(jié)拍為1/4拍。將1拍的時(shí)長定為1秒，則只需要再提供一個(gè)4Hz的時(shí)鐘頻率即可產(chǎn)生1/4拍的時(shí)長。演奏的時(shí)間控制通過記譜來完成，對(duì)于占用時(shí)間較長的節(jié)拍(一定是1/4拍的整數(shù)倍)，如2/4拍，只需將該音名連續(xù)記錄兩次即可。本例要求演奏時(shí)能循環(huán)進(jìn)行，因此需另外設(shè)置一個(gè)時(shí)長計(jì)數(shù)器，當(dāng)樂曲演奏完成時(shí)，保證能自動(dòng)從頭開始演奏。7.2.3演奏時(shí)音名的動(dòng)態(tài)顯示如果有必要，可以通過一個(gè)數(shù)碼管或LED來顯示樂曲演奏時(shí)對(duì)應(yīng)的音符。如用三個(gè)數(shù)碼管，分別顯示本例中的高、中、低音名，就可實(shí)現(xiàn)演奏的動(dòng)態(tài)顯示，且十分直觀。本設(shè)計(jì)通過三個(gè)數(shù)碼管來動(dòng)態(tài)顯示演奏時(shí)的音名，其中HIGH顯示為高音區(qū)音階(僅高音1)，MED[2..0]顯示的是中音區(qū)音階(中音6,5,3,2,1)，LOW[2..0]顯示的是低音區(qū)音階(低音7,6,5,3)。數(shù)碼管顯示的七段譯碼電路在此不作專門討論。需要說明的是，七段譯碼電路輸入為4位，而將HIGH、MED、LOW用作輸入時(shí)，不足4位的高位均為低電平“0”。圖7-5音樂產(chǎn)生器外部接口7.2.4VHDL程序本設(shè)計(jì)的外部接口如圖7-5所示，程序中定義了一個(gè)5位寬的zero[4..0]，這是由于實(shí)驗(yàn)平臺(tái)上連向數(shù)碼管的引腳在不賦值的情況下為高電平，這將導(dǎo)致顯示音名錯(cuò)誤，設(shè)置zero[4..0]就是要將沒用到的引腳(高音的高3位、中音的高1位和低音的高1位)賦一個(gè)低電平，從而避免顯示錯(cuò)誤。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYsongISPORT(clk_4MHz,clk_4Hz:INSTD_LOGIC; --預(yù)置計(jì)數(shù)器和樂譜產(chǎn)生器的時(shí)鐘

digit:BUFFERSTD_LOGIC_VECTOR(6DOWNTO0);

--高、中、低音數(shù)碼管指示

zero:OUTSTD_LOGIC_VECTOR(4DOWNTO0);

--用于數(shù)碼管高位置低

speaker:outSTD_LOGIC

--揚(yáng)聲器);ENDsong;ARCHITECTUREsong_archOFsongISSIGNALdivider,origin:STD_LOGIC_VECTOR(12DOWNTO0); --13位計(jì)數(shù)值和預(yù)置值SIGNALcounter:integerrange0to140; --7位計(jì)數(shù)器SIGNALcount:STD_LOGIC_VECTOR(1DOWNTO0); --記錄1/4拍SIGNALcarrier:STD_LOGIC;BEGINzero<="00000";PROCESS(clk_4MHz)BEGINIF(clk_4MHz'eventANDclk_4MHz='1')THENIF(divider="1111111111111")THENcarrier<='1';divider<=origin;ELSEdivider<=divider+'1';carrier<='0';ENDIF;ENDIF;ENDPROCESS;PROCESS(carrier)BEGINIF(carrier'eventANDcarrier='1')THENcount<=count+'1'; --輸出時(shí)鐘四分頻

IFcount="00"THENspeaker<='1';ELSEspeaker<='0';ENDIF;ENDIF;ENDPROCESS;PROCESS(clk_4Hz)BEGINIF(clk_4Hz'eventANDclk_4Hz='1')THENIF(counter=140)THENcounter<=0;ELSEcounter<=counter+1;ENDIF;ENDIF;CASEcounterISWHEN0=>digit<="0000011"; WHEN1=>digit<="0000011"; WHEN2=>digit<="0000011"; WHEN3=>digit<="0000011"; WHEN4=>digit<="0000101"; WHEN5=>digit<="0000101"; WHEN6=>digit<="0000101"; WHEN7=>digit<="0000110"; WHEN8=>digit<="0001000"; WHEN9=>digit<="0001000"; WHEN10=>digit<="0001000"; WHEN11=>digit<="0010000"; WHEN12=>digit<="0000110"; WHEN13=>digit<="0001000";WHEN14=>digit<="0000101"; WHEN15=>digit<="0000101"; WHEN16=>digit<="0101000"; WHEN17=>digit<="0101000"; WHEN18=>digit<="0101000"; WHEN19=>digit<="1000000"; WHEN20=>digit<="0110000"; WHEN21=>digit<="0101000";

WHEN22=>digit<="0011000"; WHEN23=>digit<="0101000"; WHEN24=>digit<="0010000"; WHEN25=>digit<="0010000"; WHEN26=>digit<="0010000"; WHEN27=>digit<="0010000"; WHEN28=>digit<="0010000"; WHEN29=>digit<="0010000"; WHEN30=>digit<="0010000"; WHEN31=>digit<="0000000"; WHEN32=>digit<="0010000"; WHEN33=>digit<="0010000"; WHEN34=>digit<="0010000"; WHEN35=>digit<="0011000"; WHEN36=>digit<="0000111"; WHEN37=>digit<="0000111"; WHEN38=>digit<="0000110"; WHEN39=>digit<="0000110"; WHEN40=>digit<="0000101"; WHEN41=>digit<="0000101"; WHEN42=>digit<="0000101"; WHEN43=>digit<="0000110";WHEN44=>digit<="0001000"; WHEN45=>digit<="0001000"; WHEN46=>digit<="0010000"; WHEN47=>digit<="0010000"; WHEN48=>digit<="0000011"; WHEN49=>digit<="0000011"; WHEN50=>digit<="0001000"; WHEN51=>digit<="0001000"; WHEN52=>digit<="0000110"; WHEN53=>digit<="0000101"; WHEN54=>digit<="0000110"; WHEN55=>digit<="0001000"; WHEN56=>digit<="0000101"; WHEN57=>digit<="0000101"; WHEN58=>digit<="0000101"; WHEN59=>digit<="0000101"; WHEN60=>digit<="0000101"; WHEN61=>digit<="0000101"; WHEN62=>digit<="0000101"; WHEN63=>digit<="0000101";WHEN64=>digit<="0011000"; WHEN65=>digit<="0011000"; WHEN66=>digit<="0011000"; WHEN67=>digit<="0101000"; WHEN68=>digit<="0000111"; WHEN69=>digit<="0000111"; WHEN70=>digit<="0010000"; WHEN71=>digit<="0010000";WHEN72=>digit<="0000110"; WHEN73=>digit<="0001000";

WHEN74=>digit<="0000101";

WHEN75=>digit<="0000101"; WHEN76=>digit<="0000101"; WHEN77=>digit<="0000101"; WHEN78=>digit<="0000101"; WHEN79=>digit<="0000101"; WHEN80=>digit<="0000011"; WHEN81=>digit<="0000101"; WHEN82=>digit<="0000011"; WHEN83=>digit<="0000011"; WHEN84=>digit<="0000101"; WHEN85=>digit<="0000110"; WHEN86=>digit<="0000111"; WHEN87=>digit<="0010000"; WHEN88=>digit<="0000110"; WHEN89=>digit<="0000110"; WHEN90=>digit<="0000110"; WHEN91=>digit<="0000110"; WHEN92=>digit<="0000110"; WHEN93=>digit<="0000110"; WHEN94=>digit<="0000101"; WHEN95=>digit<="0000110"; WHEN96=>digit<="0001000"; WHEN97=>digit<="0001000"; WHEN98=>digit<="0001000"; WHEN99=>digit<="0010000";

WHEN100=>digit<="0101000"; WHEN101=>digit<="0101000"; WHEN102=>digit<="0101000"; WHEN103=>digit<="0011000"; WHEN104=>digit<="0010000"; WHEN105=>digit<="0010000"; WHEN106=>digit<="0011000"; WHEN107=>digit<="0010000"; WHEN108=>digit<="0001000"; WHEN109=>digit<="0001000"; WHEN110=>digit<="0000110"; WHEN111=>digit<="0000101"; WHEN112=>digit<="0000011"; WHEN113=>digit<="0000011"; WHEN114=>digit<="0000011"; WHEN115=>digit<="0000011"; WHEN116=>digit<="0001000"; WHEN117=>digit<="0001000"; WHEN118=>digit<="0001000"; WHEN119=>digit<="0001000"; WHEN120=>digit<="0000110"; WHEN121=>digit<="0001000"; WHEN122=>digit<="0000110"; WHEN123=>digit<="0000101"; WHEN124=>digit<="0000011"; WHEN125=>digit<="0000101";WHEN126=>digit<="0000110"; WHEN127=>digit<="0001000"; WHEN128=>digit<="0000101"; WHEN129=>digit<="0000101"; WHEN130=>digit<="0000101"; WHEN131=>digit<="0000101"; WHEN132=>digit<="0000101"; WHEN133=>digit<="0000101"; WHEN134=>digit<="0000101"; WHEN135=>digit<="0000101"; WHEN136=>digit<="0000000"; WHEN137=>digit<="0000000"; WHEN138=>digit<="0000000"; WHEN139=>digit<="0000000"; WHENothers=>digit<="0000000";ENDCASE;CASEdigitIS

WHEN"0000011"=>origin<="0100001001100"; --2124WHEN"0000101"=>origin<="0110000010001"; --3089WHEN"0000110"=>origin<="0111000111110"; --3646WHEN"0000111"=>origin<="1000000101101"; --4141WHEN"0001000"=>origin<="1000100010001"; --4369WHEN"0010000"=>origin<="1001010110010";

--4786WHEN"0011000"=>origin<="1010000100101"; --5157WHEN"0101000"=>origin<="1011000001000"; --5640WHEN"0110000"=>origin<="1011100011110"; --5918WHEN"1000000"=>origin<="1100010001000"; --6280WHENothers=>origin<="1111111111111"; --8191

ENDCASE;ENDPROCESS;ENDsong_arch;7.2.5仿真結(jié)果音樂發(fā)生器的仿真波形如圖7-6所示。圖7-6音樂發(fā)生器仿真波形圖7.2.6下載驗(yàn)證鎖定引腳時(shí)將clk_4MHz和clk_4Hz分別連至CLK1和CLK2，speaker接揚(yáng)聲器，zero[4..2]、digit[6]接一個(gè)數(shù)碼管，zero[1]、digit[5..3]接一個(gè)數(shù)碼管，zero[0]、digit[2..0]接另一個(gè)數(shù)碼管。綜合適配后將配置數(shù)據(jù)下載入EDA實(shí)驗(yàn)平臺(tái)(技術(shù)資料詳見附錄)的FPGA中(有關(guān)CLK1等引腳在FPGA芯片引腳中的序號(hào)，請(qǐng)參見附錄的附圖1)，揚(yáng)聲器短接線短路(接入揚(yáng)聲器)，即可聽到MIDI音樂。7.32FSK/2PSK信號(hào)產(chǎn)生器7.3.12FSK基本原理在通信領(lǐng)域中，為了傳送信息，一般都將原始的信號(hào)進(jìn)行某種變換變成適合于通信傳輸?shù)男盘?hào)形式。在數(shù)字通信系統(tǒng)中，一般將原始信號(hào)(圖像、聲音等)經(jīng)過量化編碼變成二進(jìn)制碼流，稱為基帶信號(hào)。但數(shù)字基帶信號(hào)一般不適合于直接傳輸。例如，通過公共電話網(wǎng)絡(luò)傳輸數(shù)字信號(hào)時(shí)，由于電話網(wǎng)絡(luò)的帶寬為4kHz以下，因此數(shù)字信號(hào)不能直接在其上傳輸。此時(shí)可將數(shù)字信號(hào)進(jìn)行調(diào)制，F(xiàn)SK即為一種常用的數(shù)字調(diào)制方式，由FSK調(diào)制的波形如圖7-7示。

FSK又稱移頻鍵控,它利用載頻頻率的變化來傳遞數(shù)字信息。數(shù)字調(diào)頻信號(hào)可以分為相位離散和相位連續(xù)兩種。若兩個(gè)載頻由不同的獨(dú)立振蕩器提供，它們之間相位互不相關(guān)，就稱相位離散的數(shù)字調(diào)頻信號(hào)；若兩個(gè)頻率由同一振蕩信號(hào)源提供，只是對(duì)其中一個(gè)載頻進(jìn)行分頻，這樣產(chǎn)生的兩個(gè)載頻就是相位連續(xù)的數(shù)字調(diào)頻信號(hào)。圖7-7FSK調(diào)制的波形7.3.22FSK信號(hào)產(chǎn)生器由于FSK為模擬信號(hào)，而FPGA只能產(chǎn)生數(shù)字信號(hào)，因此需對(duì)正弦信號(hào)采樣并經(jīng)模數(shù)變換來得到所需的FSK信號(hào)。本例由FPGA產(chǎn)生正弦信號(hào)的采樣值。FSK信號(hào)發(fā)生器框圖如圖7-8所示，整個(gè)系統(tǒng)共分為分頻器、m序列產(chǎn)生器、跳變檢測(cè)、2:1數(shù)據(jù)選擇器、正弦波信號(hào)產(chǎn)生器和DAC數(shù)模變換器等6部分，其中前5部分由FPGA器件完成。圖7-8FSK調(diào)制信號(hào)發(fā)生器框圖1．分頻器本實(shí)例中數(shù)據(jù)速率為1.2kHz，要求產(chǎn)生1.2kHz和2.4kHz兩個(gè)正弦信號(hào)。對(duì)正弦信號(hào)每周期取100個(gè)采樣點(diǎn)，因此要求能產(chǎn)生3個(gè)時(shí)鐘信號(hào)：1.2kHz(數(shù)據(jù)速率)、120kHz(產(chǎn)生1.2kHz正弦信號(hào)的輸入時(shí)鐘)和240kHz(產(chǎn)生2.4kHz正弦信號(hào)的輸入時(shí)鐘)?；鶞?zhǔn)時(shí)鐘由一個(gè)12MHz的晶振提供。設(shè)計(jì)中要求一個(gè)50分頻(產(chǎn)生240kHz信號(hào))，再2分頻(產(chǎn)生120kHz信號(hào))和100分頻(產(chǎn)生1.2kHz信號(hào))，共有三個(gè)分頻值。

2．m序列產(chǎn)生器

m序列是偽隨機(jī)序列的一種，它的顯著特點(diǎn)是：隨機(jī)特性，預(yù)先可確定性，循環(huán)特性。正因?yàn)檫@些特性，使得m序列產(chǎn)生器在通信領(lǐng)域得到了廣泛的應(yīng)用。本例用一種帶有兩個(gè)反饋抽頭的3級(jí)反饋移位寄存器，得到一串“1110010”循環(huán)序列，并采取措施防止進(jìn)入全“0”狀態(tài)。通過更換時(shí)鐘頻率可以方便地改變輸入碼元的速率。m序列產(chǎn)生器的電路結(jié)構(gòu)如圖7-9所示。圖7-9m序列產(chǎn)生器電路結(jié)構(gòu)3．跳變檢測(cè)將跳變檢測(cè)引入正弦波的產(chǎn)生中，可以使每次基帶碼元上升沿或下降沿到來時(shí)，對(duì)應(yīng)輸出波形位于正弦波形的sin0處。引入跳變檢測(cè)主要是為了便于觀察，確保示波器上顯示為一個(gè)連續(xù)的波形?；鶐盘?hào)的跳變檢測(cè)可以有很多方法，圖7-10為一種便于在可編程邏輯器件中實(shí)現(xiàn)的方案。圖7-10信號(hào)跳變檢測(cè)電路4．2:1數(shù)據(jù)選擇器2:1數(shù)據(jù)選擇器用于選擇正弦波產(chǎn)生器的兩個(gè)輸入時(shí)鐘。一個(gè)時(shí)鐘的頻率為120kHz，此時(shí)正弦波產(chǎn)生器產(chǎn)生一個(gè)1.2kHz的正弦波，代表數(shù)字信號(hào)“0”；另一個(gè)時(shí)鐘的頻率為240kHz，此時(shí)產(chǎn)生一個(gè)2.4kHz的正弦波信號(hào)，代表數(shù)字信號(hào)“1”。5．正弦信號(hào)的產(chǎn)生用數(shù)字電路和DAC變換器可以產(chǎn)生要求的模擬信號(hào)。根據(jù)抽樣定理可知，當(dāng)用模擬信號(hào)最大頻率兩倍以上的速率對(duì)該模擬信號(hào)采樣時(shí)，便可將原模擬信號(hào)不失真地恢復(fù)出來。本例要求得到的是兩個(gè)不同頻率的正弦信號(hào)，實(shí)驗(yàn)中對(duì)正弦波每個(gè)周期采樣100個(gè)點(diǎn)，即采樣速率為原正弦信號(hào)頻率的100倍，因此完全可以在接收端將原正弦信號(hào)不失真地恢復(fù)出來，從而可以在接收端對(duì)FSK信號(hào)正確地解調(diào)。經(jīng)DAC轉(zhuǎn)換后，可以在示波器上觀察到比較理想的波形。本實(shí)驗(yàn)中每個(gè)采樣點(diǎn)采用8位量化編碼，即8位分辨率。采樣點(diǎn)的個(gè)數(shù)與分辨率的大小主要取決于CPLD/FPGA器件的容量，其中分辨率的高低還與DAC的位數(shù)有關(guān)。實(shí)驗(yàn)表明，采用8位分辨率和每周期100個(gè)采樣點(diǎn)可以達(dá)到相當(dāng)不錯(cuò)的效果。具體的正弦信號(hào)產(chǎn)生器可以用狀態(tài)機(jī)來實(shí)現(xiàn)。按前面的設(shè)計(jì)思路，本實(shí)現(xiàn)方案共需100個(gè)狀態(tài)，分別為s1～s100。同時(shí)設(shè)計(jì)一個(gè)異步復(fù)位端，保證當(dāng)每個(gè)“1”或“0”到來時(shí)其調(diào)制信號(hào)正好位于坐標(biāo)原點(diǎn)，即sin0處。狀態(tài)機(jī)共有8位輸出(Q7～Q0)，經(jīng)DAC變換為模擬信號(hào)輸出。為得到一個(gè)純正弦波形，應(yīng)在DAC的輸出端加上一個(gè)低通濾波器，由于本例僅觀察FSK信號(hào)，因此省去了低通濾波器。本設(shè)計(jì)中，數(shù)字基帶信號(hào)與FSK調(diào)制信號(hào)的對(duì)應(yīng)關(guān)系為“0”對(duì)應(yīng)1.2kHz，“1”對(duì)應(yīng)2.4kHz，此二載波的頻率可以方便地通過軟件修改。圖7-112FSK/2PSK信號(hào)產(chǎn)生器外部接口7.3.32FSK/2PSK信號(hào)產(chǎn)生器在2FSK的基礎(chǔ)上，可以較容易地設(shè)計(jì)出2PSK信號(hào)產(chǎn)生器，其接口如圖7-11所示。在檢測(cè)到基帶碼元的上升沿或下降沿時(shí)，使輸出波形位于sinπ處，即可使波形倒相，產(chǎn)生2PSK信號(hào)。在設(shè)計(jì)的最后，應(yīng)考慮選用DAC器件將波形數(shù)據(jù)轉(zhuǎn)換為模擬波形輸出。本實(shí)驗(yàn)箱上選用8位并行DAC器件TLC7528，將8位數(shù)據(jù)輸出連至DAC器件的8位數(shù)據(jù)輸入端，即可觀察到產(chǎn)生的2FSK/2PSK波形。為了觀察波形的方便，我們將TLC7528連接成電壓輸出的方式(器件本身是電流輸出方式)，后面跟一個(gè)射隨器以增強(qiáng)帶載能力。7.3.42FSK信號(hào)產(chǎn)生器的VHDL程序LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYfskISPORT(clock:INSTD_LOGIC; --正弦波發(fā)生器時(shí)鐘

dout:OUTSTD_LOGIC_VECTOR(7DOWNTO0); --并行數(shù)據(jù)DATAcode:BUFFERSTD_LOGIC --輸出m序列);

ENDfsk;ARCHITECTUREfsk_archOFfskISSIGNALcount100:STD_LOGIC_VECTOR(6DOWNTO0);--記錄100個(gè)狀態(tài)SIGNALcount50:STD_LOGIC_VECTOR(5DOWNTO0);SIGNALsinclk1:STD_LOGIC;SIGNALsinclk,coderate:STD_LOGIC;SIGNALtemp,jump_high:STD_LOGIC;SIGNALm:STD_LOGIC_VECTOR(2DOWNTO0); --m序列BEGINPROCESS(clock)BEGINIF(clock'eventANDclock='1')THEN --產(chǎn)生FSK所需的另一個(gè)頻率sinclk1=clock/2sinclk1<=NOTsinclk1;ENDIF;ENDPROCESS;PROCESS(sinclk1) ---sinclk1100分頻得到coderate碼元速率BEGINIF(sinclk1'eventANDsinclk1='1')THENIF(count50="110001")THENcount50<="000000";coderate<=NOTcoderate;ELSEcount50<=count50+'1';ENDIF;ENDIF;ENDPROCESS;m_sequence_form: --產(chǎn)生"1110010"m序列PROCESS(coderate)BEGINIF(coderate'eventANDcoderate='1')THENm(0)<=m(1);m(1)<=m(2);ENDIF;ENDPROCESS;PROCESS(coderate)BEGINIF(coderate'eventANDcoderate='1')THENm(2)<=(m(1)XORm(0))OR(NOT(m(0)ORm(1)orm(2)));ENDIF;ENDPROCESS;

code<=m(0);

PROCESS(sinclk1,clock,code)BEGINIF(code='0')THENsinclk<=sinclk1；ELSEsinclk<=clock;--選擇正弦波產(chǎn)生器的時(shí)鐘頻率

ENDIF;ENDPROCESS;jump_high<=(nottemp)ANDcode;--0到1跳變PROCESS(sinclk) --2FSK跳變的不同處理BEGINIF(sinclk'eventANDsinclk='1')THENtemp<=code;IF((count100="1100011")OR(jump_high='1'))THENcount100<="0000000";ELSEcount100<=count100+'1';ENDIF;ENDIF;ENDPROCESS;PROCESS(count100) --產(chǎn)生正弦周期波形的一個(gè)周期內(nèi)的100個(gè)樣點(diǎn)值BEGINCASEcount100ISWHEN"0000000"=>dout<="01111111"; WHEN"0000001"=>dout<="10000111";WHEN"0000010"=>dout<="10001111"; WHEN"0000011"=>dout<="10010111";WHEN"0000100"=>dout<="10011111"; WHEN"0000101"=>dout<="10100110";WHEN"0000110"=>dout<="10101110"; WHEN"0000111"=>dout<="10110101";WHEN"0001000"=>dout<="10111100"; WHEN"0001001"=>dout<="11000011";WHEN"0001010"=>dout<="11001010"; WHEN"0001011"=>dout<="11010000";WHEN"0001100"=>dout<="11010110"; WHEN"0001101"=>dout<="11011100";WHEN"0001110"=>dout<="11100001"; WHEN"0001111"=>dout<="11100110";WHEN"0010000"=>dout<="11101011"; WHEN"0010001"=>dout<="11101111";WHEN"0010010"=>dout<="11110010"; WHEN"0010011"=>dout<="11110110";WHEN"0010100"=>dout<="11111000"; WHEN"0010101"=>dout<="11111010";

WHEN"0010110"=>dout<="11111100"; WHEN"0010111"=>dout<="11111101";WHEN"0011000"=>dout<="11111110"; WHEN"0011001"=>dout<="11111111";WHEN"0011010"=>dout<="11111110"; WHEN"0011011"=>dout<="11111101";WHEN"0011100"=>dout<="11111100"; WHEN"0011101"=>dout<="11111010";WHEN"0011110"=>dout<="11111000"; WHEN"0011111"=>dout<="11110110";WHEN"0100000"=>dout<="11110010"; WHEN"0100001"=>dout<="11101111";WHEN"0100010"=>dout<="11101011"; WHEN"0100011"=>dout<="11100110";WHEN"0100100"=>dout<="11100001"; WHEN"0100101"=>dout<="11011100";WHEN"0100110"=>dout<="11010110"; WHEN"0100111"=>dout<="11010000";WHEN"0101000"=>dout<="11001010"; WHEN"0101001"=>dout<="11000011";WHEN"0101010"=>dout<="10111100"; WHEN"0101011"=>dout<="10110101";WHEN"0101100"=>dout<="10101110"; WHEN"0101101"=>dout<="10100110";WHEN"0101110"=>dout<="10011111"; WHEN"0101111"=>dout<="10010111";WHEN"0110000"=>dout<="10001111"; WHEN"0110001"=>dout<="10000111";WHEN"0110010"=>dout<="01111111"; WHEN"0110011"=>dout<="01110111";

WHEN"0110100"=>dout<="01101111"; WHEN"0110101"=>dout<="01100111";WHEN"0110110"=>dout<="01011111"; WHEN"0110111"=>dout<="01011000";WHEN"0111000"=>dout<="01010000"; WHEN"0111001"=>dout<="01001001";WHEN"0111010"=>dout<="01000010"; WHEN"0111011"=>dout<="00111011";WHEN"0111100"=>dout<="00110100"; WHEN"0111101"=>dout<="00101110";WHEN"0111110"=>dout<="00101000"; WHEN"0111111"=>dout<="00100010";WHEN"1000000"=>dout<="00011101"; WHEN"1000001"=>dout<="00011000";WHEN"1000010"=>dout<="00010011"; WHEN"1000011"=>dout<="00001111";WHEN"1000100"=>dout<="00001100"; WHEN"1000101"=>dout<="00001000";WHEN"1000110"=>dout<="00000110"; WHEN"1000111"=>dout<="00000100";WHEN"1001000"=>dout<="00000010"; WHEN"1001001"=>dout<="00000001";WHEN"1001010"=>dout<="00000000"; WHEN"1001011"=>dout<="00000000";WHEN"1001100"=>dout<="00000000"; WHEN"1001101"=>dout<="00000001";WHEN"1001110"=>dout<="00000010"; WHEN"1001111"=>dout<="00000100";WHEN"1010000"=>dout<="00000110"; WHEN"1010001"=>dout<="00001000";

WHEN"1010010"=>dout<="00001100"; WHEN"1010011"=>dout<="00001111";WHEN"1010100"=>dout<="00010011"; WHEN"1010101"=>dout<="00011000";WHEN"1010110"=>dout<="00011101"; WHEN"1010111"=>dout<="00100010";WHEN"1011000"=>dout<="00101000"; WHEN"1011001"=>dout<="00101110";WHEN"1011010"=>dout<="00110100"; WHEN"1011011"=>dout<="00111011";WHEN"1011100"=>dout<="01000010"; WHEN"1011101"=>dout<="01001001";WHEN"1011110"=>dout<="01010000"; WHEN"1011111"=>dout<="01011000";WHEN"1100000"=>dout<="01011111"; WHEN"1100001"=>dout<="01100111";WHEN"1100010"=>dout<="01101111"; WHEN"1100011"=>dout<="01110111";WHENothers=>null;ENDCASE;ENDPROCESS;ENDfsk_arch;7.3.52PSK信號(hào)產(chǎn)生器的VHDL程序LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYpskISPORT(clock:INSTD_LOGIC; --正弦波發(fā)生器時(shí)鐘

dout:OUTSTD_LOGIC_VECTOR(7DOWNTO0); --并行數(shù)據(jù)DATAcode:BUFFERSTD_LOGIC

--輸出m序列);ENDpsk;ARCHITECTUREpsk_archOFpskISSIGNALcount100:STD_LOGIC_VECTOR(6DOWNTO0); --記錄100個(gè)狀態(tài)SIGNALcount50:STD_LOGIC_VECTOR(5DOWNTO0);SIGNALsinclk1:STD_LOGIC;SIGNALsinclk,coderate:STD_LOGIC;SIGNALtemp,jump_low,jump_high:STD_LOGIC;SIGNALm:STD_LOGIC_VECTOR(2DOWNTO0); --m序列BEGINPROCESS(clock)BEGINIF(clock'eventANDclock='1')THEN --產(chǎn)生FSK所需的另一個(gè)頻率sinclk1=clock/2sinclk1<=NOTsinclk1;ENDIF;ENDPROCESS;PROCESS(sinclk1) --sinclk1100分頻得到coderate碼元速率BEGINIF(sinclk1'eventANDsinclk1='1')THENIF(count50="110001")THENcount50<="000000";coderate<=NOTcoderate;ELSEcount50<=count50+'1';ENDIF;ENDIF;ENDPROCESS;m_sequence_form: ---產(chǎn)生"1110010"m序列PROCESS(coderate)BEGINIF(coderate'eventANDcoderate='1')THENm(0)<=m(1);m(1)<=m(2);ENDIF;ENDPROCESS;

PROCESS(coderate)BEGINIF(coderate'eventANDcoderate='1')THENm(2)<=(m(1)XORm(0))OR(NOT(m(0)ORm(1)ORm(2)));ENDIF;ENDPROCESS;code<=m(0);jump_low<=(notcode)ANDtemp; --0到1跳變jump_high<=(nottemp)ANDcode; --1到0跳變PROCESS(clock) --2PSK對(duì)跳變的不同處理BEGINIF(clock'eventANDclock='1')THENtemp<=code;IF(jump_low='1')THENcount100<="0110010";ELSIF(jump_high='1')THENcount100<="0000000";ELSIF(count100="1100011")THENcount100<="0000000";ELSEcount100<=count100+'1';ENDIF;ENDIF;ENDPROCESS;PROCESS(count100) --產(chǎn)生正弦周期波形的一個(gè)周期內(nèi)的100個(gè)樣點(diǎn)值BEGINCASEcount100ISWHEN"0000000"=>dout<="01111111"; WHEN"0000001"=>dout<="10000111";WHEN"0000010"=>dout<="10001111"; WHEN"0000011"=>dout<="10010111";WHEN"0000100"=>dout<="10011111"; WHEN"0000101"=>dout<="10100110";WHEN"0000110"=>dout<="10101110"; WHEN"0000111"=>dout<="10110101";WHEN"0001000"=>dout<="10111100"; WHEN"0001001"=>dout<="11000011";WHEN"0001010"=>dout<="11001010"; WHEN"0001011"=>dout<="11010000";WHEN"0001100"=>dout<="11010110"; WHEN"0001101"=>dout<="11011100";WHEN"0001110"=>dout<="11100001"; WHEN"0001111"=>dout<="11100110";WHEN"0010000"=>dout<="11101011"; WHEN"0010001"=>dout<="11101111";WHEN"0010010"=>dout<="11110010"; WHEN"0010011"=>dout<="11110110";WHEN"0010100"=>dout<="11111000"; WHEN"0010101"=>dout<="11111010";WHEN"0010110"=>dout<="11111100"; WHEN"0010111"=>dout<="11111101";WHEN"0011000"=>dout<="11111110"; WHEN"0011001"=>dout<="11111111";WHEN"0011010"=>dout<="11111110"; WHEN"0011011"=>dout<="11111101";

WHEN"0011100"=>dout<="11111100"; WHEN"0011101"=>dout<="11111010";WHEN"0011110"=>dout<="11111000"; WHEN"0011111"=>dout<="11110110";WHEN"0100000"=>dout<="11110010"; WHEN"0100001"=>dout<="11101111";WHEN"0100010"=>dout<="11101011"; WHEN"0100011"=>dout<="11100110";WHEN"0100100"=>dout<="11100001"; WHEN"0100101"=>dout<="11011100";WHEN"0100110"=>dout<="11010110"; WHEN"0100111"=>dout<="11010000";WHEN"0101000"=>dout<="11001010"; WHEN"0101001"=>dout<="11000011";WHEN"0101010"=>dout<="10111100"; WHEN"0101011"=>dout<="10110101";WHEN"0101100"=>dout<="10101110"; WHEN"0101101"=>dout<="10100110";WHEN"0101110"=>dout<="10011111"; WHEN"0101111"=>dout<="10010111";WHEN"0110000"=>dout<="10001111"; WHEN"0110001"=>dout<="10000111";WHEN"0110010"=>dout<="01111111"; WHEN"0110011"=>dout<="01110111";WHEN"0110100"=>dout<="01101111"; WHEN"0110101"=>dout<="01100111";

WHEN"0110110"=>dout<="01011111"; WHEN"0110111"=>dout<="01011000";WHEN"0111000"=>dout<="01010000"; WHEN"0111001"=>dout<="01001001";WHEN"0111010"=>dout<="01000010"; WHEN"0111011"=>dout<="00111011";WHEN"0111100"=>dout<="00110100"; WHEN"0111101"=>dout<="00101110";

WHEN"0111110"=>dout<="00101000"; WHEN"0111111"=>dout<="00100010";WHEN"1000000"=>dout<="00011101"; WHEN"1000001"=>dout<="00011000";WHEN"1000010"=>dout<="00010011"; WHEN"1000011"=>dout<="00001111";WHEN"1000100"=>dout<="00001100"; WHEN"1000101"=>dout<="00001000";WHEN"1000110"=>dout<="00000110"; WHEN"1000111"=>dout<="00000100";WHEN"1001000"=>dout<="00000010"; WHEN"1001001"=>dout<="00000001";WHEN"1001010"=>dout<="00000000"; WHEN"1001011"=>dout<="00000000";WHEN"1001100"=>dout<="00000000"; WHEN"1001101"=>dout<="00000001";WHEN"1001110"=>dout<="00000010"; WHEN"1001111"=>dout<="00000100";WHEN"1010000"=>dout<="00000110"; WHEN"1010001"=>dout<="00001000";WHEN"1010010"=>dout<="00001100"; WHEN"1010011"=>dout<="00001111";WHEN"1010100"=>dout<="00010011"; WHEN"1010101"=>dout<="00011000";WHEN"1010110"=>dout<="00011101"; WHEN"1010111"=>dout<="00100010";WHEN"1011000"=>dout<="00101000"; WHEN"1011001"=>dout<="00101110";WHEN"1011010"=>dout<="00110100"; WHEN"1011011"=>dout<="00111011";

WHEN"1011100"=>dout<="01000010"; WHEN"1011101"=>dout<="01001001";WHEN"1011110"=>dout<="01010000"; WHEN"1011111"=>dout<="01011000";WHEN"1100000"=>dout<="01011111"; WHEN"1100001"=>dout<="01100111";WHEN"1100010"=>dout<="01101111"; WHEN"1100011"=>dout<="01110111";WHENothers=>null;ENDCASE;ENDPROCESS;ENDpsk_arch;7.3.6仿真結(jié)果2FSK信號(hào)產(chǎn)生器的仿真波形如圖7-12所示；2PSK信號(hào)產(chǎn)生器的仿真波形如圖7-13所示。

圖7-122FSK信號(hào)產(chǎn)生器仿真波形圖圖7-132PSK信號(hào)產(chǎn)生器仿真波形圖7.3.7下載驗(yàn)證鎖定引腳時(shí)將clock連至CLK1，dout連至DA輸入端，code連至TESTOUT1(測(cè)試1腳)。綜合適配后將配置數(shù)據(jù)下載入EDA實(shí)驗(yàn)平臺(tái)(技術(shù)資料詳見附錄)的FPGA中(有關(guān)CLK1等引腳在FPGA芯片引腳中的序號(hào),請(qǐng)參見附錄的附圖1)，即可用雙蹤示波器同時(shí)觀察m序列及其對(duì)應(yīng)的2FSK或2PSK波形。7.4實(shí)用多功能電子表7.4.1功能描述多功能電子表共有5種功能：功能1為數(shù)字鐘；功能2為數(shù)字跑表；功能3為調(diào)時(shí)；功能4為鬧鐘設(shè)置；功能5為日期設(shè)置。除調(diào)時(shí)功能以外，電子表處于其他功能狀態(tài)下時(shí)并不影響數(shù)字鐘的運(yùn)行。使用數(shù)字鐘功能時(shí)，還可以通過按鍵快速查看當(dāng)前的鬧鐘設(shè)置時(shí)間和當(dāng)前日期。該電子表利用EDA實(shí)驗(yàn)平臺(tái)的揚(yáng)聲器整點(diǎn)報(bào)時(shí)和定時(shí)報(bào)時(shí)，設(shè)置3個(gè)按鍵分別作為功能鍵和調(diào)整鍵。實(shí)用多功能電子表外部接口如圖7-14所示。圖7-14實(shí)用多功能電子表外部接口