集成電路后端設(shè)計(jì)概述

自動布局布線工具

SocEncounter2023/1/111MEI.XiDianUniv.SocEncounter設(shè)計(jì)流程簡介數(shù)據(jù)的準(zhǔn)備啟動工具設(shè)計(jì)數(shù)據(jù)導(dǎo)入SpecifyFloorplanPowerPlanningPlacement時(shí)鐘樹的綜合時(shí)序分析TrialRoute功耗分析SRouteNanoRoute加Filler數(shù)據(jù)輸出DRC&LVS的準(zhǔn)備2023/1/112MEI.XiDianUniv.設(shè)計(jì)流程簡介-基于標(biāo)準(zhǔn)單元的設(shè)計(jì)流程2023/1/113MEI.XiDianUniv.設(shè)計(jì)流程簡介（續(xù)）-SocE的設(shè)計(jì)流程2023/1/114MEI.XiDianUniv.設(shè)計(jì)流程簡介（續(xù)）-IO&PGplace2023/1/115MEI.XiDianUniv.設(shè)計(jì)流程簡介（續(xù)）-SpecifyFloorplan2023/1/116MEI.XiDianUniv.設(shè)計(jì)流程簡介（續(xù)）-AmebaPlace2023/1/117MEI.XiDianUniv.設(shè)計(jì)流程簡介（續(xù)）-ScanChainReorder2023/1/118MEI.XiDianUniv.設(shè)計(jì)流程簡介（續(xù)）-PowerPlaning2023/1/119MEI.XiDianUniv.設(shè)計(jì)流程簡介（續(xù)）-時(shí)鐘數(shù)綜合2023/1/1110MEI.XiDianUniv.設(shè)計(jì)流程簡介（續(xù)）-功耗分析vdd2023/1/1111MEI.XiDianUniv.設(shè)計(jì)流程簡介（續(xù)）-AddIOFiller2023/1/1112MEI.XiDianUniv.設(shè)計(jì)流程簡介（續(xù)）-PowerRoute2023/1/1113MEI.XiDianUniv.設(shè)計(jì)流程簡介（續(xù)）-DetailRoute2023/1/1114MEI.XiDianUniv.數(shù)據(jù)準(zhǔn)備-必需的文件必須的文件有以下幾個(gè)Gate-Levelnetlist(verilog)PhysicalLibrary(LEF)TimingLibrary(LIB)Timingconstraints(sdc)IOconstraint2023/1/1115MEI.XiDianUniv.數(shù)據(jù)準(zhǔn)備-門級網(wǎng)表需要的是一個(gè)完整和干凈的門級網(wǎng)表完整：讀入的網(wǎng)表必須含有“IOPADS”；“POWERPADS”；“CORNERPADS”等信息。2023/1/1116MEI.XiDianUniv.數(shù)據(jù)準(zhǔn)備-門級網(wǎng)表干凈：1、Uniquifythenetlist2、Simplifynetlistbychangingnamesofnetsinthedesign3、Removeunconnectedfromtheentiredesign4、Makesurethatallpinsnamesofleafcellsarevisible5、Checkforassignandtranstatements6、Checkforunintentionalgatingofclocksorresets7、Checkforunresolvedreferences.2023/1/1117MEI.XiDianUniv.數(shù)據(jù)準(zhǔn)備-門級網(wǎng)表-Uniquifythenetlist這樣雖然會降低網(wǎng)表的可讀性，并且增加了電路規(guī)模，但是解決了一個(gè)問題：就是APR工具完成時(shí)鐘樹綜合以后，只有Uniquify的網(wǎng)表電路，完整的拓樸信息才可以被讀回DC綜合器中，否則只會讀回其中一部分的時(shí)鐘樹電路連接信息。（認(rèn)為一個(gè)時(shí)鐘節(jié)點(diǎn)只能連接一個(gè)葉節(jié)點(diǎn)）。解決辦法：首先：取消所有子模塊的“Donttouch”的特性然后：用Uniquify命令使得所有子模塊不重名！dc_shell>remove_attributefind(-hierarchydesign,“*”)dc_shell>uniquify2023/1/1118MEI.XiDianUniv.SimplifynetlistbychangingnamesofnetsinthedesignAPR工具對網(wǎng)表中的節(jié)點(diǎn)名有一定的要求：1、長度不能太長2、不能出現(xiàn)以“下劃線”開始或結(jié)尾的線名3、線名中不能含有關(guān)鍵字“*cell*”和“*-return”解決辦法：在綜合工具中規(guī)定一些命名規(guī)則1、在.synopsys_dc.setup文件中定義相關(guān)的命名規(guī)則define_names_rulesMYRULE–allowed“A~Za~z0~9”\-first_restricted“_”–last_restricted“_”\-max_length30\-map{{“\*cell\*”，“mycell”},{“*-return”,“myreturn”}}2、在dc_shell中鍵入命令：dc_shell>change_names–hierarchy–rulesMYRULE2023/1/1119MEI.XiDianUniv.Removeunconnectedfromtheentiredesign在網(wǎng)表中會有一些不影響功能，但是卻保持開路不連接的狀態(tài)，我們最好是把它在DC里去除。因?yàn)?，這些節(jié)點(diǎn)會在APR工具中出現(xiàn)warning，可能會把一些重要的warning信息覆蓋解決辦法：dc_shell>remove_unconnected_portsfind(hierarchycell,“*”)dc_shell>check_design2023/1/1120MEI.XiDianUniv.Makesurethatallpinsnamesofleafcellsarevisible所有單元的端口實(shí)現(xiàn)顯形調(diào)用，包括沒有連接的端口，避免端口數(shù)目不匹配。如：庫中有一個(gè)觸發(fā)器：DEF(CLK,D,Q,QN)在調(diào)用的時(shí)候，只用到了三端DFFdff1(.CLK(clk),.D(data),.Q(out))這樣，在讀入netlist的時(shí)候會出現(xiàn)不匹配的問題解決辦法：在.synopsys_dc.setup文件中,把顯形調(diào)用開關(guān)打開verilogout_show_unconnected_pins=ture2023/1/1121MEI.XiDianUniv.Checkforassignandtranstatements很多的APR工具對三態(tài)線和Assign的賦值狀態(tài)無法處理，所以需要在綜合的時(shí)候進(jìn)行適當(dāng)?shù)奶幚砣龖B(tài)線的解決辦法(可能是因?yàn)樵O(shè)計(jì)中有inout的端口定義）：在.synopsys_dc.setup文件中設(shè)置：verilogout_no_tri=tureAssignstatements的解決辦法dc_shell>set_fix_multiple_port_nets–feedthroughdc_shell>set_fix_multiple_port_nets–all–buffer_constraintsdc_shell>remove_attributefind(net,<netname>)dont_touchBlockInoutBlockInoutgnd2023/1/1122MEI.XiDianUniv.Checkforunintentionalgatingofclocksorresets由于時(shí)鐘是其他一切信號的參考信號，所以，如果在綜合的時(shí)候clock信號中插入了一些buffer（很可能是由于沒有設(shè)置set_dont_touch_network)，這些buffer會影響到時(shí)鐘信號的latency和skew.一般情況下，全局的reset信號也需要被保護(hù)。解決辦法：dc_shell>report_transitive_fanout–clock_treedc_shell>report_transitive_fanout–fromreset-clock_tree和-from這兩個(gè)選項(xiàng)有一定的區(qū)別，-clock_tree可以由-from來替代，但是反過來不行。用-clock_tree選項(xiàng)的時(shí)候要保證已經(jīng)建立了時(shí)鐘信號（create_clock)2023/1/1123MEI.XiDianUniv.Checkforunresolvedreferences如果設(shè)計(jì)網(wǎng)表中存在沒有定義的模塊，則會出現(xiàn)一些報(bào)警（warning),在把網(wǎng)表送到APR工具之前，需要解決這些問題。例如，網(wǎng)表的頂層模塊是A，模塊A調(diào)用了模塊B，但是在讀入的庫信息中，沒有關(guān)于模塊B的定義；此時(shí)如果輸出一個(gè)模塊A的網(wǎng)表文件，就會出現(xiàn)unresolvedreference的報(bào)警信息。2023/1/1124MEI.XiDianUniv.數(shù)據(jù)準(zhǔn)備-物理信息文件LEFPhysicalLibrary(LEF)和GDSII有差別：含有兩類重要信息：1、和工藝相關(guān)的信息2、和自動布局布線有關(guān)的信息2023/1/1125MEI.XiDianUniv.數(shù)據(jù)準(zhǔn)備-物理信息文件LEF（續(xù)）1、和工藝相關(guān)的信息-三部分（1）層定義：單元內(nèi)部含有哪些Layer(ploy；metal1；contact；metal2；via1)（2）設(shè)計(jì)規(guī)則線寬；線間距；面積；電流密度；天線效應(yīng)；（3）寄生參數(shù)的定義電容；電阻2023/1/1126MEI.XiDianUniv.數(shù)據(jù)準(zhǔn)備-物理信息文件LEF（續(xù)）2、和自動布局布線有關(guān)信息（六部分）Unit（單元名等信息）Site（位置信息）Routingpitch（走線規(guī)則，線間距）Defaultdirection（方向信息）Viagenerate（自動實(shí)現(xiàn)互連）Viastack（通孔之間是否可以疊放）2023/1/1127MEI.XiDianUniv.數(shù)據(jù)準(zhǔn)備-物理信息文件LEF（續(xù)）2、和自動布局布線有關(guān)信息-Site2023/1/1128MEI.XiDianUniv.數(shù)據(jù)準(zhǔn)備-物理信息文件LEF（續(xù)）2、和自動布局布線有關(guān)信息-Routingpitch，DefaultdirectionMetal1routepitchMetal2routepitchDirection：奇數(shù)層：水平偶數(shù)層：垂直2023/1/1129MEI.XiDianUniv.數(shù)據(jù)準(zhǔn)備-物理信息文件LEF（續(xù)）2、自動布局布線有關(guān)信息-Viagenerate當(dāng)兩個(gè)不同的層交叉的時(shí)候需要實(shí)現(xiàn)自動連接和寬AL連接的時(shí)候需要通孔陣列來減小連線電阻LayerMetal1DirectionHORIZONTALOVERHANG0.2LayerMetal2DirectionVERTICALOVERHANG0.2LayerVia1RECT–0.14–4SPACING0.56BY0.562023/1/1130MEI.XiDianUniv.數(shù)據(jù)準(zhǔn)備-物理信息文件LEF（續(xù)）2、和自動布局布線有關(guān)信息－Viastack高層的金屬容易走線布線的密度高必須符合最小線間距等設(shè)計(jì)規(guī)則2023/1/1131MEI.XiDianUniv.數(shù)據(jù)準(zhǔn)備-物理信息文件LEF（續(xù)）2、和自動布局布線有關(guān)信息－宏單元(MACRO)宏單元的種類：StandardcellsI/OpadsMemoriesotherhardmacros描述的信息：SizeClassPinsObstructions2023/1/1132MEI.XiDianUniv.數(shù)據(jù)準(zhǔn)備-物理信息文件LEF（續(xù)）2、和自動布局布線有關(guān)信息－宏單元(MACRO)MACROADD1CLASSCORE;FOREIGNADD10.00.0;ORIGEN0.00.0;LEQADD;SIZE19.8BY6.4;SYMMETRYxy;SITEcoresitePINADIRECTIONINPUT;PORTLAYERMetal1;RECT10.3……ENDENDAOBS……ENDENDADD12023/1/1133MEI.XiDianUniv.數(shù)據(jù)準(zhǔn)備-時(shí)序信息文件（LIB)Operatingconditionslow,fast,typicalPintypeinput/output/inout

functiondata/clockcapacitancePathdelayTimingconstraintsetup,hold,mpwh,mpwl,recovery2023/1/1134MEI.XiDianUniv.數(shù)據(jù)準(zhǔn)備-時(shí)序約束文件（SDC)CreateclockInputdelayOutputdelayInputdriveOutputloading2023/1/1135MEI.XiDianUniv.數(shù)據(jù)準(zhǔn)備-時(shí)序約束文件（SDC)－續(xù)Createclock語法：create_clock[-nameclock_name]-periodperiod_value[-waveformedge_list][clock_source_list]create_clock–nameCLK1–period20–waveform{010}[get_portsI_CLK]周期2023/1/1136MEI.XiDianUniv.數(shù)據(jù)準(zhǔn)備-時(shí)序約束文件（SDC)－續(xù)create_generated_clockclkDQNI_clkdiv_clkcontrolg_clk語法：create_generated_clock-add-master_clock[-nameclock_name]-sourcemaster_clock_root[-multiply_bymult][-divide_bydiv][-duty_cycledc][-invert][-edgesedge_list][-edge_shiftedge_shift_list]clock_root_list：create_generated_clock–nameCLK2–source[get_portsI_CLK]–divide_by2[get_pinsDF/QN]：2023/1/1137MEI.XiDianUniv.數(shù)據(jù)準(zhǔn)備-時(shí)序約束文件（SDC)－續(xù)SetInputdelay

set_input_delaydelay_value[-min][-max][-rise][-fall][-clockclock_name][-clock_fall][-add_delay][-network_latency_included][-source_latency_included]port_pin_listset_input_delay1–clock[get_clocks{CLK}][getports{A}]2023/1/1138MEI.XiDianUniv.數(shù)據(jù)準(zhǔn)備-時(shí)序約束文件（SDC)－續(xù)Setoutputdelay

set_output_delaydelay_value[-min][-max][-rise][-fall][-clockclock_name][-add_delay][-network_latency_included][-source_latency_included]port_pin_listset_output_delay1–clock[get_clocks{CLK}][getports{B}]2023/1/1139MEI.XiDianUniv.數(shù)據(jù)準(zhǔn)備-時(shí)序約束文件（SDC)－續(xù)SetInputdrive

set_drive[-min][-max][-rise][-fall]drive_strengthport_listset_drive1[get_ports{IN1}]IN1IN2IN2IN1DELAYDELAYrise_min,rise_max,fall_min,fall_maxdesign2023/1/1140MEI.XiDianUniv.數(shù)據(jù)準(zhǔn)備-時(shí)序約束文件（SDC)－續(xù)SetLoad

set_load[-min][-max][-pin_load][-wire_load]load_valueport_listset_load1[get_ports{out1}]等效負(fù)載電容out2out1等效負(fù)載電容design2023/1/1141MEI.XiDianUniv.數(shù)據(jù)準(zhǔn)備-IO約束文件手工編寫IO的約束文件(encounter可以自動分派，但是效果不好）文件語法如下：Version:1MicronPerUserUnit:valuePin:pinNameside|cornerPad:padInstanceNameside|corner[cellName]Offset:lengthSkip:lengthSpacing:lengthKeepclear:sideoffset1offset22023/1/1142MEI.XiDianUniv.數(shù)據(jù)準(zhǔn)備-IO約束文件－續(xù)IO約束文件的例子Version:1Pad:CORNER0NWPad:PAD_CLKNPad:PAD_HALTNPad:CORNER1NEPad:PAD_X1WPad:PAD_X2WPad:CORNER2SWPad:PAD_IOVDD1SPad:PAD_IOVSS1SPad:CORNER3SEPad:PAD_VDD1EPad:PAD_VSS1E2023/1/1143MEI.XiDianUniv.啟動工具準(zhǔn)備工作和必備文件確保你的.cshrc含有相應(yīng)的路徑設(shè)置在terminal的命令行鍵入：encounter命令不要使用后臺啟動模式：因?yàn)閱觘ncounter后，terminal變成了鍵入命令的一個(gè)窗口！Encounter啟動的時(shí)候會自動的運(yùn)行一些初始化文件:$ENCOUNTER/etc/enc.tcl;./enc.tcl;./enc.pref.tcl生成的LOG文件有：encounter.log&encounter.cmd2023/1/1144MEI.XiDianUniv.啟動工具－續(xù)（快捷鍵）KeyActionqEditattributefFitsdisplayzZoominZZoomoutArrowspansdesignareainthedirectionofthearrowDeleteRemovesthelastrulerEscRemovesallrulersKeyActiondpopupDeleteepopupEditTeditTrim0-9Viewlayer[0-9]hhierarchyupHhierarchydownDesign->Preference,BindingKey2023/1/1145MEI.XiDianUniv.ImportDesign-DesignDesignDesignImportMaxTimingLibrariescontainingworst-caseconditionssetup-timeanalysisMinTimingLibrariescontainingbest-caseconditionshold-timeanalysisCommonTimingLibrariesusedinbothsetupandholdanalysisIOAssignmentFile:getaIOassignmenttemplate2023/1/1146MEI.XiDianUniv.ImportDesign-Design續(xù)BufferName/Footprint:specifiesthebuffercellfamilytobeinsertedorswapped.requiredtorunIPOandTDplacement.DelayName/Footprint:requiredtorunafixholdtimeviolationInverterName/Footprint:requiredtorunIPOandTDplacement.Getfootprintoflibrarycellsby:TimingReportCellFootprint2023/1/1147MEI.XiDianUniv.ImportDesign-Design續(xù)FootprintExample:ForCells:BUFXLBUFX1BUFX2BUFX3BUFX4BUFX8BUFX12BUFX16BUFX20Footprint:buf2023/1/1148MEI.XiDianUniv.ImportDesign-TimingDefaultDelayPinLimit:指定設(shè)計(jì)中所有的連線節(jié)點(diǎn)不能接超過這個(gè)值，如果超過這個(gè)臨界值則按這個(gè)值計(jì)算DefaultNetDelay:Setthedelayvaluesforanetthatmeetsthepinlimitdefault.DefaultNetLoad:Settheloadforanetthatmeetsthepinlimitdefault.InputTransitionDelay:SetthePrimaryinputsandclocknets.TimingConstraintInformation:設(shè)定時(shí)序約束文件2023/1/1149MEI.XiDianUniv.ImportDesign-Power指定設(shè)計(jì)中的電源和地線的名字這個(gè)名字只是設(shè)計(jì)者臨時(shí)定義的一個(gè)名字。為了讓這個(gè)名字和網(wǎng)表的電源和地實(shí)現(xiàn)電氣上的連接，還需要在Global-net-connection中指定2023/1/1150MEI.XiDianUniv.ImportDesign-Power-globalnetconnection2023/1/1151MEI.XiDianUniv.SpecifyFloorplan2023/1/1152MEI.XiDianUniv.SpecifyFloorplan2023/1/1153MEI.XiDianUniv.Floorplan-PlaceBlocks（自動）點(diǎn)擊命令：Floorplan

PlaceBlocks/ModulesPlace…完成自動的placeBlocks(blackboxs&partitions)hardmacros（如SRAM,ROM等)Blockhalo:在Block的一周設(shè)置一定范圍不準(zhǔn)布線和放標(biāo)準(zhǔn)單元.2023/1/1154MEI.XiDianUniv.Floorplan-PlaceBlocks（手工）可以在工具中選擇按鈕：來移動和改變Block的形狀，從而放在合適的位置?？梢酝ㄟ^命令：Floorplan

EditFloorplan來實(shí)現(xiàn)比較理想的Floorplan通過命令：FloorplanEditFloorplan

SetBlockPlacementStatus…來設(shè)置放好的宏單元的狀態(tài)為“preplace”，從而避免這些單元在后面的ameobaplace過程中被移動2023/1/1155MEI.XiDianUniv.Floorplan-addblockhaloFloorplan

EditBlockHalo…,Halo可以避免在block周圍的過于擁擠2023/1/1156MEI.XiDianUniv.Floorplan-powerplanAddcorering2023/1/1157MEI.XiDianUniv.Floorplan-powerplan（續(xù)）Addtheblockring2023/1/1158MEI.XiDianUniv.Floorplan-powerplan（續(xù)）Addtheblockring2023/1/1159MEI.XiDianUniv.Floorplan-powerplan（續(xù)）Addstripes2023/1/1160MEI.XiDianUniv.AmeobaPlacePrototyping:Runsquickly,butcomponentsmaynotbeplacedatlegallocation.TimingDriven:Buildtiminggraphbeforeplace.meetingsetuptimingconstraintswithroutability.LimitedIPObyupsizeing/downsizinginstances.IgnoreScanConnectionnetsconnectedtoeitherthescan-inorscan-outareignored.CheckplacementafterplacedplaceCheckPlacementPlacePlace…2023/1/1161MEI.XiDianUniv.ClockProblemClockproblemHeavyclocknetloadingLongclockinsertiondelayClockskewSkewacrossclocksClocktosignalcouplingeffectClockispowerhungryElectromigrationonclocknetSolutionsoftheseproblemsmaybeconflictClockisoneofthemostimportanttreasureinachip,donottakeitasotheruse.2023/1/1162MEI.XiDianUniv.ClockTreeTopology2023/1/1163MEI.XiDianUniv.SynthesizeClockTree2023/1/1164MEI.XiDianUniv.CreateClockTreeSpec.ClockCreateClockTreeSpec2023/1/1165MEI.XiDianUniv.CTSCTStracestheclockstartingfromarootpin,andstopsat:AclockpinAD-inputpinAninstancewithoutatimingarcAuser-specifiedleafpinorexcludedpinWriteaCTSspec.template:specifyClockTree-template2023/1/1166MEI.XiDianUniv.CTSspec.ACTSspec.containthefollowinginformation.Timingconstraintfile(optional)Namingattributes(optional)Macromodeldata(optional)Clockgroupingdata(optional)AttributesusedbyNanoRouteroutingsolution(optional)RequirementformanualCTSorgatedCTS2023/1/1167MEI.XiDianUniv.CTSSpec.

--ManuallyDefineClockTreeTopologyClockNetNamenetNameLevelNumber

numberSpecifytheclocktreelevelnumberLevelSpec

levelNumbernumberOfBuffersbufferTypelevelNumber

SpecifythelevelnumberintheclocktreenumberOfBuffer

thetotalnumberofbuffersCTSshouldallowonthespecifiedlevelExample:

LevelSpec12CLKBUFX2

LevelSpec22CLKBUFX2End2023/1/1168MEI.XiDianUniv.CTSSpec.

--AutomaticGatedCTSSectionAutoCTSRootPinclockRootPinNameMaxDelay

number{ns|ps}MinDelay

number{ns|ps}SinkMaxTran

number{ns|ps}maximuminputtransitiontimeforsinks(clockpins)BufMaxTran

number{ns|ps}maximuminputtransitiontimeforbuffers(default400)MaxSkew

number{ns|ps}2023/1/1169MEI.XiDianUniv.CTSSpec.

--AutomaticGatedCTSSectioncont.NoGating

{rising|falling|NO}rising:stopstracingthroughagate(includebuffersandinverters)andtreatsthegateasarising-edge-triggeredflip-flopclockpin.falling:stopstracingthroughagate(includebuffersandinverters)andtreatsthegateasafalling-edge-triggeredflip-flopclockpin.No:AllowsCTStotracethroughclockgatinglogic.(default)AddDriverCell

driver_cell_namePlaceadrivercellattheclosestpossiblelocationtotheclockportlocation.2023/1/1170MEI.XiDianUniv.CTSSpec.

--AutomaticGatedCTSSectioncont.LeafPin

+pinNamerising|falling+……Markthepinasa“l(fā)eaf”pinfornon-clock-typeinstances.

LeafPin

+instance1/Arising+instance2/ArisingLeafPort

+portNamerising|faling

+……Marktheportasa“l(fā)eaf”portfornon-clock-typeinstances2023/1/1171MEI.XiDianUniv.CTSSpec.

--AutomaticGatedCTSSectioncont.ExcludedPin

+pinName

+…..ExcludedPort

+portName

+……Treatstheportasanon-leafport,andpreventstracingandskewanalysisofthepin.2023/1/1172MEI.XiDianUniv.CTSSpec.

--AutomaticGatedCTSSectioncont.ThroughPin

+pinName

+…..Tracesthroughthepin,evenifthepinisaclockpinPreservePin

+inputPinName

+…….Preservethenetlistforthepinsbelowthepinintheclocktree.2023/1/1173MEI.XiDianUniv.SynthesizeClockTreeClockSynthesizeClockTree2023/1/1174MEI.XiDianUniv.ClockSynthesisreportSummaryreportanddetailreportnumberofsubtreesrise/fallinsertiondelaytriggeredgeskewrise/fallskewbufferandclockpintransitiontimedetaileddelayrangesforallbuffersaddtoclocksClocknetsSavesthegeneratedclocknetsusedtoguideclocknetroutingClockroutingguideSavestheclocktreeroutingdatausedasprerouteguidewhilerunningTrialRoute2023/1/1175MEI.XiDianUniv.DisplayClockTreeClockDisplayDisplayClockTree…2023/1/1176MEI.XiDianUniv.DisplayClockTree

--bylevel2023/1/1177MEI.XiDianUniv.DisplayClockTree

--byphasedelay2023/1/1178MEI.XiDianUniv.ClockTreeBrowserClockClockTreeBrowerDisplaytrigedge,rise/falldelay,rise/fallskew,inputdelay,inputtranofeachcell.Resize/DeleteleafcellorclockbufferReconnectclocktree2023/1/1179MEI.XiDianUniv.In-PlaceOptimizationIPOsetuptimeholdtimeDRV(DesignRuleViolation)2023/1/1180MEI.XiDianUniv.TrialRouteperformquickroutingforcongestionandparasiticsestimationPrototyping:Qponentsindesignmightnoberoutedatlegallocation2023/1/1181MEI.XiDianUniv.TrialRouteCongestionMarkervisuallycheckthecongestionstatistics.dumpcongestionarea:dumpCongesArea-allfile_nameThevertical(V)overflowis25/20(25tracksarerequired,butonly20tracksareavailable).TheHorizontal(H)overflowis16/18(16tracksarerequired,and18tracksareavailable)2023/1/1182MEI.XiDianUniv.TrialRouteCongestionMarkercont.LevelColorOverflowValue1!BlueOnemoretrackrequired2!GreenTwomoretrackrequired3!YellowThreemoretrackrequired4!RedFourmoretrackrequired5!MagentaFivemoretrackrequired6andhigher!GreytoWhiteSixormoretrackrequired2023/1/1183MEI.XiDianUniv.TimingAnalysisTimingSpecifyAnalysisConditionSpecifyRCExtractionMode…TimingExtractRC…TimingTimingAnalysis…NoAsync/Async:recovery,removalcheckNoSkew/Skew:checkwith/withoutclockskewconstraint2023/1/1184MEI.XiDianUniv.SlackBrowserTimingTimingDebugSlackBrowser…2023/1/1185MEI.XiDianUniv.PowerAnalysisTimingExtractRC…PowerEditPadLocation…PowerEditNetToggleProbability…2023/1/1186MEI.XiDianUniv.StatisticalPowerAnalysisPowerPowerAnalysisStatistical…analysisreport:ApowergraphreportcontainsaveragepowerusageworstIRdropworstEMviolationinstancepowerfileinstancevoltagefileboundaryvoltagefile2023/1/1187MEI.XiDianUniv.Simlation-BasedPowerAnalysisPowerPowerAnalysisSimulation-BasedsavenetlistforsimulationDesignSaveNetlist…simulationanddumpvcdfile.$dumpvars;$dumpfile(“wave.vcd”);Inputvcdfileforpoweranalysis2023/1/1188MEI.XiDianUniv.DisplayIRDropPowerDisplayDisplayIRDrop…2023/1/1189MEI.XiDianUniv.DisplayElectronMigrationPowerDisplayDisplayEM…2023/1/1190MEI.XiDianUniv.SRouteRouteSpecialNet(power/groundnet)BlockpinsPadpinsPadringsStandardcellpinsStripes(unconnected)2023/1/1191MEI.XiDianUniv.AddIOfilleraddIoFiller

–cellPFILL–prefixIOFILLERaddIoFiller

–cellPFILL_9–prefixIOFILLERaddIoFiller

–cellPFILL_1–prefixIOFILLERaddIoFiller

–cellPFILL_01–prefixIOFILLER-fillAnyGapConnectiopadpowerbusbyinsertingIOfiller.Addfromwiderfillertonarrowerfiller.（由小到大）2023/1/1192MEI.XiDianUniv.NanoRouteRouteNanoRoute2023/1/1193MEI.XiDianUniv.AddCoreFillerPlaceFillerAddFiller…ConnecttheNWELL/PWELLlayerincorerows.InsertWellcontact.Addfromwiderfillertonarrowerfiller.2023/1/1194MEI.XiDianUniv.OutputDataDesignSaveGDS…DesignSaveNetlist…DesignSaveDEFExportGDSforDRC,LVS,LPE,andtapeout.ExportNetlistforLVSandsimulation.ExportDEFforreorderedscanchain.2023/1/1195MEI.XiDianUniv.Post-LayoutVerification–

DRC/ERC/LVS/LPE

2023/1/1196MEI.XiDianUniv.Post-LayoutVerificationOverviewPost-LayoutVerificationdothefollowingthings:DRC(DesignRuleCheck)ERC(ElectricalRuleCheck)LVS(LayoutversusSchematic)LPE/PRE(LayoutParasiticExtraction/ParasiticResistanceExtraction)andPost-LayoutSimulation.2023/1/1197MEI.XiDianUniv.Post-LayoutVerificationOverviewcont.2023/1/1198MEI.XiDianUniv.Post-LayoutVerificationOverviewcont.2023/1/1199MEI.XiDianUniv.DRCflowPrepareLayoutstreamingds2addpowerpadtextstreamoutgds2PreparecommandfilerunDRCViewDRCerror(DRCsummary)2023/1/11100MEI.XiDianUniv.PrepareLayout2023/1/11101MEI.XiDianUniv.PrepareLayout:StreamInGDSIIRequire:technologyfiledisplay.drfFile->import->stream2023/1/11102MEI.XiDianUniv.PrepareLayout:AddPowerTextAddpowertextforLVSandPostsimForlibraryAddtextDVDDforIOpowerpadAddtextDGNDforIOgroundpadAddtextVDDforcorepowerpadAddtextGNDforcoregroundpad2023/1/11103MEI.XiDianUniv.PrepareLayout:StreamOutGDSIIFile->Export->stream..2023/1/11104MEI.XiDianUniv.PreparecommandfileEditrunsetfileLAYOUTPATH“CHIP.gds2”LAYOUTPRIMARY“CHIP”LAYOUTSYSTEMGDSII…DRCSELECTCHECKNW.W.1NW.W.2…DRCUNSELECTCHECKNW.S.1YNW.S.2Y…DRCICSTATIONYESINCLUDE“Calibre-drc-cur”2023/1/11105MEI.XiDianUniv.SubmitCalibreJobSubmitCalibreJob

calibre

–drcumc18DRC.calResultlogCHIP.drc.summary(ASCIIresult)CHIP.drc.results(Graphicresult)2023/1/11106MEI.XiDianUniv.UsingCalibreRVEAddin.cdsinitsetSkillPath(“.~//usr/memtor/Calibre_ss/cur/shared/pkgs/icb/tools/queryskl”)load(“calibre.skl”)2023/1/11107MEI.XiDianUniv.UsingCalibreRVE2023/1/11108MEI.XiDianUniv.UsingCalibreRVE2023/1/11109MEI.XiDianUniv.LVSOverview2023/1/11110MEI.XiDianUniv.InitialCorrespondencePointsInitialcorrespondencepointsestablishastartingplaceforlayoutandschematiccomparison.Createinitialcorrespondencenodepairsbyaddingtextstringsonlayoutdatabase.allpinsinthetopofschematicnetlistwillbetreatedasaninitialcorrespondingnodeifcalibrefindsatextstringinlayoutwhichmatchesthenodenameinschematic.2023/1/11111MEI.XiDianUniv.Black-BoxLVSCalibreblack-boxLVSOnetypeofhierarchicalLVS.Black-boxLVStreatseverylibrarycellasablackbox.Black-boxLVSchecksonlytheinterconnectionsbetweenlibrarycellsinyourdesign,butnotcellinside.Youneednotknowthedetaillayoutofeverylibrarycells.ReduceCPUtime.2023/1/11112MEI.XiDianUniv.Black-BoxLVSvs.Transistor-LevelLVS2023/1/11113MEI.XiDianUniv.LVSflowPrepareLayoutThesameasDRCPrepareLayoutPrepareNetlist

v2lvsPreparecalibrecommandfileruncalibreLVSViewLVSerror(LVSsummary/RVE)2023/1/11114MEI.XiDianUniv.PrepareNetlistforCalibreLVSv2lvs–vCHIP.v–lumc18lvs.v–oCHIP.spi

–sumc18lvs.spiIfamacroDRAM64x16isusedv2lvs–vCHIP.v–lumc18lvs.v–lDRAM64x16.v–oCHIP.spi

–sumc18lvs.spi

–sDRAM64x16.spi2023/1/11115MEI.XiDianUniv.PreparecommandfileforCalibreLVSandrunLVSEditthecommandfileLAYOUTPATH“CHIP.calibre.gds”LAYOUTPIMARY“CHIP”LAYOUTSYSTEMGDSIISOURCEPATH“CHIP.spi”SOURCEPRIMARY“CHIP”RuntheLVScalibre

–lvs

–spiceCHIP.spi

–hier

–autoumc18LVS.cal2023/1/11116MEI.XiDianUniv.APR中設(shè)置預(yù)估一些經(jīng)驗(yàn)值2023/1/11117MEI.XiDianUniv.內(nèi)容IntroductionFloorplan的問題Powerplan的問題Placement的問題Routing的問題2023/1/11118MEI.XiDianUniv.集成電路設(shè)計(jì)的基本流程2023/1/11119MEI.XiDianUniv.物理設(shè)計(jì)流程IOPADPlacementFloorplan&PowerGlobalPlacementDetailPlacementCTSGlobalRouteDetailRouteExtractionDelaycalcTimingverification2023/1/11120MEI.XiDianUniv.幾個(gè)基本概念Cell:acircuitcomponenttobeplacedonthechiparea.Inplacement,thefunctionalityofthecomponentisignored.Net:specifyingasubsetofterminals,toconnectseveralcells.Netlist:asetofnetswhichcontainstheconnectivityinformationofthecircuit.2023/1/11121MEI.XiDianUniv.Floorplan的問題2023/1/11122MEI.XiDianUniv.FloorplanningInputDesignnetlist(required)Arearequirements(required)Powerrequirements(required)Timingconstraints(required)Physicalpartitioninginformation(required)Diesizevs.performancevs.scheduletrade-off(required)I/Oplacement(optional)Macroplacementinformation(optional)2023/1/11123MEI.XiDianUniv.FloorplanningOutputDie/blockareaI/OsplacedMacrosplacedPowergriddesignedPowerpre-routingStandardcellplacementareasDesignreadyforstandardcellplacement2023/1/11124MEI.XiDianUniv.Floorplan的主要任務(wù)BlocksIOPad布線通道1、把所有的Block放在IOPAD的限制的框架內(nèi)2、留出足夠的內(nèi)部走線通道3、不同的Block（硬核、固核、軟核）有不同的形狀和尺寸，增加了布線難道，調(diào)整Block位置和方向（可以旋轉(zhuǎn)、鏡像等）2023/1/11125MEI.XiDianUniv.物理設(shè)計(jì)時(shí)Die尺寸的預(yù)估針對每個(gè)設(shè)計(jì)，需要一個(gè)合適的面積面積與性能是一個(gè)比較復(fù)雜的關(guān)系面積太小可能導(dǎo)致布線困難、迭代次數(shù)過多以及版圖無法實(shí)現(xiàn)等問題采用物理設(shè)計(jì)方法與面積呈一個(gè)反比關(guān)系2023/1/11126MEI.XiDianUniv.物理設(shè)計(jì)時(shí)Die尺寸的預(yù)估－續(xù)Die尺寸的經(jīng)典值：

3層金屬布線：Cell利用率－65％4層金屬布線：Cell利用率－70％5層金屬布線：Cell利用率－75％6層金屬布線：Cell利用率－80％FloorPlan的衡量準(zhǔn)則：如果互連密度低－用Cell利用率來表示如果互連密度高－用Net利用率來表示2023/1/11127MEI.XiDianUniv.通道－Channels定義:每一條布線通道都中止于Block的邊界通道的形成與你擺放Block的位置有關(guān)2023/1/11128MEI.XiDianUniv.通道的交叉圖定義：交叉圖的節(jié)點(diǎn)是通道，邊是兩個(gè)互相接觸的通道節(jié)點(diǎn)的連線。交叉圖表示一種通道間的路徑信息交叉圖可以用來指導(dǎo)globalRouting2023/1/11129MEI.XiDianUniv.FloorPlan的建議某個(gè)布線通道的全局（需要連接出去）走線會在相鄰的通道邊延處產(chǎn)生Pin腳如果布線通道交叉圖形成一個(gè)環(huán)狀（Wheel)，則認(rèn)為這個(gè)布局會布不通，這樣的布局是不好的ChannelAChannelB引入pin腳約束2023/1/11130MEI.XiDianUniv.好的FloorPlan－SlicingFloorplanSlicingFloorplan定義：橫豎切片，每次把剩下的圖形切成兩部分，而不會切到Blocks（其實(shí)就是一個(gè)二叉樹結(jié)構(gòu)，枝干是切片的Channel，樹葉是Blocks）這樣的FloorPlan可以保證不會出現(xiàn)Wheel，從而保證可布通。2023/1/11131MEI.XiDianUniv.PowerPlan問題2023/1/11132MEI.XiDianUniv.Powerplan為了更好的對芯片供電，需要建立：1、coreRing2、blocksring3、stripes從而建立合適的電源網(wǎng)格2023/1/11133MEI.XiDianUniv.Power布線資源20～40％用于VCC,VSSPower的增加需要更加密集的電源網(wǎng)格PIN：VccorVsspincarries0.5-1WofpowerPentium4uses423pins;223VccorVssMorepins＝packagemoreexpensive（封裝和PCB系統(tǒng)重新設(shè)計(jì)的費(fèi)用）電池1kgNiCadbatterypowersaPentium4aloneforlessthan1hour性能：HighchiptemperaturesdegradecircuitperformanceLargeacross-chiptemperaturevariationsinduceclockskewHighchippowerlimitsuseofhigh-performancecircuitsPowertransientsdetermineminimumpowersupplyvoltage2023/1/11134MEI.XiDianUniv.Power－續(xù)Pentium4dieisabout1.5gandlessth