EDA技術(shù)與應(yīng)用講義 第章 原理圖輸入設(shè)計(jì)方法 QUARUS II本

第3章

原理圖輸入設(shè)計(jì)方法QuartusII版操作

<EDA技術(shù)與應(yīng)用>課程講義合肥工業(yè)大學(xué)彭良清上一章下一章本章內(nèi)容何時(shí)使用原理圖設(shè)計(jì)輸入常用文件介紹設(shè)計(jì)步驟元件庫(kù)和Altera宏的使用如何將VHDL代碼文件生成圖形符號(hào)何時(shí)使用原理圖設(shè)計(jì)輸入？符合傳統(tǒng)的電路設(shè)計(jì)習(xí)慣一般只是在“top-level”(頂層)文件中使用？QuartusII常用文件介紹

文件擴(kuò)展名稱(chēng)用途MAX+PLUSII中的名稱(chēng).vhdVHDL代碼源文件.vhd.bdf圖形輸入源文件.gdf.qsf器件引腳與編譯配置指配文件.qsf.pofCPLD,EEPROM器件編程文件.pof.sofFPGA器件的SRAM文件配置.sof一般步驟電路的模塊劃分設(shè)計(jì)輸入器件和引腳指配編譯與排錯(cuò)功能仿真和時(shí)序仿真編程與配置，設(shè)計(jì)代碼的芯片運(yùn)行電路的模塊劃分人工根據(jù)電路功能進(jìn)行模塊劃分合理的模塊劃分關(guān)系到電路的性能實(shí)現(xiàn)的難易程度根據(jù)模塊劃分和系統(tǒng)功能確定：

PLD芯片型號(hào)模塊劃分后，就可以進(jìn)行具體設(shè)計(jì)了設(shè)計(jì)輸入一般EDA軟件允許3種設(shè)計(jì)輸入：HDL語(yǔ)言電路圖波形輸入圖形設(shè)計(jì)輸入的過(guò)程++圖形設(shè)計(jì):圖元圖形設(shè)計(jì):端口如何編寫(xiě)寫(xiě)一個(gè)新新的圖形形文件？？FILE->NEW出出現(xiàn)以下下對(duì)話窗窗，選擇擇如下：：如何調(diào)入入元件？？Edit->InsertSymbol出現(xiàn)現(xiàn)下面窗窗口將自己編寫(xiě)寫(xiě)的符號(hào)調(diào)入入從標(biāo)準(zhǔn)庫(kù)中中調(diào)入將符號(hào)之之間連線線調(diào)入I/O端口口元件符符號(hào)2類(lèi)標(biāo)標(biāo)準(zhǔn)庫(kù)庫(kù)Megafunctions/LPM宏宏模塊塊功能復(fù)雜雜、參數(shù)數(shù)可設(shè)置置的模塊塊Primitives基本圖元元簡(jiǎn)單的、、功能固固定的邏邏輯元件件，不可可調(diào)整參參數(shù)如何將VHDL設(shè)計(jì)編編程SymbolVHDL文件編編譯后，，自動(dòng)生生成同名名的符號(hào)號(hào)文件符號(hào)文件件的擴(kuò)展展名稱(chēng)（（*.bsf））調(diào)入過(guò)程程如下：：何為？？器器件和引引腳指配配器件指配配為設(shè)計(jì)輸輸入選選擇合適適的PLD器件件型號(hào)何謂引腳腳指配將設(shè)計(jì)代代碼（圖圖形）中中的端口（PORT）和PLD芯芯片的引引腳（（PIN）對(duì)應(yīng)起來(lái)來(lái)的.指配文件件MAX+PLUSII：“*.acf”QuartusII：“*.qsf”器件和引引腳指配配的方法法方法有2種在軟件的的菜單界界面中指指配修改指配配文件（是文本本文件））菜單界面面中指配修改指配配文件CHIPio_2d_lockBEGIN|iVD:INPUT_PIN=7;|iHD:INPUT_PIN=8;|iDENA:INPUT_PIN=6;|iCLK:INPUT_PIN=211;|oCLK:OUTPUT_PIN=237;|oVD:OUTPUT_PIN=234;|oHD:OUTPUT_PIN=233;|oDENA:OUTPUT_PIN=235;.................................................DEVICE=EPF10K30AQC240-2;END;........................................編譯與與排錯(cuò)錯(cuò)編譯過(guò)過(guò)程有有2種種，作作用分分別為為：語(yǔ)法編編譯：：只是是綜合合并輸輸出網(wǎng)網(wǎng)表編譯設(shè)設(shè)計(jì)文文件，，綜合合產(chǎn)生生門(mén)級(jí)級(jí)代碼碼編譯器器只運(yùn)運(yùn)行到到綜合合這步步就停停止了了編譯器器只產(chǎn)產(chǎn)生估估算的的延時(shí)時(shí)數(shù)值值完全的的編譯譯：包包括編編譯，，網(wǎng)表表輸出出，綜綜合，，配置置器件件編譯器器除了了完成成以上上的步步驟，，還要要將設(shè)設(shè)計(jì)配配置到到ALTERA的器器件中中去編譯器器根據(jù)據(jù)器件件特性性產(chǎn)生生真正正的延延時(shí)時(shí)時(shí)間和和給器器件的的配置置文件件功能仿仿真和和時(shí)序序仿真真仿真的的概念念：在設(shè)計(jì)計(jì)代碼碼下載載到芯芯片前前，在在EDA軟軟件中中對(duì)設(shè)設(shè)計(jì)計(jì)的輸輸出出進(jìn)行行波形形仿真真。常用的的2種種仿真真模式式功能仿仿真對(duì)設(shè)計(jì)計(jì)的邏邏輯功功能進(jìn)進(jìn)行仿仿真時(shí)序仿仿真對(duì)設(shè)計(jì)計(jì)的邏邏輯功功能和和信號(hào)號(hào)的時(shí)時(shí)間延延時(shí)進(jìn)進(jìn)行仿仿真。。仿真前前還要要做的的工作作輸入信信號(hào)的的建立立QuartusII軟軟件中中關(guān)于仿仿真的的原文文2種仿仿真真文件件矢量波波形文文件：：aVectorWaveformFile(.vwf)文本矢矢量文文件atext-basedVectorFile(.vec),編程與與配置置最后，，如果仿仿真也也正正確的的話話，那我們們就可可以將設(shè)計(jì)計(jì)代碼碼配配置或或者編編程到到芯芯片片中中了了編程的的文件件類(lèi)型型對(duì)于CPLD或者EPC2，，ECS1等配置置芯片片，編編程文文件擴(kuò)擴(kuò)展名名為：：“*.POF““配置的的文件件類(lèi)型型對(duì)于FPGA芯片，，配置置文件件擴(kuò)展展名為為：“*.SOF““硬件設(shè)設(shè)計(jì)和和軟件件設(shè)計(jì)計(jì)的時(shí)時(shí)間協(xié)協(xié)調(diào)軟件模模塊劃劃分，，器件件的初初步信信號(hào)確確定（（主要要是根根據(jù)需需要的的I/O引引腳的的數(shù)量量）軟件設(shè)設(shè)計(jì)，，硬件件外圍圍電路路設(shè)計(jì)計(jì)和器器件選選擇軟件仿仿真仿真完完成后后，器器件信信號(hào)的的重新新審核核，進(jìn)進(jìn)行硬硬件電電路圖圖設(shè)計(jì)計(jì)綜合調(diào)調(diào)試完成設(shè)計(jì)的的幾個(gè)個(gè)問(wèn)題題如何組組織多多個(gè)設(shè)設(shè)計(jì)文文件的的系統(tǒng)統(tǒng)？，，項(xiàng)目目的概概念。。時(shí)鐘系系統(tǒng)如如何設(shè)設(shè)計(jì)？？電路的的設(shè)計(jì)計(jì)功耗耗高速信信號(hào)的的軟件件和硬硬件設(shè)設(shè)計(jì)Theend.以下內(nèi)內(nèi)容為為正正文的的引用用，可可不不閱讀讀。常用EDA工具具軟件件EDA軟件件方面面，大大體可可以分分為兩兩類(lèi)：：PLD器件件廠商商提供供的EDA工具具。較較著名名的如如：Altera公公司的的Max+plusII和QuartusII、、Xilinx公公司的的FoundationSeries、、Latice-Vantis公司司的ispEXERTSystem。第三方方專(zhuān)業(yè)業(yè)軟件件公司司提供供的EDA工具具。常常用的的有：：Synopsys公公司的的FPGACompilerII、ExemplarLogic公公司的的LeonardoSpectrum、Synplicity公公司的的Synplify。第三方方工具具軟件件是對(duì)CPLD/FPGA生產(chǎn)產(chǎn)廠家家開(kāi)發(fā)發(fā)軟件件的補(bǔ)補(bǔ)充和和優(yōu)化化，如如通常常認(rèn)為為Max+plusII和和QuartusII對(duì)VHDL/VerilogHDL邏邏輯綜綜合能能力不不強(qiáng)，，如果果采用用專(zhuān)用用的HDL工具具進(jìn)行行邏輯輯綜合合，會(huì)會(huì)有效效地提提高綜綜合質(zhì)質(zhì)量。。ALTERA公公司司的EDA合作作伙伴伴硬件描描述語(yǔ)語(yǔ)言：：起源源是電子子電路路的文文本描描述。。最早的的發(fā)明明者：：美國(guó)國(guó)國(guó)防部部，VHDL,1983大浪淘淘沙，，為大大者二二：VHDL和VerilogHDL其他的的小兄兄弟：：ABEL、、AHDL、SystemVerilog、、SystemC。一個(gè)D觸發(fā)發(fā)器的的VHDL代碼碼例子子--VHDLcodeposition:p83_ex4_11_DFF1---------------------------------------------------------------------------------LIBARYIEEE;--USEIEEE.STD_LOGIC_1164.ALL;ENTITYDFF1ISPORT(CLK:INBIT;D:INBIT;Q:OUTBIT);ENDENTITYDFF1;ARCHITECTUREbhvOFDFF1ISBEGINPROCESS(CLK)BEGINIFCLK'EVENTAND(CLK='1')AND(CLK'LAST_VALUE='0')THEN--嚴(yán)嚴(yán)格格的CLK信號(hào)號(hào)上升升沿定定義Q<=D;ENDIF;ENDPROCESS;ENDARCHITECTUREbhv;代碼實(shí)實(shí)體（（5－－10）代碼結(jié)結(jié)構(gòu)體體（11－－20）如何使使用VHDL來(lái)來(lái)設(shè)計(jì)計(jì)電路路？VHDL設(shè)設(shè)計(jì)電電路的的的5步曲曲語(yǔ)言編編碼邏輯綜綜合功能和和時(shí)序序仿真真器件適適配器件編編程使用MAX+PLUSII軟件件的設(shè)設(shè)計(jì)過(guò)過(guò)程MAX+PLUSII設(shè)計(jì)計(jì)過(guò)程程說(shuō)明明CompilerNetlistExtractor（（編譯譯器網(wǎng)網(wǎng)表提提取器器）:通過(guò)該該過(guò)程程生成成設(shè)計(jì)計(jì)項(xiàng)目目的網(wǎng)網(wǎng)表文文件,DatabaseBuilder(數(shù)據(jù)據(jù)庫(kù)構(gòu)構(gòu)建器器):用于將將所有有的設(shè)設(shè)計(jì)文文件集集成到到項(xiàng)目目數(shù)據(jù)據(jù)庫(kù)中中如果指指定端端口的的實(shí)體體已被被抽取取.則則從從盤(pán)中中讀取取.cnf文文件信信息就就可以以了,因因而節(jié)節(jié)省了了時(shí)間間.LogicSynthesizer(邏輯輯綜合合器):選擇合合適的的邏輯輯化簡(jiǎn)簡(jiǎn)算法法,去除冗冗余和和無(wú)用用邏輯輯,有效使使用器器件的的邏輯輯資源源.Fitter(適配配器)將電路路適配配到某某個(gè)PLD器件件中。。TimingSNFExtractor(時(shí)序序SNF文文件提提取器器)產(chǎn)生用用于時(shí)時(shí)序仿仿真的的網(wǎng)表表文件件Assembler（匯匯編器器）產(chǎn)生用用于器器件編編程的的目標(biāo)標(biāo)代碼碼其他的的HDL綜綜合工工具Altera公公司MAX+PLUSII10.2（已經(jīng)經(jīng)停止止發(fā)行行，新新器件件不支支持））QUARTUSII5.0（推薦薦使用用）Xilinx公公司司ISE7.0：Xilinx公司司集成成開(kāi)發(fā)發(fā)的工工具Foundation:Xilinx公公司早早期開(kāi)開(kāi)發(fā)工工具，，逐步步被ISE取代代ISEWebpack：Webpack是xilinx提提供的的免費(fèi)費(fèi)開(kāi)發(fā)發(fā)軟件件，功功能比比ISE少少一些些，可可以從從xilinx網(wǎng)站站下載載有了HDL語(yǔ)言言后？？硬件設(shè)設(shè)計(jì)人人員的工作作過(guò)程程已經(jīng)類(lèi)類(lèi)似似與軟件設(shè)設(shè)計(jì)人人員，那么么這種模模式的的好處處是？？讓我們先先看看看原來(lái)來(lái)是如如何做做的－－>CompilerNetlistExtractor

（編編譯器網(wǎng)表表提取器））TheCompilermodulethatconvertseachdesignfileinaproject(oreachcellofanEDIFInputFile)intoaseparatebinaryCNF.Thefilename(s)oftheCNF(s)arebasedontheprojectname.ExampleTheCompilerNetlistExtractoralsocreatesasingleHIFthatdocumentsthehierarchicalconnectionsbetweendesignfiles.Thismodulecontainsabuilt-inEDIFNetlistReader,VerilogNetlistReader,VHDLNetlistReader,andconvertersthattranslateADFsandSMFsforusewithMAX+PLUSII.Duringnetlistextraction,thismodulecheckseachdesignfileforproblemssuchasduplicatenodenames,missinginputsandoutputs,andoutputsthataretiedtogether.返回DatabaseBuilder(數(shù)據(jù)庫(kù)構(gòu)構(gòu)建器):TheCompilermodulethatbuildsasingle,fullyflattenedprojectdatabasethatintegratesallthedesignfilesinaprojecthierarchy.TheDatabaseBuilderusestheHIFtolinktheCNFsthatdescribetheproject.BasedontheHIFdata,theDatabaseBuildercopieseachCNFintotheprojectdatabase.EachCNFisinsertedintothedatabaseasmanytimesasitisusedwithintheoriginalhierarchicalproject.Thedatabasethuspreservestheelectricalconnectivityoftheproject.TheCompilerusesthisdatabasefortheremainderofprojectprocessing.EachsubsequentCompilermoduleupdatesthedatabaseuntilitcontainsthefullyoptimizedproject.Inthebeginning,thedatabasecontainsonlytheoriginalnetlists;attheend,itcontainsafullyminimized,fittedproject,whichtheAssemblerusestocreateoneormorefilesfordeviceprogramming.Asitcreatesthedatabase,theDatabaseBuilderexaminesthelogicalcompletenessandconsistencyoftheproject,andchecksforboundaryconnectivityandsyntacticalerrors(e.g.,anodewithoutasourceordestination).Mosterrorsaredetectedandcanbeeasilycorrectedatthisstageofprojectprocessing.返回LogicSynthesizerTheCompilermodulethatsynthesizesthelogicinaproject'sdesignfiles.UsingthedatabasecreatedbytheDatabaseBuilder,theLogicSynthesizercalculatesBooleanequationsforeachinputtoaprimitiveandminimizesthelogicaccordingtoyourspecifications.ForprojectsthatuseJKorSRflipflops,theLogicSynthesizercheckseachcasetodeterminewhetheraDorTflipflopwillimplementtheprojectmoreefficiently.DorTflipflopsaresubstitutedwhereappropriate,andtheresultingequationsareminimizedaccordingly.TheLogicSynthesizeralsosynthesizesequationsforflipflopstoimplementstateregistersofstatemachines.AnequationforeachstatebitisoptimallyimplementedwitheitheraDorTflipflop.Ifnostatebitassignmentshavebeenmade,orifanincompletesetofstatebitassignmentshasbeencreated,theLogicSynthesizerautomaticallycreatesasetofstatebitstoencodethestatemachine.Theseencodingsarechosentominimizetheresourcesused.返回Fitter（適配配器）TheCompilermodulethatfitsthelogicofaprojectintooneormoredevices.UsingthedatabaseupdatedbythePartitioner,theFittermatchesthelogicrequirementsoftheprojectwiththeavailableresourcesofoneormoredevices.Itassignseachlogicfunctiontothebestlogiccelllocationandselectsappropriateinterconnectionpathsandpinassignments.TheFitterattemptstomatchanyresourceassignmentsmadefortheprojectwiththeresourcesonthedevice.Ifitcannotfindafit,theFitterallowsyoutooverridesomeorallofyourassignmentsorterminatecompilation.TheFittermodulegeneratesaFitFilethatdocumentspin,buriedlogiccell,chip,clique,anddeviceassignmentsmadebytheFittermoduleinthelastsuccessfulcompilation.Eachtimetheprojectcompilessuccessfully,theFitFileisoverwritten.Youcanback-annotatetheassignmentsinthefiletopreservetheminfuturecompilations.返回TimingSNFExtractor(時(shí)序SNF文件提提取器)TheCompilermodulethatcreatesatimingSNFcontainingthelogicandtiminginformationrequiredfortimingsimulation,delayprediction,andtiminganalysis.TheTimingSNFExtractoristurnedonwiththeTimingSNFExtractorcommand(Processingmenu).ItisalsoturnedonautomaticallywhenyouturnontheEDIFNetlistWriter,VerilogNetlistWriter,orVHDLNetlistWritercommand(Interfacesmenu).TheTimingSNFExtractorcannotbeturnedonatthesametimeastheFunctionalSNFExtractorortheLinkedSNFExtractor.AtimingSNFdescribesthefullyoptimizedcircuitafteralllogicsynthesisandfittinghavebeencompleted.Regardlessofwhetheraprojectispartitionedintomultipledevices,thetimingSNFdescribesaprojectasawhole.Therefore,timingsimulationandtiminganalysis(includingdelayprediction)areavailableonlyfortheprojectasawhole.Neithertimingsimulationnorfunctionaltestingisavailableforindividualdevicesinamulti-deviceproject.Functionaltestingisavailableonlyforasingle-deviceproject.返回Assembler（匯編器器）TheCompilermodulethatcreatesoneormoreprogrammingfilesforprogrammingorconfiguringthedevice(s)foraproject.TheAssemblermodulecompletesprojectprocessingbyconvertingtheFitter'sdevice,logiccell,andpinassignmentsintoaprogrammingimageforthedevice(s),intheformofoneormorePOFs,SOFs,HexFiles,TTFs,JamFiles,JBCFiles,and/orJEDECFiles.POFsandJEDECFilesarealwaysgenerated;SOFs,HexFiles,andTTFsarealwaysgeneratediftheprojectusesACEX1K,FLEX6000,FLEX8000orFLEX10Kdevices;andJamFilesandJBCFilesarealwaysgeneratedforMAX9000,MAX7000B,MAX7000AEorMAX3000Aprojects.IfyouturnontheEnableJTAGSupportoptionintheClassic&MAXGlobalProjectDeviceOptionsdialogbox(Assignmenu)ortheClassic&MAXIndividualDeviceOptionsdialogbox,theAssemblerwillalsogenerateJamFilesandJBCFilesforMAX7000AorMAX7000Sprojects.Aftercompilation,youcanalsouseSOFstocreatedifferenttypesoffilesforconfiguringFLEX6000,FLEX8000andFLEX10KdeviceswithConvertSRAMObjectFiles(Filemenu).TheprogrammingfilescanthenbeprocessedbytheMAX+PLUSIIProgrammerandtheMPUorAPUhardwaretoproduceworkingdevices.SeveralotherprogramminghardwaremanufacturersalsoprovideprogrammingsupportforAlteradevices.返回SimulationModeFunctionalSimulatesthebehaviorofflattenednetlistsextractedfromthedesignfiles.YoucanuseTclcommandsandscriptstocontrolsimulationandtoprovidevectorstimuli.YoucanalsoprovidevectorstimuliinaVectorWaveformFile(.vwf)oratext-basedVectorFile(.vec),althoughtheSimulatorusesonlythesequenceoflogiclevelchanges,andnottheirtiming,fromthevectorstimuli.Thistypeofsimulationalsoallowsyoutochecksimulationcoverage(theratioofoutputportsactuallytogglingbetween1and0duringsimulation,comparedtothetotalnumberofoutputportspresentinthenetlist).TimingUsesafullycompilednetlistthatincludesestimatedoractualtiminginformation.YoucanuseTclcommandsandscriptstocontrolsimulationandtoprovidevectorstimuli.YoucanalsoprovidevectorstimuliinaVectorWaveformFile(.vwf)oratext-basedVectorFile(.vec).Thistypeofsimulationalsoallowsyoutochecksetupandholdtimes,detectglitches,andchecksimulationcoverage(theratioofoutputportsactuallytogglingbetween1and0duringsimulation,comparedtothetotalnumberofoutputportspresentinthenetlist).TimingusingFastTimingModelPerformsatimingsimulationusingtheFastTimingModeltosimulatefastestpossibletimingconditionswiththefastestdevicespeedgradeMegafunctions/LPMArithmeticComponentsGatesI/OComponentsMemoryCompilerParallelFlashLoaderMegafunctionSignalTapIILogicAnalyzerMegafunctionStorageComponentsArithmeticComponentsaltaccumulatedivide*altfp_add_sublpm_absaltfp_multlpm_add_subaltmemmultlpm_comparealtmult_accumlpm_counteraltmult_addlpm_dividealtsqr