分析adi tigersharc培訓(xùn)ts201處理器

1、System Design2Resources: ADSP-TS201S Data SheetOverview of Architecture including feature descriptionsPin Descriptions: Type, FunctionElectrical Characteristics: DC loading, Supply CurrentAC Signal SpecificationsInput setup and holdOutput valid and holdOutput enable/disableAsynchronous minimum pulse

2、 widthsCapacitive Loading nominal 30pF, De-rating curvesPower CalculationsInitial GuidelinesPackage dimensions and pinoutThermal Characteristics3ResourcesTigerSHARC DSP Hardware Specification (ADSP-TS201S)Cluster Bus, Link Ports, I/O Pins, etc.Detail Signaling protocols and sequence of eventsData sh

3、eet does not tell the whole storyApplication Notes / Whitepapers:Plexus TigerSHARC ADSP-201 MP Analysis reportSimulations and timing analysis showing fully functional cluster bus operation for 6 TigerSHARCs, SDRAM, and a host running at 100MHzPhysical implementation description including via fan-out

4、, system clock distribution, PCB stackup, and placement and routingXilinx/Altera Link Port ModuleVerilog/VHDL module for TS201S link port compatible interface for Xilinx/Altera FPGAs4ADSP-TS2015Clock Driver ExampleClockBuffer Drive Impedance = 10 WA separate buffer and transmission line is needed fo

5、r each groupof processors that are further than 4 inches from each other.50 W Transmission Line40 W50 W Transmission Line40 W50 W Transmission Line40 WACTQ240 Octal Inverter(National Semiconductor)orIDT49FCT805/AorCY7C992ANALOGDEVICESADSP-TS101SSHARCT I G E R TMANALOGDEVICESADSP-TS101SSHARCT I G E R

6、 TMANALOGDEVICESADSP-TS101SSHARCT I G E R TM6TDI1645123406446436420123PINPINTDOBoundary RegistersInstruction RegisterBypass RegisterADSP-TS101SADSP-TS101STCKTMSJTAG ICE oranother deviceJTAG ICE oranother deviceJTAG Scan PathJTAG (EE-68)8JTAG Header layoutThe Emulation JTAG Header:JTAG port consists

7、of:TDOTDI/TRSTTCKTMS/EMUSignals named B are meant for boundary board level test9JTAG header connectionsJTAG header without boundary scan circuitry10JTAG chain for Multi Processing Systems11Power Cycling GuidelinesIf possible, use same power outlet for PC and targetPower On:Power on target powerAttac

8、h probe to targetActivate VisualDSP+ environmentPower Off:Close VisualDSP+ environmentDetach probe from targetPower off targetMulti-Processor Break Point13MPBP ImplementationSet the TS201s running, and monitor the JTAG EMU signal via enhanced pod logicOnce the EMU signal activates, Stop JTAG TCLK, a

9、nd toggle JTAG TMSAll processors halt within 15 Clock Cycles 300MHzOnly limitation is that Single and Multi-Processor Break Points cannot be mixed. Its one or the other.14Block Diagram15Future Multi-Processor (MP) BreakpointsCandidate for inclusion in the Rhine processorSynchronized Halt of all DSPs in the JTAG chainBi-Directional Multi-Processor Bre