計(jì)算機(jī)系統(tǒng)結(jié)構(gòu)英文課件

1、Chapter 2: Computer-System StructuresComputer System OperationI/O StructureStorage Structure Storage Hierarchy Hardware Protection General System Architecture1Uniprocessor Computer-System Architecturecontroller2ControllerA device controller is a part of a computer system that makes sense of the sign

2、als going to, and coming from the CPU processor. Each device controller is in charge of a particular device type. Device controllers use binary and digital codes. Each device controller has a local buffer and a command register. I/O is from the device to local buffer of controller. I/O devices and t

3、he CPU can execute concurrently. Device controllers communicate with the CPU by causing an interrupt. 3Functions of device controllersReceiving and understanding the commands of CPUimplementing the data exchange between CPU and devices (format conversion)Recording the status of device to be queried

4、by CPU (status register)Identifying the address of each device4Common Functions of InterruptsInterrupts transfers control to the interrupt service routine generally, through the interrupt vector, which contains the addresses of all the service routines. 通常中斷通過(guò)中斷向量把控制傳給中斷服務(wù)程序Interrupt architecture mu

5、st save the address of the interrupted instruction. Incoming interrupts are disabled while another interrupt is being processed to prevent a lost interrupt.A trap is a software-generated interrupt caused either by an error or a user request.An operating system is interrupt driven.5Interrupt Handling

6、The operating system preserves the state of the CPU by storing registers and the program counter. Determines which type of interrupt has occurred:polling vectored interrupt system Separate segments of code determine what action should be taken for each type of interrupt 6Interrupt Time Line For a Si

7、ngle Process Doing Output (P21)7Chapter 2: Computer-System StructuresComputer System OperationI/O StructureStorage Structure Storage Hierarchy Hardware Protection General System Architecture8I/O Structure1. No channel (IOP):pollingCPU-OrientedCPURAMCCCCDisk DrivePrinterDeviceSystem Bus9I/O Structure

8、2. channel (IOP):Memory-OrientedC1IOP1CPURAMIOP2C2C3C4Device1Device2Device3Device4Device5Device6Device710How to output the data in RAM ?Construct a channel programSubmit the channel program to the corresponding IOP via RAMThe IOP executes the channel programThe IOP notifies CPU by causing an interru

9、pt upon completion A channel program is a sequence of I/O instructions executed by the input/output channel processor (IOP). The channel program consists of one or more channel command words. 11Two I/O MethodsSynchronousAsynchronous12Synchronous I/OAfter I/O starts, control returns to user program o

10、nly upon I/O completion. wait instruction idles the CPU until the next interruptwait loop (contention for memory access). At most one I/O request is outstanding at a time, no simultaneous I/O processing. 13Asynchronous I/OAfter I/O starts, control returns to user program, without waiting for I/O com

11、pletion. System call request to the operating system to allow user to wait for I/O completion. Device-status table contains entry for each I/O device indicating its type, address, and state. Operating system indexes into I/O device table to determine device status and to modify table entry to includ

12、e interrupt.The main advantage of asynchronous I/O is increased system efficiency.14Device-Status Table15I/O StructureProgrammed input/output (PIO) is a method of transferring data between the CPU and a peripheral. In general, programmed I/O happens when software running on the CPU uses instructions

13、 that access I/O address space to perform data transfers to or from an I/O device.With Direct Memory Access (DMA) , the CPU would initiate the transfer, do other operations while the transfer is in progress, and receive an interrupt from the DMA controller once the operation has been done. 16Direct

14、Memory Access (DMA) StructureUsed for high-speed I/O devices able to transmit information at close to memory speeds.Device controller transfers blocks of data from buffer storage directly to main memory without CPU intervention.Only one interrupt is generated per block, rather than the one interrupt

15、 per byte.17Chapter 2: Computer-System StructuresComputer System OperationI/O StructureStorage Structure Storage Hierarchy Hardware Protection General System Architecture18Storage StructureMain memory only large storage media that the CPU can access directly. Secondary storage extension of main memo

16、ry that provides large nonvolatile storage capacity.Magnetic disks rigid metal or glass platters covered with magnetic recording materialDisk surface is logically divided into tracks, which are subdivided into sectors.The disk controller determines the logical interaction between the device and the

17、computer. 19Moving-Head Disk MechanismPositioning time (random-access time)seek time rotational latencytransfer timeTo decrease mechanical delays, i.e., the seek time and the rotational latency Disk Scheduling Algorithm20Chapter 2: Computer-System StructuresComputer System OperationI/O StructureStor

18、age Structure Storage Hierarchy Hardware Protection General System Architecture21Storage HierarchyStorage systems organized in hierarchy.Speed cost volatility Caching copying information into faster storage system; main memory can be viewed as a fast cache for secondary storage.22Storage-Device Hier

19、archy寄存器緩存主存儲(chǔ)器電子盤磁盤光盤磁帶23Chapter 2: Computer-System StructuresComputer System OperationI/O StructureStorage Structure Storage Hierarchy Hardware Protection General System Architecture24Hardware ProtectionDual-Mode OperationI/O ProtectionMemory ProtectionCPU Protection25Dual-Mode OperationSharing sys

20、tem resources requires operating system to ensure that an incorrect program cannot cause other programs to execute incorrectly.Provide hardware support to differentiate between at least two modes of operations. 至少在兩個(gè)運(yùn)行模式之間提供硬件支持1.User mode execution done on behalf of a user.2.Monitor mode (also supe

21、rvisor mode or system mode) execution done on behalf of operating system. 26userWhen an interrupt or fault occurs hardware switches to monitor mode.Dual-Mode Operation (Cont.)Mode bit added to computer hardware (PSW) to indicate the current mode: monitor (0) or user (1). Privileged instructions can

22、be issued only in monitor mode. 特權(quán)指令只能在管態(tài)下執(zhí)行 monitorInterrupt/faultset user mode27I/O ProtectionPrivileged instructionsAll I/O instructions are privileged instructions.Enable/disable interruptsModify address registersSet PSWMust ensure that a user program could never gain control of the computer in

23、monitor mode.28Memory ProtectionMust provide memory protection at least for the interrupt vector and the interrupt service routines.In order to have memory protection, add two registers that determine the range of legal addresses a program may access:base register holds the smallest legal physical m

24、emory address.limit register contains the size of the rangeMemory outside the defined range is protected.29A Base And A limit Register Define A Logical Address Space30Hardware ProtectionWhen executing in monitor mode, the operating system has unrestricted access to both monitor and users memory.The

25、load instructions for the base and limit registers are privileged instructions. 31CPU ProtectionTimer interrupts computer after specified period to ensure operating system maintains control. Timer is decremented every clock tick.When timer reaches the value 0, an interrupt occurs. Timer commonly used to implement time sharing.Timer also used to