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1、Fundamentals of the LIN Bus SystemREM/EB Petra Kraft Edited for GT by U. Hoffmann7/28/2022REM/EB Petra Kraft2ContentsThe LIN bus system AdvantagesHistoryLIN Specification PackagePhysical LayerCommunication in the NetworkStructure of Messages - The LIN Frame Fault Detection and HandlingLIN Configurat

2、ion LanguageSelection7/28/2022REM/EB Petra Kraft3Standardized communication protocolSingle-wire bus, low-cost solution Transfer rates up to 20 kbaudsBased on serial interface (UART/SCI)Applications today:Link between actuators and sensors CAN B (I-CAN): Link between switches, control panels and moto

3、rsCAN C (E-CAN): Interface motor electronics and alternatorSource: LIN Spec 1.2= Local Interconnect NetworkSelection7/28/2022REM/EB Petra Kraft4Advantages of LIN use Open standardReduced diversity of serial interface protocolsFewer connectors and wiresLow cost thanks to single-wire communication and

4、 synchronization (no quartz for slaves)Low quiescent currentGuaranteed latency times for signal transmission predictable behaviorSleep and wake up functions(central sleep via master, wake-up from all nodes)Tool-supported development, simulation optionsStandard hardware and software Selection7/28/202

5、2REM/EB Petra Kraft5History Oct. 1998Initiation of working group with seven partners:automotive manufacturers, tool makers, semiconductor producersJuly 1999Specification Revision 1.0Aug. 1999DC Management requires use of LIN as designstandard Mar. 2000Presentation of LIN to press in DetroitFrom 2001

6、First production models with LINSelection7/28/2022REM/EB Petra Kraft6LIN Specification Package (Revision 1.2) LIN Protocol Specification: Description of Physical Layer and Data Link LayerLIN Configuration LanguageDefinition of format for configuration files (ldf file)LIN APIDescription of interface

7、between network and applicationSource: LIN Spec 1.27/28/2022REM/EB Petra Kraft7Physical Layer (Revision 1.2)Open collector circuitBus length: 0 bis 40 m Terminating resistance, master: 1 kohms, Terminating resistance, slave: 20 - 47 kohmsSerial interface (UART/SCI)Level on bus line: Recessive (1) -

8、min. 80% UBAT at transmission, min. 60% UBAT at receptionDominant (0) - max. 20% UBAT at transmission, max. 40% UBAT at receptionSource: LIN Spec 1.2LINSelection7/28/2022REM/EB Petra Kraft8Communication in the LIN Network Master Task: Communication control(ID, synchronization, scheduling)Slave Task:

9、 Data transmission(dumb, response when ID sent from master) Central bus access control based on message addressingMaster ECUSlave ECUSlave ECUMaster TaskSlave TaskSlave TaskSlave Task7/28/2022REM/EB Petra Kraft9Details of Communication ProcessSource: LIN Spec 1.2Master transmits - HEADERSlave answer

10、s - RESPONSESelection7/28/2022REM/EB Petra Kraft10Automatic clock detection:Transfer of clock frequency via 5 falling edges(recessive to dominant) Addressing of message:Identifier: ID0 -ID3Length check (opt.): ID4, ID5Parity bit: P0, P1Data exchangeStart bit (dominant)Data: Bits 0 - 7Stp bit (recess

11、ive) Byte synchronizationCheck for bit errorAdd with Carryacross all date bytesLIN FrameHeaderStructure of LIN Frames (Revision 1.2)SynchBreakSynchFieldIdentFieldResponseData Field0 DataField7DataField6DataField5DataField4DataField3DataField2DataField1CRCSynch BreakSynch Break low phase Synch BreakD

12、elimiterSynch FieldStart 0 1 2 3 4 5 6 7 Stop Bit Bit Identification FieldID0ID1ID2ID3ID4ID5P0P1Start 0 1 2 3 4 5 6 7 Stop Bit Bit Data FieldID0ID1ID2ID3ID4ID5P6P1Start 0 1 2 3 4 5 6 7 Stop Bit Bit Check Sum FieldC0C1C2C3C4C5C6C7Start 0 1 2 3 4 5 6 7 Stop Bit Bit In-frame response spaceInterbyte spa

13、ceHard Synchronization: Synch Break Low Phase: Minimum 13 dominant bits Synch Break Delimiter: Minimum 1 recessive bitSelection7/28/2022REM/EB Petra Kraft11Fault Detection and HandlingParity verificationCheck sum verificationBus monitoringResponding verificationBus activityNo error signalingFaulty L

14、IN messages considered not transmitted and discardedFault handling must be defined in the application layerSelection7/28/2022REM/EB Petra Kraft12LIN Configuration Language Standardized exchange format for LIN networkFormat: ldf fileSyntax and semantics defined in LIN Specification PackageComponents:

15、Protocol version, language version, transfer rateNodes: node name, slave or master (jitter, time-base)Signals: signal name, size, Init_Value, sender, receiverFrames: frame name, Frame_ID, sender, size, list of signals with offsetSchedule table: schedule table name, list of frames with frame time Sig

16、nal groups: signal group name, size, list of signals with offsetSignal encoding types: type name, description 7/28/2022REM/EB Petra Kraft13LDF File /* * */* */* Description: LIN Description file */* Date: 11.21.2002 */* Project: DBE_Auswertung */* Release: DBE_01 */* Configuration: Config_DBE */* Ne

17、twork: DBE_LIN */* */* * */LIN_description_file;LIN_protocol_version = 1.2;LIN_language_version = 1.2;LIN_speed = 19.200 kbps;Nodes Master : ZGW_MASTER_DBE, 3.000 ms, 0.000 ms; Slaves: LRS_SLAVE, DBE_SLAVE, WISCHER_SLAVESignals FEHBIT : 8, 0, DBE_SLAVE, ZGW_MASTER_DBE; SCH_ST : 8, 0, DBE_SLAVE, ZGW_

18、MASTER_DBE; RLS_ST : 16, 0, LRS_SLAVE, ZGW_MASTER_DBE; WISCH_ST : 8, 0, WISCHER_SLAVE, ZGW_MASTER_DBE; KL_58D : 8, 0, ZGW_MASTER_DBE, DBE_SLAVE; WISCH_ANF : 8, 0, ZGW_MASTER_DBE, WISCHER_SLAVE; RLS_ANF : 16, 0, ZGW_MASTER_DBE, LRS_SLAVE; SHD_ALARM : 1, 0, ZGW_MASTER_DBE, DBE_SLAVE; SHD_AUF_K : 1, 0,

19、 ZGW_MASTER_DBE, DBE_SLAVE; SHD_ZU_K : 1, 0, ZGW_MASTER_DBE, DBE_SLAVE; HD_AUF_K : 1, 0, ZGW_MASTER_DBE, DBE_SLAVE; KL_15_EIN : 1, 0, ZGW_MASTER_DBE, DBE_SLAVE; KL_15C_EIN : 1, 0, ZGW_MASTER_DBE, DBE_SLAVE;Frames DBE_SLAVE_Ifc1_Frm2_ba : 1, DBE_SLAVE, 2 FEHBIT, 8; SCH_ST, 0; LRS_SLAVE_Ifc1_Frm3_ba : 2, LRS_SLAVE, 2 RLS_ST, 0; WISCHER_SLAVE_Ifc1_Frm4_