數(shù)字電路英文版第八單元知識(shí)分享

1、第一頁，共123頁。Astable (非穩(wěn)態(tài)的非穩(wěn)態(tài)的 ) Hold-time ( 保持時(shí)間保持時(shí)間 )Asynchronous ( 異步異步 )Bistable ( 雙穩(wěn)態(tài)雙穩(wěn)態(tài) ) Clear ( 清零清零 )D flip-flop ( D 觸發(fā)器觸發(fā)器 ) Edge-triggered flip-flop ( 邊沿觸發(fā)器邊沿觸發(fā)器 )Feed-back ( 反饋反饋 ) Hysteresis ( 遲滯遲滯(chzh) ) J-K flip-flop ( JK觸發(fā)器觸發(fā)器 )Latch ( 鎖存器鎖存器 ) Master-slave flip-flop ( 主從觸發(fā)器主從觸發(fā)器 )第二頁，

2、共123頁。Monostable ( 單穩(wěn)態(tài)單穩(wěn)態(tài) ) One-shot ( 單穩(wěn)單穩(wěn) )Preset ( 預(yù)置預(yù)置1 ) RESET ( 置置0 )SET ( 置置1 ) Set-up time ( 設(shè)置時(shí)間設(shè)置時(shí)間 )S-R flip-flop ( RS觸發(fā)器觸發(fā)器 ) Synchronous ( 同步同步(tngb) )Timer ( 計(jì)時(shí)器計(jì)時(shí)器 ) Toggle ( 觸發(fā)觸發(fā) , 計(jì)數(shù)計(jì)數(shù) )第三頁，共123頁。KEY TERMS Astable Having no stable state. An astable multivibrator oscillates between t

3、wo quasistable states.Asynchronous Having no fixed time relationship.Bistable Having two stable states. Flip-flops and latches are bistable multivibrators.第四頁，共123頁。Clear An asynchronous input used to reset a flip-flop ( make the Q output 0 ).D flip-flop A type of bistable multivibrator in which the

4、 output assumes the state of the D input on the triggering edge of a clock pulse.第五頁，共123頁。Edge-triggered flip-flop A type of flip-flop in which the data are entered and appear on the output on the same clock edge.Feedback The output voltage or a portion of it that is connected back to the input of

5、a circuit.第六頁，共123頁。Hold time The time interval required for the control levels to remain on the inputs to a flip-flop after the triggering edge of the clock in order to reliably activate the device.Latch A bistable digital circuit used for storing a bit.第七頁，共123頁。Hystersis A characteristic of a thr

6、eshold-triggered circuit, such as the Schmitt trigger, where the device turns on and off at different input levels.J-K flip-flop A type of flip-flop that can operate in the SET, RESET, no-change, and toggle modes.第八頁，共123頁。Master-slave flip-flop A type of flip-flop in which the input data are entere

7、d into the device on the leading edges of clock pulses and apper at the output on trailing edges. Master-slave flip-flops have, for the most part, been replaced by edge-triggered types.第九頁，共123頁。Monostable Having only one stable state. A monostable multivibrator, commonly called a one-shot, produces

8、 a single pulse in response to a triggering input.One-shot A monostable multivibrator.Preset An asynchronous input used to set a flip-flop ( make the Q output 1 ).第十頁，共123頁。RESET The state of a flip-flop or latch when the output is 0; the action of producing a RESET state.SET The state of a flip-flo

9、p or latch when the output is 1; the action of producing a SET state.第十一頁，共123頁。Set-up time The time interval required for the control levels to be on the inputs to a digital circuit, such as a flip-flop, prior to the triggering edge of a clock pulse.S-R flip-flop A SET-RESET flip-flop.第十二頁，共123頁。Sy

10、nchronous Having a fixed time relationship.Toggle The action of a flip-flop when it changes state on each clock pulse.第十三頁，共123頁。The latch is a type of temporary storage device that has two stable states (bistable) and is normally placed in a category separate from that of flip-flop. 2.第十四頁，共123頁。 L

11、atches are basically similar to flip-flops because they are bistable devices that can reside in either of two states using a feedback arrangement, in which the outputs are connected back to the opposite inputs. The main difference between latches and flip-flop is in the method used for changing thei

12、r state.3.第十五頁，共123頁。The S-R (SET-RESET) LatchRSQQActive-HIGH input S-R latch ( NOR S-R Latch )4.第十六頁，共123頁。QQSR5VRRRRRR5.第十七頁，共123頁。SRQQ(b) Active-LOW input S-R latch ( NAND S-R Latch )6.第十八頁，共123頁。SRQQWhen Q is HIGH, Q is LOW, and when Q is LOW, Q is HIGH.7.第十九頁，共123頁。第二十頁，共123頁。第二十一頁，共123頁。 Input

13、 Outputs S R Q Q Comments 1 1 NC NC No change.latch remains in present state. 0 1 1 0 Latch SET . 1 0 0 1 Latch RESET . 0 0 1 1 Invalid condition . TABLE 8-1Truth table for an active-LOW input S-R latch.8.第二十二頁，共123頁。 Input Outputs S R Q Q Comments 0 0 NC NC No change.latch remains in present state.

14、 0 1 0 1 Latch RESET . 1 0 1 0 Latch SET . 1 1 0 0 Invalid condition . TABLE 8-1Truth table for an active-HIGH input S-R latch.第二十三頁，共123頁。SRQQActive-HIGH input S-R latchSRQQ(b) Active-LOW input S-R latchSR9.第二十四頁，共123頁。EXAMPLE 8-1SRQ10.第二十五頁，共123頁。EXAMPLE 8-1: Related Problem Determine the Q output

15、 of an active-HIGH input S-R latch if the waveforms in above are inverted and applied to the input.SRQ第二十六頁，共123頁。 Although S remains LOW for only a very short time before the switch bounce, this is sufficient to set the latch. 第二十七頁，共123頁。The Gated S-R LatchSRQQENSREN(a) Logic diagram(b) Logic symb

16、ol12.The latch will not change until EN is HIGH, but as long as it remains HIGH, the output is controlled by the state of the S and R inputs.第二十八頁，共123頁。EXAMPLE 8-2 Determine the output waveform if the inputs shown in Fig.8-9 are applied to a gated S-R latch that is initially RESET.SRQEN13.Fig.8-9(a

17、)(b)第二十九頁，共123頁。EXAMPLE 8-2: Related Problem Determine the Q output of a gated S-R latch if the S and R inputs in Fig. 8-9 (a) are inverted.SRQEN13.Fig.8-9(a)(b)第三十頁，共123頁。The Gated D LatchDQQENDEN(a) Logic diagram(b) Logic symbol14.QQQn+1 = D( S )( R )第三十一頁，共123頁。EXAMPLE 8-3 Determine the Q output

18、waveform if the inputs shown in Fig.8-11 (a) are applied to a gated D latch, which is initially RESET.DQEN15.Fig.8-11(a)第三十二頁，共123頁。EXAMPLE 8-3 Related Problem Determine the Q output of the gated D latch, if the D input in Fig.8-11 ( a ) is reverted.DQEN(a)第三十三頁，共123頁。 Input Outputs D EN Q Q Comment

19、s 0 1 0 1 RESET . 1 1 1 0 SET . X 0 Q0 Q0 No changeTruth table16.Qn+1 = D第三十四頁，共123頁。Flip-flops are synchronous bistable devices, also known as bistable multivibrators. In this case, the term synchronous means that the output changes state only at a specified point on a triggering input called the c

20、lock( CLK ) which is designated as a control input C; that is, changes in the output occur in synchronization with the clock.17.第三十五頁，共123頁。Edge-triggered flip-flop:SRQQCDQQCJKQQCSRQQCDQQCJKQQCTop: positive edge-triggered; bottom: negative edge-triggered.18.第三十六頁，共123頁。The Edge-Triggered S-R Flip-Fl

21、op:SRQQC Inputs Outputs 0 0 X Q0 Q0 No change S R CLK Q Q Comments 0 1 0 1 RESET 1 0 1 0 SET 1 1 ? ? Invalid19.Qn+1 = S + RQn ( SR = 0 condition )第三十七頁，共123頁。EXAMPLE 8-4SRQQC123456SRQCLK20.第三十八頁，共123頁。EXAMPLE 8-4 Determine Q for the S and R inputs in Fig. 8-16 ( a) if the flip-flop is a negative edg

22、e-triggered device.123456SRQCLK第三十九頁，共123頁。第四十頁，共123頁。PulsetransitiondetectorQQSRCLK01HIGH (1)LOW (0)01010101This gate is disabledBecause R is LOW.This gate is enabled.G4G3G2G1HIGHFig. 8-1821.第四十一頁，共123頁。PulsetransitiondetectorQQSRCLK01HIGH (1)LOW (0)01010101This gate is disabledbecause S is LOW.Thi

23、s gate is enabled.G4G3G2G1HIGHFig. 8-1922.第四十二頁，共123頁。The Edge-Triggered D Flip-Flop:SQQCDCLK Inputs Outputs 1 1 0 SET(1) D CLK Q Q Comments 0 0 1 RESET(0)23.R第四十三頁，共123頁。EXAMPLE 8-5DQQC1234QDCLK24.第四十四頁，共123頁。1234QDCLKEXAMPLE 8-5 Related Problem Determine the Q output for the D flip-flop if the D i

24、nput in Fig. 8-21 ( a ) is reversed.第四十五頁，共123頁。1234QDCLKEXAMPLE 8-5 Related Problem Determine the Q output for the D flip-flop if the D input in Fig. 8-21 ( a ) is reversed.第四十六頁，共123頁。The Edge-Triggered J-K Flip-Flop:JKQQC Inputs Outputs 0 0 Q0 Q0 No change J K CLK Q Q Comments 0 1 0 1 RESET 1 0 1

25、 0 SET 1 1 Q0 Q0 Toggle25.Qn+1 = J Qn + KQn第四十七頁，共123頁。 Inputs Output 0 0 0 0 J K Qn Qn+1 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0Qn+1 = J Qn + KQn1JKQn00011110010123456711110J= X K= 1J= 1 K= XJ= X K= 0J= 0 K= X第四十八頁，共123頁。 Inputs Output 0 0 0 0 S R Qn Qn+1 0 0 1 1 0 1 0 0 0 1 1 0 1 0

26、 0 1 1 0 1 1 1 1 0 X 1 1 1 XSRQn000111100101234567110S= 0 R= 1S= 1 R= 0S= X R= 0S= 0 R= X11XXQn+1 = S + RQn ( SR = 0 condition )第四十九頁，共123頁。PulsetransitiondetectorQQJKA simplified logic diagram for a positive edge-triggered J-K flip-flop.G4G3G2G1CLK26.第五十頁，共123頁。PulsetransitiondetectorQQJKTransition

27、s illustrating the toggle when J=1 and K=1.G4G3G2G1CLK123HIGHHIGH12312312327.第五十一頁，共123頁。EXAMPLE 8-612345CLKJKQJKQQCCLKToggleNochangeResetSetSet28.Fig. 8-24( a )第五十二頁，共123頁。EXAMPLE 8-6 Related Problem Determine the Q output for the J-K flip-flop if the J-K inputs in Fig. 8-24 ( a ) are reversed.1234

28、5CLKJKQFig. 8-24第五十三頁，共123頁。EXAMPLE 8-6 Related Problem Determine the Q output for the J-K flip-flop if the J-K inputs in Fig. 8-24 ( a ) are reversed.12345CLKJKQToggleNochangeResetSetReset第五十四頁，共123頁。Asynchronous Preset and Clear InputsJKQQCPRECLRLogic symbol for a J-K flip-flop with active-LOW pre

29、set and clear inputs.29.第五十五頁，共123頁。PulsetransitiondetectorPRECLRQQJKCLKLogic diagram for a basic J-K flip-flop with active-LOW preset and clear.30.第五十六頁，共123頁。JKQQCPRECLREXAMPLE 8-8: For the positive edge-triggered J-K flip-flop, determine Q.HIGH31.第五十七頁，共123頁。213456789CLRPREQPresetToggleClear32.第五

30、十八頁，共123頁。EXAMPLE 8-8: Related Problem If you interchange the PRE and CLR waveforms in Fig. 8-28 ( a ), what the Q output look like. 213456789CLRPREQ第五十九頁，共123頁。EXAMPLE 8-8: Related Problem If you interchange the PRE and CLR waveforms in Fig. 8-28 ( a ), what the Q output look like. 213456789CLRPREQ

31、PresetToggleClear第六十頁，共123頁。 Another class of flip-flop is the pulse-triggered master-slave, which has largely been replaced by the edge-triggered devices. Although master-slave flip-flops are essentially becoming obsolete, you may encounter this type of flip-flop in some existing equipment.33.第六十一頁

32、，共123頁。Data are entered into the flip-flop at the leading edge of the clock pulses, but the output does not reflect the input state until the trailing edge. The pulse-triggered master-slave flip-flop does not allow data to change while the clock pulse is active.34.第六十二頁，共123頁。The Pulse-Triggered Mas

33、ter-Slave J-K flip-flopG1G2SRQQG1G2SRQQCJKCLKMasterSlave 35.第六十三頁，共123頁。 Inputs Outputs 0 0 Q0 Q0 No change J K CLK Q Q Comments 0 1 0 1 RESET 1 0 1 0 SET 1 1 Q0 Q0 ToggleTruth table for the master-slaver flip-flop36.第六十四頁，共123頁。JKQQCJKQQC(a) Active-HIGH clock: Data are clocked in on positive-going

34、edge of clock pulse and transferred to output on the following negative- going edge.(b) Active-LOW clock: Data are clocked in on negative -going edge of clock pulse and transferred to output on the following positive- going edge.37.第六十五頁，共123頁。EXAMPLE 8-10: Determine the Q output of the master-slave

35、 J-K flip-flop for the input waveforms shown in Fig. JKQQC38.第六十六頁，共123頁。567892134KJQCLKMa SSla SMa NCSla NCMa RESla REMa NCSla NCMa SSla SMa REMa RESla RESla REMa SMa SSla SSla SSETNCNCToggleReset39.第六十七頁，共123頁。 Application ExampleParallel Data Storage: A common requirement in digital systems is to

36、 store several bits of data from parallel lines simultaneously in a group of flip-flop.40.第六十八頁，共123頁。DDDDQ1Q0Q2Q3D0D1D2D3CLKCLRRRRRD0D1D3D20011CLKCLRQ1Q0Q2Q3000041.0011CLRD stored0011第六十九頁，共123頁。Frequency Division: Another application of a flip-flop is dividing the frequency of a periodic waveform.

37、JKQCHIGHCLK213456789CLKQ42.第七十頁，共123頁。JKQACHIGHCLK213456789CLKQAJKQBCHIGHQB43.第七十一頁，共123頁。JKQAC1CLK21345678CLKQAJKQBC1QBCounting110110100100001103201123Binary sequenceBinary sequence第七十二頁，共123頁。EXAMPLE 8-12: Determine the output waveforms in the relation to the clock for QA,QB,QC in the below circui

38、t. JKQAC1JKCCLKJKCQBQCQAQBQC44.第七十三頁，共123頁。1CLKQAQBQC1111011111110000000000000045.第七十四頁，共123頁。The one-shot is a monostable multivibrator, a device with only one stable state. A one-shot is normally in its stable state and will change to its unstable state only when triggered. 46.第七十五頁，共123頁。Once it

39、is triggered, the one-shot remains in its unstable state for a predetermined length of time and then automatically returns to its stable state. The time that the device stays in its unstable state determines the pulse width of its output. 47.第七十六頁，共123頁。Triggert1t1t1t1t1t2t2t2t2RG1G2Q+VApparent LOW4

40、8.第七十七頁，共123頁。QQTriggerQQCREXTCEXTTriggerCXRX/CX+VBasic one-shot logic symbols. CX and RX stand for external components.49.第七十八頁，共123頁。Nonretriggerable One-Shots : It will not respond to any additional trigger pulses from the time it is triggered into its unstable state until it returns to its stabl

41、e state.TriggerQtw(a)第七十九頁，共123頁。TriggerQtwThese pulse are ignored by the one-shot.(b)50.第八十頁，共123頁。The output pulse width is set by the values of the resistor (RINT = 2k, and REXT is selected) and the capacitor according to the following formula:tw = 0.7RCEXTR is either RINT or REXT51.第八十一頁，共123頁。R

42、etriggerable One-Shots : It can be triggered before it times out.TriggerQtw(a)第八十二頁，共123頁。TriggerQtwRetriggers(b)52.第八十三頁，共123頁。A general formula for calculating the values of these components for a specified pulse width (tw) is tw = 0.32CEXT( 1+0.7/R)53.第八十四頁，共123頁。第八十五頁，共123頁。The 555 timer is a ve

43、rsatile and widely used device because it can be configured in two different modes as either a monostable multivibrator (one-shot) or as an astable multivibrator (oscillator). An astable multivibrator has no stable states and therefore changes back and forth (oscillates) between two unstable states

44、without any external triggering.54.第八十六頁，共123頁。+_+_RSQQ1Comparator AComparator BThresholdControlvoltageTriggerDischargeGNDResetVccoutputDischargetransistorRRR(6)(8)(5)(2)(7)(1)(4)(3)55.第八十七頁，共123頁。Monostable (One-Shot) Operationtw = 1.1R1C1DISCHRESETTHRESHTRIGOUTCONTGNDVccVcc(8)(4)(7)(6)(2)(1)(5)(3)

45、R1C1C256.第八十八頁，共123頁。+_+_RSQQ1ABVccoutputRRR(6)(8)(5)(2)(7)(1)(4)(3)LOWLOWH-TH0 VLOW(a) Prior to triggeringR1ON57.第八十九頁，共123頁。+_+_RSQQ1ABVccRRR(6)(8)(5)(2)(7)(1)(4)(3)LOW0 V(b) When triggeredt0t0t0t0Vc10R1OFF58.Output第九十頁，共123頁。+_+_RSQQ1ABRRR(6)(5)(2)(7)(1)(4)LOW0 V(c) At end of charging intervalt0t

46、0t1t0VCC0R1ONt1t1t1HIGH2359.第九十一頁，共123頁。Astable OperationDISCHRESETTHRESHTRIGOUTCONTGNDVccVcc(8)(4)(7)(6)(2)(1)(5)(3)R1C1C260.R2第九十二頁，共123頁。第九十三頁，共123頁。+_+_RSQQ1ABRRR(6)(5)(2)(7)(1)(4)(3)0 VOperation of the 555 timer in the astable modeR1ONChargingDischargingR261.2/3 Vcc1/3 Vcc(1)(1) 第九十四頁，共123頁。The

47、 frequency of oscillation is given by the following formula.f =1.44(R1+ 2R2)C1 (8-4)The time that the output is HIGH (tH) is how long it takes C1 to charge from 1/3Vcc to 2/3Vcc.tH =0.7(R1+ R2)C1 (8-5)62.第九十五頁，共123頁。The time that the output is LOW (tL) is how long it takes C1 to discharge from 1/3Vc

48、c to 2/3Vcc.tL =0.7R2C1 (8-6)T = tH + tL =0.7( R1+ 2R2)C1Duty cycle = = tHT tH tH tL +63.第九十六頁，共123頁。Duty cycle = 100% R1+R2 R1+2R264. (8-7)第九十七頁，共123頁。Duty cycle = 100% R1 R1+R2DISCHRESETTHRESHTRIGOUTCONTGNDVccVcc(8)(4)(7)(6)(2)(1)(5)(3)R1C1C2D165. (8-8)R2第九十八頁，共123頁。+_+_RSQQ1ABRRR(6)(5)(2)(7)(1)(4

49、)VI Schmitt-Trigger FFVCC59.第九十九頁，共123頁。6847235555(0)6847235555(0)R3R2R1S20 k5V10uFC2C10.01uF0.01uF0.22uFC32.4 k tw =10 s f = 1.2 kHz Find R1, R2 第一百頁，共123頁。6847235555(0)6847235555(0)R3R2R1S20 k5V10uFC2C10.01uF0.01uF0.22uFC32.4 k tw =10 s f = 1.2 kHz Find R1, R2 One Shot : tw = 1.1R1C1 ( 8 3 ) Astab

50、le multivibrator : f = 1.44/( R2+2R3)C2 (8-4)第一百零一頁，共123頁。Chapter 8: Flip-Flop and Related DevicesTrue/False All multivibrators require feedback. Multivibrators must be level triggered.Edge-triggered flip-flops can be identified by the triangle on the clock input.A D flip-flop is constructed by conn

51、ecting an inverter between the Set and Clock terminals. 第一百零二頁，共123頁。5. The J-K flip-flop eliminates the invalid state by toggling when both inputs are high and the clock transitions.6. Preset and Clear inputs are normally synchronous.7. When using master-slave flip-flops, the data is entered into t

52、he flip-flop on the leading edge of the clock, but the output does not change until the trailing edge of the clock.8. Pulse-triggered flip-flops are identified by a bubble on the Q output terminal.第一百零三頁，共123頁。9. A one-shot is a special type of multivibrator which must be triggered to produce each o

53、utput pulse.10. The 555 timer can be used in either the astable or monostable modes.Multiple Choice:11. An active-HIGH input S-R latch has a 1 on the S input and a 0 on the R input, what state is the latch in ?Q = 1, Q = 0 b. Q = 1, Q = 1 c. Q = 0, Q = 1 d. Q = 0, Q = 0 第一百零四頁，共123頁。12. What advanta

54、ge does a J-K flip-flop have over a R-S flip-flop?It has fewer gates.It has only one output.It has no invalid states.a. It does not require a clock input.第一百零五頁，共123頁。13. What is one disadvantage of a R-S flip-flop?It has no Enable input.It has an invalid states.It has no CLOCK input.a. It has only

55、a single output.第一百零六頁，共123頁。14. How is the invalid state problem associated with the R-S flip-flop overcome? The R terminal is eliminated.The R input is fed through an inverter.A single input terminal is used ( D ).a. Both b and c are correct.第一百零七頁，共123頁。15. Which of the following is correct for a

56、 gated D latch?The output toggles if one of the inputs is held high.Q output follows the input D when the ENABLE is high.Only one of the inputs can be high at a time.a. The output complement follows the input when enabled.第一百零八頁，共123頁。16 . Which symbol is used to identify edge-triggered flip-flops?A

57、 bubble on the Clock input. An inverted “ L “ on the output. The letter E on the Enable input.a. A triangle on the Clock input.第一百零九頁，共123頁。17. Edge-triggered flip-flops must havevery fast response times.at least two inputs to handle rising and falling edges.a pulse transition detector.a. active-low

58、 inputs and complemented outputs.第一百一十頁，共123頁。18. Which of the following describes the operation of a positive edge-triggered D flip-flop? If both inputs are high , the output will toggle. The output will follow the input on the leading edge of the clock. When both inputs are low, an invalid state w

59、ill exist.a. The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of clock.第一百一十一頁，共123頁。19. What is the significance of the J-K terminals on the J-K flip-flop? There is no known significance in their designations.The J represents

60、“jump”, which is how the Q output reacts whenever the clock goes high and the J input is also high.The letters represent the initials of Johnson and King, the co-inventors of the J-K flip-flop.a. All of the other letters of the alphabet are already in use.第一百一十二頁，共123頁。20. What is the major advantag