dea吳延海 第8章

1、第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例8.1 數(shù)字密碼鎖電路設(shè)計(jì)數(shù)字密碼鎖電路設(shè)計(jì) 8.2 IIR濾波器電路設(shè)計(jì)濾波器電路設(shè)計(jì) 8.3 簡(jiǎn)單電子琴電路設(shè)計(jì)簡(jiǎn)單電子琴電路設(shè)計(jì) 8.4 交通信號(hào)燈控制器電路設(shè)計(jì)交通信號(hào)燈控制器電路設(shè)計(jì)第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 8.1 數(shù)字密碼鎖電路設(shè)計(jì)數(shù)字密碼鎖電路設(shè)計(jì)8.1.1 系統(tǒng)設(shè)計(jì)要求系統(tǒng)設(shè)計(jì)要求(1) 密碼輸入：每按下一個(gè)數(shù)字鍵，就輸入一個(gè)數(shù)值，并在顯示器上顯示出該數(shù)值，同時(shí)將先前輸入的數(shù)據(jù)依次左移一個(gè)數(shù)字位置。(2) 密碼清除：按下“清除”鍵可清除前面所有輸入的值。第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例(3) 密碼更改：按下“更改”鍵可將目前的數(shù)碼

2、設(shè)定成新的密碼。(4) 密碼上鎖：按下“上鎖”鍵可將密碼鎖定。(5) 密碼解鎖：按下“解鎖”鍵首先檢查輸入的密碼是否正確，密碼正確即開(kāi)鎖。第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例8.1.2 系統(tǒng)設(shè)計(jì)系統(tǒng)設(shè)計(jì)根據(jù)系統(tǒng)設(shè)計(jì)要求，系統(tǒng)設(shè)計(jì)采用自頂向下的設(shè)計(jì)方法。頂層設(shè)計(jì)采用原理圖設(shè)計(jì)方式，系統(tǒng)整體設(shè)計(jì)原理圖如圖8-1所示。它由密碼鎖輸入模塊(SR)、密碼鎖控制模塊(CTRL)和譯碼顯示模塊(YM)三部分組成。第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例圖8-1 系統(tǒng)的整體組裝設(shè)計(jì)原理圖第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例8.1.3 模塊設(shè)計(jì)與實(shí)現(xiàn)模塊設(shè)計(jì)與實(shí)現(xiàn)1密碼鎖輸入模塊(1) 時(shí)序產(chǎn)生電路。時(shí)序產(chǎn)生電路中使用三種不同頻率的工作脈沖波形

3、，即系統(tǒng)時(shí)鐘脈沖、彈跳消除取樣信號(hào)和鍵盤(pán)掃描信號(hào)。(2) 鍵盤(pán)掃描電路。鍵盤(pán)掃描電路的作用是提供鍵盤(pán)掃描信號(hào)，掃描信號(hào)變化的順序依次為11101101101101111110。第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例圖8-2 鍵盤(pán)掃描示意圖第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例當(dāng)鍵盤(pán)掃描信號(hào)為1110時(shí)，按鍵位置分別為011(“1”鍵按下)、101(“2”鍵按下)、110(“3”鍵按下)；當(dāng)鍵盤(pán)掃描信號(hào)為1101時(shí)，按鍵位置分別為011(“4”鍵按下)、101(“5”鍵按下)、110(“6”鍵按下)；當(dāng)鍵盤(pán)掃描信號(hào)為1011時(shí)，按鍵位置分別為011(“7”鍵按下)、101(“8”鍵按下)、110(“9”鍵按下)；當(dāng)鍵盤(pán)

4、掃描信號(hào)為0111時(shí)，按鍵位置分別為011(“*”鍵按下)、101(“0”鍵按下)、110(“#”鍵按下)。第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例(3) 鍵盤(pán)譯碼電路。上述鍵盤(pán)中的按鍵分為數(shù)字按鍵和功能按鍵，每個(gè)功能按鍵可能負(fù)責(zé)不同的功能，例如“清除”鍵、“上鎖”鍵和“解鎖”鍵等。數(shù)字按鍵主要是用來(lái)輸入數(shù)字的。但是鍵盤(pán)所產(chǎn)生的輸出是無(wú)法直接拿來(lái)用作密碼鎖控制電路的輸入的；另外，不同的按鍵具有不同的功能，所以必須有鍵盤(pán)譯碼電路來(lái)規(guī)劃每個(gè)按鍵的輸出形式，以便執(zhí)行相應(yīng)的動(dòng)作。第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 按鍵存儲(chǔ)電路。因?yàn)槊看螔呙钑?huì)產(chǎn)生新的按鍵數(shù)據(jù)，可能會(huì)覆蓋前面的數(shù)據(jù)，所以需要一個(gè)按鍵存儲(chǔ)電路，將整個(gè)鍵盤(pán)掃描完

5、畢的結(jié)果記錄下來(lái)。本設(shè)計(jì)采用串入串出移位寄存器實(shí)現(xiàn)按鍵存儲(chǔ)電路。第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 各按鍵位置與數(shù)碼關(guān)系如表8-1所示。其中“*”為“上鎖”鍵，“#”為“清除/解鎖”鍵。若按下的是數(shù)字鍵，則譯成相對(duì)應(yīng)的BCD碼；若按下的是功能鍵，則譯成四位數(shù)的碼字，并由密碼鎖控制電路給出相應(yīng)的動(dòng)作。第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例根據(jù)上述分析，密碼輸入電路的VHDL源程序(SR.VHD)如下：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_ARIT

6、H.ALL;第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例ENTITY SR ISPORT( CLK_IN : IN STD_LOGIC; -時(shí)鐘信號(hào) KEY_IN : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -按鍵輸入信號(hào) DATA_N : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -數(shù)字鍵數(shù)據(jù) DATA_F : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);-功能鍵數(shù)據(jù) FLAG_N: OUT STD_LOGIC; -數(shù)字鍵數(shù)據(jù)標(biāo)志第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 FLAG_F: OUT STD_LOGIC; -功能鍵數(shù)據(jù)標(biāo)志 CQD: OUT

7、 STD_LOGIC; -鍵盤(pán)輸入采樣時(shí)鐘 KSEL: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -鍵盤(pán)掃描信號(hào) CSR: OUT STD_LOGIC_VECTOR(1 DOWNTO 0);-按鍵行號(hào)00,01,10,11END ENTITY SR;第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例ARCHITECTURE ART OF SR IS SIGNAL C_QD: STD_LOGIC; SIGNAL C_SR: STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL N,F: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL FN,FF:

8、STD_LOGIC;第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 SIGNAL SEL: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL Q: STD_LOGIC_VECTOR(5 DOWNTO 0); SIGNAL C: STD_LOGIC_VECTOR(2 DOWNTO 0);BEGIN -內(nèi)部連接 DATA_N = N; -數(shù)字鍵譯碼值寄存器DATA_F =F; 第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例FLAG_N = FN; -數(shù)字鍵標(biāo)志值數(shù)據(jù)FLAG_F = FF;CQD = C_QD; -鍵盤(pán)輸入采樣時(shí)鐘CSR =C_SR; -按鍵位置KSEL=SEL; -鍵盤(pán)掃描信號(hào)C(0) = KE

9、Y_IN(0); -按鍵輸入寄存器(鍵盤(pán)矩陣的輸出)C(1) = KEY_IN(1);C(2) = KEY_IN(2);第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例COUNTER: BLOCK IS；-鍵盤(pán)掃描模塊(計(jì)數(shù)器) BEGIN PROCESS(CLK_IN) IS BEGIN IF(CLK_INEVENT AND CLK_IN=1) THEN Q=Q+1; END IF;第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 C_QD=Q(3);-鍵盤(pán)輸入采樣時(shí)鐘 C_SR = Q(5 DOWNTO 4);-確定鍵盤(pán)掃描行號(hào) END PROCESS; SEL = 1110 WHEN C_SR=00 ELSE；-掃描“0”行 11

10、01 WHEN C_SR=01 ELSE 1011 WHEN C_SR=10 ELSE 0111 WHEN C_SR=11 ELSE 1111; END BLOCK COUNTER;第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 KEY_DECODER: BLOCK；-鍵盤(pán)譯碼模塊 SIGNAL Z: STD_LOGIC_VECTOR(4 DOWNTO 0);-按鍵位置 BEGIN PROCESS(C_QD)；-鍵盤(pán)采樣時(shí)鐘觸發(fā) BEGIN Z=C_SR & C;-按鍵位置(2位)&按鍵輸入(3位) IF(C_QDEVENT AND C_QD=1) THEN第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 CASE Z

11、 IS WHEN 11101 = N N N N N N N N N N N F F F=1000; END CASE;第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 END IF; END PROCESS; FN = NOT (N(3) AND N(2) AND N(1) AND N(0);-數(shù)字鍵標(biāo)志 FF = F(2) OR F(0); -功能鍵標(biāo)志 END BLOCK KEY_DECODER;END ARCHITECTURE ART;第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例2密碼鎖控制模塊1) 數(shù)字按鍵輸入的相應(yīng)控制(1) 如果按下數(shù)字鍵，第一個(gè)數(shù)字會(huì)從顯示器的最右端開(kāi)始顯示，此后每新按下一個(gè)數(shù)字，顯示器上的數(shù)字必須左

12、移一位，以便將新的數(shù)據(jù)顯示出來(lái)。第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例(2) 假如要更改輸入的數(shù)字，可以按“倒退”鍵來(lái)清除前面輸入的一個(gè)數(shù)字，或者按“清除”鍵清除所有輸入數(shù)字，再重新輸入四位數(shù)。(3) 由于這里設(shè)計(jì)的是一個(gè)四位電子密碼鎖，所以當(dāng)輸入的數(shù)字鍵超過(guò)4個(gè)時(shí)，電路不予理會(huì)，而且不再顯示第四個(gè)以后的數(shù)字。第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例2) 功能按鍵輸入的相應(yīng)控制(1) “清除”鍵：清除所有的輸入數(shù)字，即作歸零動(dòng)作。(2) “上鎖”鍵：按下此鍵時(shí)可將密碼鎖上鎖(上鎖前必須設(shè)置四位數(shù)字密碼)。(3) “解鎖”鍵：按下此鍵會(huì)檢查輸入的密碼是否正確，若密碼正確無(wú)誤則解鎖。第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例下面給出密碼鎖

13、控制模塊的VHDL源程序(CTRL.VHD)：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例ENTITY CTRL ISPORT ( DATA_N : IN STD_LOGIC_VECTOR(3 DOWNTO 0);-數(shù)字鍵數(shù)據(jù) DATA_F : IN STD_LOGIC_VECTOR(3 DOWNTO 0);-功能鍵數(shù)據(jù) FLAG_N : IN STD_LOGIC; -數(shù)字鍵數(shù)據(jù)標(biāo)志 FLAG_F : IN S

14、TD_LOGIC; -功能鍵數(shù)據(jù)標(biāo)志 MIMAIN : BUFFER STD_LOGIC; -密碼輸入標(biāo)志第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 SETIN : BUFFER STD_LOGIC; -密碼設(shè)置標(biāo)志 OLD : BUFFER STD_LOGIC; -舊密碼設(shè)置標(biāo)志 CQD : IN STD_LOGIC; -鍵盤(pán)輸入采樣時(shí)鐘 ENLOCK : OUT STD_LOGIC; -開(kāi)鎖信號(hào) DATA_BCD:OUT STD_LOGIC_VECTOR(15 DOWNTO0);-BCD數(shù)據(jù)END ENTITY CTRL;第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例ARCHITECTURE ART OF CTRL IS S

15、IGNAL ACC, REG: STD_LOGIC_VECTOR (15 DOWNTO 0);-ACC暫存鍵入的信息，REG存儲(chǔ)輸入的密碼BEGIN PROCESS (CQD,FLAG_F) IS BEGIN IF (CQDEVENT AND CQD=0) THEN第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 IF FLAG_F=1 THEN IF(DATA_F = 0100) THEN ACC= 1111111111111111; -功能鍵“*” MIMAIN=0; SETIN=0; OLD ENLOCK MIMAIN = 1; -密碼輸入標(biāo)志 ACC SETIN = 1; -密碼設(shè)置標(biāo)志 ACC=11111

16、11111111111; OLD NULL;第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 END CASE; ELSIF (MIMAIN=1) THEN IF ACC=REG THEN；-密碼核對(duì) ENLOCK=0; MIMAIN=0; ELSE MIMAIN=0; END IF;第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 ELSIF (SETIN=1) THEN IF (OLD=1) THEN IF(ACC=REG) THEN OLD=0; ELSE SETIN=0; OLD=0; END IF; ELSE第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 IF (ACC“1001100110011001”) THEN；-BCD碼小于“9999”

17、為有效碼 REG=ACC; -密碼存儲(chǔ) SETIN=0; END IF; END IF; END IF; END IF;第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 ELSIF FLAG_N=1 THEN ACC= ACC(11 DOWNTO 0)& DATA_N;-實(shí)現(xiàn)數(shù)位左移 END IF; END IF;END PROCESS;DATA_BCD DOUT7 DOUT7 DOUT7 DOUT7 DOUT7 DOUT7 DOUT7 DOUT7 DOUT7 DOUT7 DOUT7=“0000000”; END CASE; END PROCESS;END ARCHITECTURE ART;第 8 章數(shù)字系

18、統(tǒng)設(shè)計(jì)實(shí)例8.1.4 波形仿真波形仿真1. 密碼鎖輸入模塊的仿真波形密碼鎖輸入模塊仿真波形如圖8-3所示。第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例圖8-3 密碼鎖輸入模塊仿真波形第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例2. 密碼鎖控制模塊的仿真波形密碼鎖控制模塊仿真波形如圖8-4所示。圖8-4 密碼鎖控制模塊仿真波形第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例3. 密碼鎖譯碼模塊的仿真波形密碼鎖譯碼模塊仿真波形如圖8-5所示。圖8-5 密碼鎖譯碼模塊仿真波形第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例4. 密碼鎖系統(tǒng)總體仿真圖(1) 設(shè)置新密碼部分。初始出廠時(shí)設(shè)置的密碼為“0000”，用戶重新設(shè)置為“0062”。頂層模塊仿真波形1如圖8-6所示。圖8-6

19、頂層模塊仿真波形1第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例(2) 上鎖部分。按下“#”表示上鎖，設(shè)置完畢后上鎖鍵(ENLOCK)有效。頂層模塊仿真波形2如圖8-7所示。圖8-7 頂層模塊仿真波形2第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 (3) 解鎖但輸入錯(cuò)誤。當(dāng)按下“0692”、“*”時(shí)，上鎖鍵(ENLOCK)仍然有效，表示輸入密碼有錯(cuò)誤，沒(méi)有解開(kāi)密碼。頂層模塊仿真波形3如圖8-8所示。第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例圖8-8 頂層模塊仿真波形3第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例(4) 解鎖且輸入正確。當(dāng)按下“0062”、“*”時(shí)，上鎖鍵(ENLOCK)無(wú)效，表示輸入的密碼正確，解開(kāi)密碼。頂層模塊仿真波形4如圖8-9所示。第 8 章

20、數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例圖8-9 頂層模塊仿真波形4第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 8.2 IIR濾波器電路設(shè)計(jì)濾波器電路設(shè)計(jì)8.2.1 概述概述IIR濾波器傳輸函數(shù)的一般形式為kN1kkM0ka(k)z1b(k)zH(z) (8-1) 第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例其差分方程的一般形式為k)a(k)y(nk)b(k)x(ny(n)N1kM0k(8-2) 常用的IIR數(shù)字濾波器實(shí)現(xiàn)方法有如下幾種： 采用在通用計(jì)算機(jī)系統(tǒng)中加上專用的加速處理機(jī)實(shí)現(xiàn)； 利用DSP芯片實(shí)現(xiàn)； 采用普通硬件組合實(shí)現(xiàn)； 采用EDA技術(shù)和FPGA/CPLD器件實(shí)現(xiàn)。第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例在這幾種方法中，利用EDA加FPGA/CPLD的

21、方法具有速度快、成本低、效率高等優(yōu)點(diǎn)。通常利用EDA技術(shù)和FPGA/CPLD實(shí)現(xiàn)IIR數(shù)字濾波器有如下幾種方法： 利用VHDL實(shí)現(xiàn)； 利用LPM設(shè)計(jì)方法； 利用DSP Bulider實(shí)現(xiàn)； 利用IP核實(shí)現(xiàn)。第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例8.2.2 IIR濾波器設(shè)計(jì)方案濾波器設(shè)計(jì)方案式(8-2)的二階形式如下：2k21k12k21k1k0kzaza1zbzbb(z)H(8-3) 第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例這樣就可以將任意階的IIR濾波器通過(guò)若干二階網(wǎng)絡(luò)(也稱為濾波器的二階基本節(jié))級(jí)聯(lián)起來(lái)，如圖8-10所示。圖8-10 級(jí)聯(lián)二階IIR網(wǎng)絡(luò)第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例對(duì)于每一個(gè)二階基本節(jié)，可以通過(guò)轉(zhuǎn)置直接

22、型結(jié)構(gòu)加以實(shí)現(xiàn)，如圖8-11所示。圖8-11 二階基本節(jié)直接型結(jié)構(gòu)第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例采用這種級(jí)聯(lián)結(jié)構(gòu)實(shí)現(xiàn)IIR濾波器的優(yōu)點(diǎn)是每一個(gè)基本節(jié)只是關(guān)系到濾波器的某一對(duì)極點(diǎn)和一對(duì)零點(diǎn)，調(diào)整系數(shù)ai，只單獨(dú)地調(diào)整了濾波器第i對(duì)零點(diǎn)，而不影響其他任何零、極點(diǎn)。同樣，調(diào)整bi系數(shù)，也只單獨(dú)調(diào)整了第i對(duì)極點(diǎn)。因此，這種結(jié)構(gòu)便于準(zhǔn)確地實(shí)現(xiàn)濾波器的零、極點(diǎn)，也便于調(diào)整濾波器的頻率響應(yīng)性能。第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例假設(shè)要設(shè)計(jì)一個(gè)4階IIR濾波器，則采用MATLAB實(shí)現(xiàn)IIR濾波器的源代碼如下：FilterOrder=4;FeedForward,FeedBack = ellip(FilterOrder,3,

23、50,300/500);figure(1);freqz(FeedForward,FeedBack);title(Frequency Response (full precision coefficients);z,p,k = tf2zp(FeedForward,FeedBack);SecOrd = zp2sos(z,p,k); 第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例可得SecOrd= 0.11160.2086 0.1116 1.0000 -0.5362 0.4138 1.0000 1.4239 1.0000 1.0000 0.5099 0.8690則可得該濾波器的二階差分方程的系數(shù)如表8-2所示，幅頻響應(yīng)

24、如圖8-12所示。第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例圖8-12 IIR幅頻響應(yīng)第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例8.2.3 IIR濾波器實(shí)現(xiàn)濾波器實(shí)現(xiàn)1. 設(shè)計(jì)方案式(8-3)所對(duì)應(yīng)的二階節(jié)系統(tǒng)函數(shù)的差分方程為2)y(na1)y(na2)x(nb1)x(nbx(n)by(n)21210(8-4)第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例2. 主要功能模塊設(shè)計(jì)1) 輸入控制單元將輸入數(shù)據(jù)送入輸入寄存器中，其VHDL描述如下： input_reg_process : PROCESS (clk) BEGIN IF clkevent AND clk = 1 THEN IF reset = 1 THEN in

25、put_register = 0.0000000000000000E+000;第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 ELSIF clk_en = 1 THEN input_register =x; END IF; END IF; END PROCESS input_reg_process; scale1 = input_register * scaleconst1;第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例2) 移位單元將輸入寄存器上一時(shí)刻的數(shù)據(jù)送入delay_section1(0)，同時(shí)又將delay_section1(0)上一時(shí)刻的數(shù)據(jù)送入delay_section1(1),其VHDL描述如下：第 8 章數(shù)字系統(tǒng)設(shè)

26、計(jì)實(shí)例delay_process_section1 : PROCESS (clk) BEGIN IF clkevent AND clk = 1 THEN IF reset = 1 THEN delay_section1(0 TO 1) 0.0000000000000000E+000);第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 ELSIF clk_en = 1 THEN delay_section1(0) = a1sum1; delay_section1(1) = delay_section1(0); END IF; END IF; END PROCESS delay_process_section1;第 8

27、 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例3) 乘加單元先將系數(shù)與其相關(guān)數(shù)據(jù)相乘，再進(jìn)行相加，其VHDL描述如下：PROCESS(scale1,delay_section1,a1sum1)BEGIN inputconv1 = scale1; a2mul1 = delay_section1(0) * coeff_a2_section1; a3mul1 = delay_section1(1) * coeff_a3_section1; b1mul1 = a1sum1;第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 b2mul1 = delay_section1(0) * coeff_b2_section1; b3mul1 = delay_s

28、ection1(1); a2sum1 = inputconv1 - a2mul1; a1sum1 = a2sum1 - a3mul1; b2sum1 = b1mul1 + b2mul1; b1sum1 = b2sum1 + b3mul1; scale2 = b1sum1 * scaleconst2;第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例4) 輸出控制單元將輸出數(shù)據(jù)送入輸出寄存器輸出，其VHDL描述如下： output_register_process : PROCESS (clk) BEGIN IF clkevent AND clk = 1 THEN IF reset = 1 THEN output_re

29、gister = 0.0000000000000000E+000 第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 ELSIF clk_enable = 1 THEN output_register = output_typeconvert; END IF; END IF; END PROCESS output_register_process;result 0); dataa_1: IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS = 0); dataa_2: IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS = 0);第 8 章數(shù)字

30、系統(tǒng)設(shè)計(jì)實(shí)例 datab_0: IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS = 0); datab_1: IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS = 0); datab_2: IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS = 0); ena0: IN STD_LOGIC:= 1; result: OUT STD_LOGIC_VECTOR (37 DOWNTO 0);END fmadd;第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例ARCHITECTURE SYN OF fma

31、dd ISSIGNAL sub_wire0: STD_LOGIC_VECTOR (37 DOWNTO 0);SIGNAL sub_wire1: STD_LOGIC_VECTOR (17 DOWNTO 0);SIGNAL sub_wire2: STD_LOGIC_VECTOR (53 DOWNTO 0);SIGNAL sub_wire3: STD_LOGIC_VECTOR (17 DOWNTO 0);SIGNAL sub_wire4: STD_LOGIC_VECTOR (17 DOWNTO 0);第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例SIGNAL sub_wire5: STD_LOGIC_VECTOR (1

32、7 DOWNTO 0);SIGNAL sub_wire6: STD_LOGIC_VECTOR (53 DOWNTO 0);SIGNAL sub_wire7: STD_LOGIC_VECTOR (17 DOWNTO 0);SIGNAL sub_wire8: STD_LOGIC_VECTOR (17 DOWNTO 0);COMPONENT altmult_addGENERIC (第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例addnsub_multiplier_aclr1: STRING;addnsub_multiplier_pipeline_aclr1: STRING;addnsub_multiplier_pipe

33、line_register1: STRING;addnsub_multiplier_register1: STRING;dedicated_multiplier_circuitry: STRING;input_aclr_a0: STRING;input_aclr_a1: STRING;第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例input_aclr_a2: STRING;input_aclr_b0: STRING;input_aclr_b1: STRING;input_aclr_b2: STRING;input_register_a0: STRING;input_register_a1: STRING;inpu

34、t_register_a2: STRING;input_register_b0: STRING;input_register_b1: STRING;第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例input_register_b2: STRING;input_source_a0: STRING;input_source_a1: STRING;input_source_a2: STRING;input_source_b0: STRING;input_source_b1: STRING;input_source_b2: STRING;intended_device_family: STRING;lpm_type: ST

35、RING;multiplier1_direction: STRING;第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例multiplier_aclr0: STRING;multiplier_aclr1: STRING;multiplier_aclr2: STRING;multiplier_register0: STRING;multiplier_register1: STRING;multiplier_register2: STRING;number_of_multipliers: NATURAL;output_aclr: STRING;output_register: STRING;port_addnsub1:

36、STRING;第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例port_signa: STRING;port_signb: STRING;representation_a: STRING;representation_b: STRING;signed_aclr_a: STRING;signed_aclr_b: STRING;signed_pipeline_aclr_a: STRING;signed_pipeline_aclr_b: STRING;signed_pipeline_register_a: STRING;第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例signed_pipeline_register_b: STRING;sig

37、ned_register_a: STRING;signed_register_b: STRING;width_a: NATURAL;width_b: NATURAL;width_result: NATURAL);PORT(dataa: IN STD_LOGIC_VECTOR(53 DOWNTO 0); datab:IN STD_LOGIC_VECTOR(53 DOWNTO 0);第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 clock0: IN STD_LOGIC ; aclr3: IN STD_LOGIC ; ena0: IN STD_LOGIC ; result: OUT STD_LOGIC_VECTOR

38、(37 DOWNTO 0);END COMPONENT;BEGIN第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例sub_wire8 = datab_2(17 DOWNTO 0);sub_wire7 = datab_0(17 DOWNTO 0);sub_wire4 = dataa_2(17 DOWNTO 0);sub_wire3 = dataa_1(17 DOWNTO 0);result = sub_wire0(37 DOWNTO 0);sub_wire1 = dataa_0(17 DOWNTO 0);sub_wire2 = sub_wire4(17 DOWNTO 0) & sub_wire3(17 DOW

39、NTO 0) & sub_wire1(17 DOWNTO 0);第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例sub_wire5 = datab_1(17 DOWNTO 0);sub_wire6 ACLR3,addnsub_multiplier_pipeline_aclr1 = ACLR3,addnsub_multiplier_pipeline_register1 = CLOCK0,第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例addnsub_multiplier_register1 = CLOCK0,dedicated_multiplier_circuitry = AUTO,input_aclr_a0 = ACLR3,in

40、put_aclr_a1 = ACLR3,input_aclr_a2 = ACLR3,input_aclr_b0 = ACLR3,input_aclr_b1 = ACLR3,input_aclr_b2 = ACLR3,第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例input_register_a0 = CLOCK0,input_register_a1 = CLOCK0,input_register_a2 = CLOCK0,input_register_b0 = CLOCK0,input_register_b1 = CLOCK0,input_register_b2 = CLOCK0,input_source_a0 =

41、 DATAA,input_source_a1 = DATAA,input_source_a2 = DATAA,第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例input_source_b0 = DATAB,input_source_b1 = DATAB,input_source_b2 = DATAB,intended_device_family = FLEX10K,lpm_type = altmult_add,multiplier1_direction = ADD,multiplier_aclr0 = ACLR3,multiplier_aclr1 = ACLR3,multiplier_aclr2 = ACLR3,第

42、 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例multiplier_register0 = CLOCK0,multiplier_register1 = CLOCK0,multiplier_register2 = CLOCK0,number_of_multipliers = 3,output_aclr = ACLR3,output_register = CLOCK0,port_addnsub1 = PORT_UNUSED,port_signa = PORT_UNUSED,port_signb = PORT_UNUSED,第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例representation_a = SIGNED,representa

43、tion_b = SIGNED,signed_aclr_a = ACLR3,signed_aclr_b = ACLR3,signed_pipeline_aclr_a = ACLR3,signed_pipeline_aclr_b = ACLR3,signed_pipeline_register_a = CLOCK0,signed_pipeline_register_b = CLOCK0,signed_register_a = CLOCK0,signed_register_b = CLOCK0,第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例width_a = 18,width_b = 18,width_result

44、= 38)PORT MAP (dataa = sub_wire2,datab = sub_wire6,clock0 = clock0,aclr3 = aclr3,ena0 = ena0,result = sub_wire0); END SYN;第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例(2) LPM加法器的VHDL源程序如下：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;LIBRARY lpm;USE lpm.ALL;第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例ENTITY adder ISPORT(dataa: IN STD_LOGIC_VECTOR(17 DOWNTO 0);datab:

45、 IN STD_LOGIC_VECTOR (17 DOWNTO 0);cout: OUT STD_LOGIC ;overflow: OUT STD_LOGIC ;result: OUT STD_LOGIC_VECTOR (17 DOWNTO 0);END adder;第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例ARCHITECTURE SYN OF adder ISSIGNAL sub_wire0: STD_LOGIC ;SIGNAL sub_wire1: STD_LOGIC ;SIGNAL sub_wire2: STD_LOGIC_VECTOR (17 DOWNTO 0);COMPONENT lpm_add_

46、subGENERIC (lpm_direction: STRING;lpm_hint: STRING;lpm_type: STRING;lpm_width: NATURAL);第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例PORT (dataa: IN STD_LOGIC_VECTOR (17 DOWNTO 0); datab: IN STD_LOGIC_VECTOR (17 DOWNTO 0); overflow: OUT STD_LOGIC ; cout : OUT STD_LOGIC ; result: OUT STD_LOGIC_VECTOR (17 DOWNTO 0);END COMPONENT;第 8

47、 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例BEGINoverflow = sub_wire0;cout = sub_wire1;result ADD,第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例lpm_hint = ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO,lpm_type = LPM_ADD_SUB,lpm_width = 18 )PORT MAP (dataa = dataa,datab = datab,overflow = sub_wire0,cout = sub_wire1,result = sub_wire2);END SYN;第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例(3) 二階節(jié)IIR濾波器模塊iir_

48、1的VHDL構(gòu)造體源程序如下：ARCHITECTURE translated OF iir_1 IS COMPONENT adder PORT (dataa : IN STD_LOGIC_VECTOR(17 DOWNTO 0); datab : IN STD_LOGIC_VECTOR(17 DOWNTO 0); result : OUT STD_LOGIC_VECTOR(17 DOWNTO 0); cout : OUT STD_LOGIC; overflow : OUT STD_LOGIC);第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 END COMPONENT; SIGNAL coef_b1: STD_LO

49、GIC_VECTOR(DLY_WIDTH-1 DOWNTO 0); SIGNAL coef_b2: STD_LOGIC_VECTOR(DLY_WIDTH-1 DOWNTO 0); SIGNAL coef_a0: STD_LOGIC_VECTOR(DLY_WIDTH-1 DOWNTO 0); SIGNAL coef_a1: STD_LOGIC_VECTOR(DLY_WIDTH-1 DOWNTO 0); SIGNAL coef_a2: STD_LOGIC_VECTOR(DLY_WIDTH-1 DOWNTO 0); 第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 SIGNAL coef_a2: STD_LOGIC_VE

50、CTOR(DLY_WIDTH-1 DOWNTO 0); SIGNAL result_xhdl1: STD_LOGIC_VECTOR(OUTPUT_WIDTH-1 DOWNTO 0); SIGNAL feedback_fp_xhdl2:STD_LOGIC_VECTOR(OUTPUT_WIDTH-2 DOWNTO 0); SIGNAL wn_xhdl3: STD_LOGIC_VECTOR(DLY_WIDTH01-DOWNTO 0); SIGNAL feedback_xhdl4: STD_LOGIC_VECTOR(DLY_WIDTH01-1DOWNTO 0); 第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例COMPON

51、ENT fmadd IS PORT (clock0: IN STD_LOGIC; dataa_0: IN STD_LOGIC_VECTOR(17 DOWNTO 0); aclr3: IN STD_LOGIC; datab_0: IN STD_LOGIC_VECTOR(17 DOWNTO 0); dataa_2: IN STD_LOGIC_VECTOR(17 DOWNTO 0); datab_1: IN STD_LOGIC_VECTOR(17 DOWNTO 0); ena0 : IN STD_LOGIC; datab_2: IN STD_LOGIC_VECTOR(17 DOWNTO 0); re

52、sult : OUT STD_LOGIC_VECTOR(37 DOWNTO 0); 第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例END COMPONENT; COMPONENT tmadd IS PORT (clock0 : IN STD_LOGIC; dataa_0 : IN STD_LOGIC_VECTOR(17 DOWNTO 0); aclr3: IN STD_LOGIC; datab_0: IN STD_LOGIC_VECTOR(17 DOWNTO 0); datab_1: IN STD_LOGIC_VECTOR(17 DOWNTO 0); ena0: IN STD_LOGIC; result: OUT

53、 STD_LOGIC_VECTOR(36 DOWNTO 0); 第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例END COMPONENT;BEGIN result = result_xhdl1; feedback_fp = feedback_fp_xhdl2; wn = wn_xhdl3; feedback = feedback_xhdl4; coef_b1 = conv_STD_LOGIC_VECTOr( -b1, 18) ; coef_b2 = conv_STD_LOGIC_VECTOR( -b2, 18) ;第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 coef_a0 = conv_STD_LOGIC_VECTOR(a0,

54、18) ; coef_a1 = conv_STD_LOGIC_VECTOR(a1, 18) ; coef_a2 = conv_STD_LOGIC_VECTOR(a2, 18) ; feedback_xhdl4 clk, aclr3 = reset,第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 ena0 = clken, dataa_0 = wn_xhdl3, dataa_2 = wn_xhdl3, datab_0 = coef_a1, datab_1 = coef_a2, datab_2 = coef_a0, result = result_xhdl1); 第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 two_mult_add_

55、inst : tmadd PORT MAP ( clock0 = clk, dataa_0 = wn_xhdl3, aclr3 = reset, datab_0 = coef_b1, datab_1 = coef_b2, ena0 = clken, result = feedback_fp_xhdl2); 第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 adder_inst : adder PORT MAP (dataa = x, datab = feedback_xhdl4, result = wn_xhdl3, cout = open, overflow = open); END translated;第 8

56、 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例總體設(shè)計(jì)的構(gòu)造體VHDL源程序如下：ARCHITECTURE translated OF iir_top IS SIGNAL out_1 : BIT_VECTOR(OUTPUT_WIDTH-1 DOWNTO 0); SIGNAL pzeros : BIT_VECTOR(F_BITS-1 DOWNTO 0); SIGNAL xn : BIT_VECTOR(DLY_WIDTH-1 DOWNTO 0); 第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 SIGNAL result_w : BIT_VECTOR(OUTPUT_WIDTH-1 DOWNTO 0); SIGNAL xn_reg : BIT_

57、VECTOR(DLY_WIDTH-1 DOWNTO 0); SIGNAL in_2 : BIT_VECTOR(DLY_WIDTH-1 DOWNTO 0); SIGNAL result_xhdl1 : BIT_VECTOR(OUTPUT_WIDTH-1 DOWNTO 0); 第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例COMPONENT iir_1 is PORT (reset : IN BIT; clk : IN BIT; clken : IN BIT; x : IN BIT_VECTOR(INPUT_WIDTH-1 DOWNTO 0); result : OUT BIT_VECTOR(OUTPUT_WIDTH

58、-1 DOWNTO 0); feedback_fp : OUT BIT_VECTOR(OUTPUT_WIDTH-2 DOWNTO 0); feedback : OUT BIT_VECTOR(DLY_WIDTH-1 DOWNTO 0); wn: OUT BIT_VECTOR(DLY_WIDTH-1 DOWNTO 0); 第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例END COMPONENT;BEGIN result = result_xhdl1; pzeros = “0000” ; xn = x(INPUT_WIDTH-1) & x(INPUT_WIDTH-1 DOWNTO 0) & pzeros

59、 (F_BITS-1 DOWNTO 0) ;第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 PROCESS BEGIN WAIT UNTIL (clkEVENT AND clk = 1); IF (reset = 1) THEN xn_reg 0); result_xhdl1 0); in_2 0); ELSE IF (clken = 1) THEN第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 xn_reg = xn; result_xhdl1 = result_w; in_biquad2 a10, a1 = a11,第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 a2 = a12, b1 = b11, b2 = b12) PORT MAP (clk

60、 = clk, clken = clken, reset = reset, x = xn_reg, result = out_1); 第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例 base_iir_2 : iir_1 GENERIC MAP (a0 = a20, a1 = a21, a2 = a22, b1 = b21, b2 = b22) PORT MAP (clk = clk, clken = clken, reset = reset, x = in_2, result = result_w); END translated;第 8 章數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例2. 基于DSP Builder的IIR濾波器設(shè)計(jì)(1) 在MATLAB/Simulink中進(jìn)行設(shè)計(jì)輸入，即