基于FPGA的函數(shù)信號(hào)發(fā)生器設(shè)計(jì)-英文翻譯

1、論 文 翻 譯7A Precision frequency synthesis method by FPGAContentsA method of frequency measurement based on a closed loop composed mainly of a Frequency Comparator (FC) and a Direct Digital Synthesizer (DDS) is presented in this paper. The DDS serves as reference sinewave signal generator acting at one

2、 of the FC's inputs. The FC accepts the hard-limited waveform of the DDS as well as the unknown frequency. From the comparison of the two signals a logic output that controls an up/down counter is produced. The counter's output acting as the Frequency Setting Word (FSW) instructs the DDS to

3、produce a new sinewave closer in frequency to the unknown one. When the loop settles, the FSW gives the digital estimate of the unknown frequency. Advantage is taken from the inherent high resolution of the DDS and noise immunity of the loop, to design an equally precise and immune frequency meter.

4、All the additional associated stages up to the instrument's display are presented.1 IntroductionThe most commonly used frequency measurement technique adopts counters that count the pulses of the unknown frequency during a predefined time window (aperture). Apart from this, techniques where the

5、pulses of a reference frequency are counted during one or more periods of the unknown one are also common. In the latter case, the period instead of the frequency is estimated .Some papers in the literature deal with the problem of low frequency measurement and are focusing in the frequency range of

6、 cardiac (heart) signals (a few hertz) or in the mains frequency (50-60 Hz). These techniques are actually measuring the period of the signals and use some way to calculate its reciprocal, the frequency. In the frequency is calculated by the method of look-up tables. Others are microprocessor or mic

7、rocontroller based.The above methods can be characterized as open-loop methods i.e. digital counters are used to count during a predefined tinle interval and calculate the result afterwards. Its closed-loop form characterizes the proposed method in this paper. By the term "closed-loop" we

8、denote some sort of feedback. A waveform with a known (controlled) frequency is produced within the circuit and is fed back to the frequency comparison stage which consecutively forces it to approximate the unknown (input) frequency. The device that produces the above mentioned waveform of controlle

9、d frequency is a Direct Digital Synthesizer.2 Direct Digital SynthesisA typical Direct Digital Synthesizer consists of a RAM containing samples of a sinewave (sine look-up table, LUT). These samples are swept in a controlled manner by the aid of a Frequency Setting Word (FSW), which determines the p

10、hase step. A typical FSW is 32-bit wide, but 48-bit synthesizers leading in higher frequency resolution are also available. A phase accumulator produces the successive addresses of the sine look-up table and generates a digitized sine wave output. The digital part of the DDS, the phase accumulator a

11、nd the LUT, is called Numerically Controlled Oscillator (NCO). The final stage, which in contrast to the previous one is mostly analog, consists of a D/A converter followed by a filter. The filter smoothes the digitized sinewave, producing a continuous output signal. In the applications where a squa

12、re wave output is needed, this is obtained by a hard limiter after the filter. It is not equivalent to use e.g. the MSB of the accumulator's output instead of the filtered and hard limited waveform because significant jitter will be encountered.The frequency of the output signal for an n-bit sys

13、tem is calculated in the following way; If the phase step is equal to one, the accumulator will count by ones, taking clock cycles to address the entire LUT and to generate one cycle of the output sinewave. This is the lowest frequency that the system can generate and is also its frequency resolutio

14、n. Setting the FSW equal to two, results in the accumulator counting by twos, taking clock cycles to complete one cycle of the output sinewave. It can easily be shown that for any integer m, where m<, the number of clock cycles taken to generate one cycle of the output sine wave is /m, and the ou

15、tput frequency (fDDS) and the frequency resolution (fres) are given by the following formulas：fDDS=fres= fclk/For n = 32 and having a clock frequency of fclk = 33 MHz, the frequency resolution is 7.68 mHz. If n is increased to 48, with the same clock frequency, a resolution of 120 nHz is possible.3

16、The proposed frequency measurement techniqueThe idea that led to our present design came from the extremely high frequency resolution of the DDS devices and is enforced by the noise immunity of its closed loop form. A (known) frequency source, the DDS, is employed in a closed loop and is forced prog

17、ressively to produce an output with a frequency equal to the unknown input . A rule of thumb in the DDS systems is that the maximum acceptable synthesized frequency is about 25% of the clock frequency (well below the Nyquist limit). According to this, our prototype that uses a 33 MHz clock would eff

18、ectively count up to 8 MHz. Looking at the GaAs products, we can see that recently available DDS devises can operate at clock frequencies up to the extent of 400 MHz. Therefore, by the present method, frequency counters working up to 100 MHz can be designed. The resolution will depend on the number

19、of FSW bits and the clock frequency. The clock frequency fclk of the DDS is very critical because as it decreases, the resolution of the proposed method (defined as fclk/) becomes finer i.e. it improves. The impact of the clock frequency decrease is the subsequent decrease of its maximum output freq

20、uency that limits the counter's maximum count. The major blocks have been shown . Among them are the Frequency Comparator and the DDS. To overcome some disadvantages of the specific frequency comparator a correction stage has been incorporated. This stage is also used for the measurement extract

21、ion in order to display the correct reading.3.1 Operation of the circuitThe circuit operates in such a way that at the beginning of a new measurement the DDS output frequency would be controlled in a successive approximation way. The initial DDS frequency would be half of it's maximum. In additi

22、on, the frequency step of the approximation would equal the 1/4 of the DDS maximum frequency. On every approximation the frequency step is divided by two and added or subtracted to the FSW of the DDS, depending on the output of the Frequency Comparator. The approximation procedure stops when the ste

23、p size decreases to one. After that, an up/down counter substitutes the approximation mechanism. The digital FSW, after the appropriate correction and decoding, is presented in an output device i.e. an LCD display or any other suitable means. Alternatively, it can be digitally recorded or it can be

24、read by a computer. As conclusion of this initial approach we could say that the proposed method is based on a Digital Controlled Synthesizer which is forced to produce a frequency almost equal to the unknown one.3.2 Frequency comparisonThe frequency comparator seems to be the most critical stage of

25、 the design. The implementation is based on a modified phase/frequency comparator proposed by Philips in the 74HC4046 PLL device. It consists primarily of two binary counters, counting up to two and an RS flip-flop.The function of the frequency comparator is based on the principle that the lower fre

26、quency, i.e. larger period, includes (embraces) at least one or more full periods of the higher frequency (smaller period). This means that two or more rising edges of the higher frequency waveform are included within the lower frequency period. Considering the above, the circuit operates as follows

27、: When the first counter (#1) encounters two rising edges of the unknown frequency in one period of the DDS, it sets the output of the RS flip-flop. The logic "1" of the RS flip-flop acting at the U/D control input of the Up/Down counter forces the DDS to rise its output frequency. On the

28、contrary, when the second counter (#2) counts two rising edges of the DDS output within a period of the unknown frequency it resets the RS flip-flop's output. This action decreases the frequency of the DDS.At a first glance one could think that the synthesized frequency could reach the measured

29、one (fin) and then the operation of the counter stops. Unfortunately this is not the case. A dynamic mechanism takes place instead. The circuit needs some time to realize the correct frequency relation. We will refer to this time as "hysteresis". Hysteresis depends on the initial timing re

30、lation of the DDS output and on the unknown frequency. Initially, during the hysteresis period, the indication regarding the larger frequency is ambiguous i.e. it can be erroneous. The ambiguity settles when two rising edges of the higher frequency waveform occur during one period of the lower one.

31、If we consider the case of the DDS frequency to be equal to the unknown one, we will find that the comparator's output will toggle, indicating alternatively that the DDS frequency is higher or lower than the unknown. This is actually an acceptable and expected condition,because (as in a voltage

32、comparator) an equality indication could not exist. In our case this is not a problem because the circuit is embedded in a closed loop. The loop will act in a manner that after some short time, the hysteresis, the situation will be reversed and so on. The duration of hysteresis is variable. This sit

33、uation is controlled, as will be explained later. Although an analog implementation of the frequency comparator would look more robust to noise we insisted to the digital implementation for three reasons: ease of implementation in VLSI or Programmable Logic Devices (PLDs) with no need of analog comp

34、onents, wide frequency range of operation and shorter response time.3.3 Interaction between frequency comparator and digital synthesizerAfter the successive approximation of the unknown frequency the Frequency Comparator "realizes" that the synthesized frequency is higher (lower) than the

35、unknown one and produces a logic 0 (1) at the output which commands the up/down counter to count in the down (up) direction. As previously mentioned, the output of this counter is considered to be the FSW to the DDS stage. In the case when the DDS frequency was initially lower, the synthesized frequ

36、ency will increase progressively to reach the unknown one. This will not be "realized" by the frequency comparator and the synthesized frequency will keep on increasing for some clock cycles, until the comparator detects the correct relation of it's two input frequencies, the unknown o

37、ne and the DDS output. The same phenomenon will be observed for the opposite (decreasing) case also. This is due to hysteresis that was mentioned earlier.When DDS output (fDDS) has approached fin, due to hysteresis, no specific frequency is synthesized. Instead, it swings between f1 and f2, where f1

38、 and f2 are the two extreme values of the frequency swing lying symmetrically around fin. The DDS output can be considered as a frequency modulated carrier by a triangular waveform. The triangular waveform is the analog representation of the FSW applied to the DDS. lower trace shows a typical output

39、 of the Frequency Comparator. In the same figure, upper trace, is shown in analog form the FSW variation as it is trying to approach the correct value. This waveform has been captured using an auxiliary hardware circuit: A digital-to-analog converter (DAC) was connected to the output of the U/D coun

40、ter (MSBs) in order to study the operation. This DAC is not shown in the block diagram of the circuit. Stated differently, the lower trace is the U/D command (input) to the counter while the upper trace is a hypothetical "frequency modulating" waveform. It is obvious that the term "hy

41、pothetical" is used because there is not such a waveform available somewhere in the circuit (except for the auxiliary DAC). Instead, its numerical equivalent exists. The magnitude of the slope of the elements of the triangular waveform is constant for constant input frequency and depends on the

42、 clock of the U/D counter (horizontal axis) and the voltage reference of the DAC (vertical axis). This slope is k fin.3.4 Description of the prototype hardwareFor evaluation purposes two prototypes have been built and tested in the laboratory. The first approach was a low frequency instrument (opera

43、ting up to 15 KHz) . The purpose of this implementation was to study the principles of operation of the proposed method. Next, a higher frequency prototype was built which will be described in more detail here. In order to implement the digital part of the prototype, (Frequency Comparator, Successiv

44、e Counter, Correction Stage) two PLD devices from Altera (EPF 8064LC68-12) were used. These devices are interconnected with the DDS, which is the Q2240I-3S1 from Qualcomm. The DDS has a 32-bit input and a 12-bit output for the sine lookup table (LUT). The 12-bit output of the LUT is fed into the D/A

45、 converter, the AD9713B from Analog Devices. Its analog output is connected to an I/V amplifier (current-to-voltage converter). The generated sinewave has upper harmonics, due to the DAC operation. These harmonics are removed from the filters that follow the DAC. The correction stage is implemented

46、partially on the PLDs and partially on the microcontroller. Based on the up-down command of the frequency comparator we store the two extreme values, FSW1 and FSW2, which are then transferred into the micro-controller (Atmel AT89C52), transformed into numerical representation and fed to the LCD Disp

47、lay. The micro-controller also controls the whole operation of the prototype. The behaviour of the instrument was according to the expected and was alike to a conventional bench frequency counter. The speed of measurement was checked using lower trace, obtained by the aid of a digital oscilloscope. Each state, high or low, of this waveform corresponds to the tim