基于vhdl語(yǔ)言的簡(jiǎn)易電子鐘課程設(shè)計(jì)說(shuō)明書

1、設(shè) 計(jì) 報(bào) 告現(xiàn)代電子技術(shù)綜合實(shí)驗(yàn)課程名稱 數(shù)字式秒表設(shè)計(jì)與實(shí)現(xiàn)設(shè)計(jì)題目 指導(dǎo)老師 學(xué) 生 學(xué) 號(hào) 目錄1 引言.1.1課程設(shè)計(jì)的內(nèi)容及要求.2 VHDL簡(jiǎn)介.2.1硬件描述語(yǔ)言VHDL.2.1.1 VHDL語(yǔ)言的特點(diǎn).2.1.2 VHDL語(yǔ)言的設(shè)計(jì)流程.3 秒表設(shè)計(jì)過(guò)程.3.1原理框圖.3.2設(shè)計(jì)思路模塊化.3.3模塊的功能簡(jiǎn)述.分頻器.計(jì)數(shù)器.數(shù)據(jù)鎖存器.顯示譯碼模塊.控制模塊.按鍵消抖模塊.頂層文件.4 模塊電路仿真. 4.1 分頻器 4.2計(jì)數(shù)器 4.2.1 模6計(jì)數(shù)器 4.2.2 模10計(jì)數(shù)器5 實(shí)驗(yàn)總結(jié).5.1實(shí)驗(yàn)結(jié)論.5.2心得總結(jié).6 參考文獻(xiàn).7 附錄(各模塊源程序).1.

2、引言：在當(dāng)今信息化社會(huì)中，集成電路和計(jì)算機(jī)應(yīng)用得到高速發(fā)展，。它在人們?nèi)粘Ｉ钜驯夭豢缮?，大多?shù)電子產(chǎn)品多是由計(jì)算機(jī)電路組成。本文目的就是基于計(jì)算機(jī)電路利用VHDL語(yǔ)言設(shè)計(jì)出數(shù)字秒表。秒表在很多領(lǐng)域充當(dāng)了重要的角色，在不同的場(chǎng)合和條件下對(duì)于秒表的精度和功能是不同的，有些科學(xué)實(shí)驗(yàn)的要求甚至能達(dá)到納秒級(jí)別。1.1課題內(nèi)容要求：本課題目標(biāo)是掌握VHDL開(kāi)發(fā)FPGA的一般流程，重點(diǎn)是電子秒表的設(shè)計(jì)。該設(shè)計(jì)以VHDL作為硬件開(kāi)發(fā)語(yǔ)言，以ISE作為軟件開(kāi)發(fā)平臺(tái)，準(zhǔn)確地實(shí)現(xiàn)了秒表計(jì)數(shù)、清零、暫停等功能，并使用ModelSim仿真軟件對(duì)VHDL程序?qū)崿F(xiàn)了電路仿真，完成了綜合布局布線，最終將程序下載到芯片Spa

3、rtan-3A，并通過(guò)板子上相應(yīng)模塊驗(yàn)證實(shí)驗(yàn)的正確性。除此以外，利用課余時(shí)間學(xué)習(xí)數(shù)字頻率計(jì)的硬件實(shí)現(xiàn)方法，即用MultiSim仿真等。 秒表設(shè)計(jì)的具體要求：計(jì)時(shí)范圍是000000到595999。有兩個(gè)按鈕開(kāi)關(guān)start/stop和split/reset，控制秒表的啟動(dòng)、停止、分段和復(fù)位：秒表已經(jīng)被復(fù)位的情況下，按下state/stop鍵，秒表開(kāi)始計(jì)時(shí)。在秒表正常運(yùn)行的情況下，如果按下state/reset則秒表暫停計(jì)時(shí)；再次按下該鍵，秒表繼續(xù)計(jì)時(shí)。在秒表正常運(yùn)行下，如果按下split/reset，顯示停止在按鍵時(shí)的時(shí)間，但秒表仍然在計(jì)時(shí)；再次按下該鍵，秒表恢復(fù)正常顯示。在秒表暫停計(jì)時(shí)的情況下，

4、按下split/reset，秒表復(fù)位歸零。2.VHDL簡(jiǎn)介：2.1 VHDL特點(diǎn)：（1）作為HDL的第一個(gè)國(guó)際標(biāo)準(zhǔn)，VHDL具有很強(qiáng)的可移植性。 （2）具有豐富的模擬仿真語(yǔ)句和庫(kù)函數(shù)，隨時(shí)可對(duì)設(shè)計(jì)進(jìn)行仿真模擬，因而能將設(shè)計(jì)中的錯(cuò)誤消除在電路系統(tǒng)裝配之前，在設(shè)計(jì)早期就能檢查設(shè)計(jì)系統(tǒng)功能的可行性，有很強(qiáng)的預(yù)測(cè)能力。 （3）VHDL有良好的可讀性，接近高級(jí)語(yǔ)言，容易理解。 （4）系統(tǒng)設(shè)計(jì)與硬件結(jié)構(gòu)無(wú)關(guān)，方便了工藝的轉(zhuǎn)換，也不會(huì)因工藝變化而使描述過(guò)時(shí)。 （5）支持模塊化設(shè)計(jì)，可將大規(guī)模設(shè)計(jì)項(xiàng)目分解成若干個(gè)小項(xiàng)目，還可以把已有的設(shè)計(jì)項(xiàng)目作為一個(gè)模塊調(diào)用。 

5、;（6）對(duì)于用VHDL完成的一個(gè)確定設(shè)計(jì)，可以利用EDA工具進(jìn)行邏輯綜合和優(yōu)化，并能自動(dòng)地把VHDL描述轉(zhuǎn)變成門電路級(jí)網(wǎng)表文件。 （7）設(shè)計(jì)靈活，修改方便，同時(shí)也便于設(shè)計(jì)結(jié)果的交流、保存和重用，產(chǎn)品開(kāi)發(fā)速度快，成本低。2.2 VHDL設(shè)計(jì)流程：（1文本編輯:用任何文本編輯器都可以進(jìn)行，也可以用專用的HDL編輯環(huán)境。 （2)功能仿真:將文件調(diào)入HDL仿真軟件進(jìn)行功能仿真，檢查邏輯功能是否正確。 (3)邏輯綜合:將源文件調(diào)入邏輯綜合軟件進(jìn)行綜合，即把語(yǔ)言綜合成最簡(jiǎn)的布爾表達(dá)式。 (4)時(shí)序仿真:需要利用在布局布線中獲得的精確參數(shù)，用仿真軟件驗(yàn)證電路的時(shí)序。 (5)器件編程:對(duì)使用的元件可

6、以進(jìn)行編程。3.秒表設(shè)計(jì)：3.1 原理框圖：Seg6:0計(jì)數(shù)器晶振鎖存器分頻器掃描顯示控制(包括掃描控制和顯示譯碼)計(jì)數(shù)清零鎖存按鍵開(kāi)關(guān)LED顯示電路按鍵消抖1kHzDig7:0控制電路3.2 設(shè)計(jì)模塊化：由以上原理圖可實(shí)現(xiàn)秒表設(shè)計(jì)的模塊化，具體而言，可以分為6個(gè)模塊：分頻器：對(duì)晶體振蕩器產(chǎn)生的時(shí)鐘信號(hào)進(jìn)行分頻，產(chǎn)生時(shí)間基準(zhǔn)信號(hào)。計(jì)數(shù)器：對(duì)時(shí)間基準(zhǔn)脈沖進(jìn)行計(jì)數(shù)，完成計(jì)時(shí)功能。注：其中包含了一個(gè)1kHz到100Hz的分頻器，合并在一個(gè)模塊里。數(shù)據(jù)鎖存器：鎖存數(shù)據(jù)，使顯示保持鎖定?？刂破鳎嚎刂朴?jì)數(shù)器的運(yùn)行、暫停以及復(fù)位；產(chǎn)生鎖存器的是能信號(hào)。掃描顯示的控制電路：包括掃描計(jì)數(shù)器、和7段譯碼器；控制8

7、個(gè)數(shù)碼管以掃描方式顯示計(jì)時(shí)結(jié)果。按鍵消抖電路：消除按鍵輸入信號(hào)抖動(dòng)的影響，輸出單脈沖。每個(gè)模塊調(diào)試后可通過(guò)頂層文件共同構(gòu)成秒表的總電路。3.3 模塊的功能簡(jiǎn)述： 分頻器：秒表設(shè)計(jì)中共需要兩種分頻器。一種是通過(guò)模為48000的計(jì)數(shù)器進(jìn)位輸出實(shí)現(xiàn)將晶體振蕩器產(chǎn)生的48MHz的時(shí)鐘信號(hào)轉(zhuǎn)化為1KHz的時(shí)鐘信號(hào)作為基準(zhǔn)，方便下面各個(gè)模塊的取用。另一種是通過(guò)模為10的計(jì)數(shù)器進(jìn)位輸出將上述1KHz的時(shí)鐘信號(hào)轉(zhuǎn)化為100Hz的時(shí)鐘信號(hào)，作為計(jì)數(shù)器的時(shí)鐘輸入。注：實(shí)際設(shè)計(jì)中，第二種分頻器被劃歸到計(jì)數(shù)器模塊，實(shí)現(xiàn)與原理圖的匹配。3.3.2 計(jì)數(shù)器：計(jì)數(shù)器功能是通過(guò)輸入的時(shí)鐘信號(hào)實(shí)現(xiàn)計(jì)數(shù)功能，在秒表設(shè)計(jì)里，共需要

8、4個(gè)模10計(jì)數(shù)器和2個(gè)模6計(jì)數(shù)器。具體而言，其中2個(gè)模10計(jì)數(shù)器和2個(gè)模6計(jì)數(shù)器分別級(jí)聯(lián)產(chǎn)生2個(gè)模60計(jì)數(shù)器，實(shí)現(xiàn)了到秒和到分的進(jìn)位。而其他的兩個(gè)模10計(jì)數(shù)器則是2位模10計(jì)數(shù)。3.3.3 數(shù)據(jù)鎖存器：它是一個(gè)控制端控制的組合邏輯電路，實(shí)現(xiàn)了暫時(shí)鎖存數(shù)據(jù)的功能。 顯示譯碼模塊：顯示譯碼管外聯(lián)部分示意圖：內(nèi)部原理圖：功能是：從鎖存器接入數(shù)據(jù)，通過(guò)掃描計(jì)數(shù)的輸出來(lái)控制多路復(fù)用的數(shù)據(jù)選擇端口和三八譯碼器的輸入端口，使其數(shù)據(jù)變化相同。38譯碼器的輸出進(jìn)行位選，bcd的輸出進(jìn)行段選使其能在顯示譯碼管顯示完整數(shù)據(jù)。注：本實(shí)驗(yàn)電路板使用共陽(yáng)極，即低電平有效。3.3.5 控制模塊：功能是產(chǎn)生實(shí)現(xiàn)秒表的暫停or

9、開(kāi)始，鎖存or清零功能。具體而言產(chǎn)生三個(gè)輸出控制信號(hào)：清零，計(jì)數(shù)，鎖存。實(shí)現(xiàn)方法：Mealy機(jī)或者是Moore機(jī)方式，區(qū)別是有一個(gè)狀態(tài)的不同。實(shí)現(xiàn)原理圖: 按鍵消抖模塊：功能是消除按鍵輸入信號(hào)的影響，輸出單脈沖。方便實(shí)現(xiàn)兩個(gè)按鍵對(duì)秒表的瞬時(shí)控制。3.3.7 頂層文件：實(shí)現(xiàn)各個(gè)模塊之間的連接匹配，同時(shí)分配實(shí)際電路板的引腳。4. 模塊電路仿真：4.1 分頻器：4.2 計(jì)數(shù)器：4.2.1 模6計(jì)數(shù)器：4.2.2 模10計(jì)數(shù)器：5. 實(shí)驗(yàn)總結(jié)：5.1 實(shí)驗(yàn)結(jié)果：經(jīng)過(guò)測(cè)試，可以由FPGA板上的key-7，key-8控制秒表實(shí)現(xiàn)開(kāi)始暫停鎖存清零的相應(yīng)功能，其它功能基本符合要求。另一方面，通過(guò)Modesim

10、仿真，可以測(cè)試各程序模塊，并且可以清楚看到各模塊仿真結(jié)果與其功能相符合。5.2 心得總結(jié)：本次EDA實(shí)驗(yàn)大致經(jīng)歷了一個(gè)多星期，這段時(shí)間里我學(xué)到了很多東西。剛開(kāi)始我對(duì)VHDL語(yǔ)言的一無(wú)所知而且顯得無(wú)從下手，在調(diào)整心態(tài)后我開(kāi)始仔細(xì)了解和掌握課件中有關(guān)于VHDL的語(yǔ)句，設(shè)計(jì)流程和調(diào)試方法，在對(duì)這些有一定理解的基礎(chǔ)上，我又看了幾個(gè)VHDL應(yīng)用的小例子，增加對(duì)原理的熟悉度。在編調(diào)試頂層文件的程序時(shí)，各元件之間的連接定義方法和關(guān)系讓我糾結(jié)了好久，最后在別人的建議下，我先畫出模塊連接框圖，明確定義了各個(gè)輸入和輸出的類型和變量。在此基礎(chǔ)上設(shè)計(jì)秒表的VHDL語(yǔ)言，顯得條理清晰和檢查糾錯(cuò)方便。通過(guò)這次實(shí)驗(yàn)，我懂得

11、了理論與實(shí)際相結(jié)合是很重要的，只有把所學(xué)的理論知識(shí)與實(shí)踐相結(jié)合起來(lái)，從理論中得出結(jié)論，才能真正理解并掌握其中的原理方法，從而提高自己的實(shí)際動(dòng)手能力和獨(dú)立思考的能力。在設(shè)計(jì)的過(guò)程中遇到問(wèn)題，發(fā)現(xiàn)了自己的不足之處，這是不可避免的。但更重要的是我們要有自己解決問(wèn)題的思路和方法，這樣才能不斷完善自己。希望以后能有更多的動(dòng)手實(shí)踐機(jī)會(huì)，在硬件實(shí)踐中發(fā)現(xiàn)自己的不足，彌補(bǔ)自己的不足。最后，特別感謝老師對(duì)我的幫助，讓我最終順利完成秒表的設(shè)計(jì)實(shí)驗(yàn)。6. 參考文獻(xiàn): 1李國(guó)洪、胡輝、沈明山.EDA技術(shù)與實(shí)驗(yàn).機(jī)械工業(yè)出版社，2009 2閆石數(shù)字電子技術(shù)基礎(chǔ)（第五版）高等教育出版社，20063 （美）John F.W

12、akerly.數(shù)字設(shè)計(jì)：原理與實(shí)踐（原書第四版）.北京：機(jī)械工業(yè)出版社，2007.57. 附錄（各模塊源程序）：（1）分頻器：48MHz到1KHz分頻器：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_Unsigned.All;- Uncomment the following library declaration if using- arithmetic functions with Signed or Unsigned values-use IEEE.NUMERIC_STD.ALL;- Uncomment the f

13、ollowing library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity fp48m_to_1k is port ( clk : in STD_LOGIC; q : out STD_LOGIC);end fp48m_to_1k;architecture Behavioral of fp48m_to_1k issignal sum:std_logic_vector(15 downto 0):=(others

14、=>'0');signal q1:std_logic:='0'beginprocess(clk)beginif falling_edge(clk) then if sum=47999 then sum<=(others=>'0');else sum<=sum+1;end if;end if;-q<=q1;end process;q<=sum(15);end Behavioral;1KHz到100Hz分頻器：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD

15、_LOGIC_Unsigned.All;- Uncomment the following library declaration if using- arithmetic functions with Signed or Unsigned values-use IEEE.NUMERIC_STD.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;enti

16、ty fp1k_to_100 is port ( clk : in STD_LOGIC; q : out STD_LOGIC);end fp1k_to_100;architecture Behavioral of fp1k_to_100 issignal sum:std_logic_vector(2 downto 0):=(others=>'0');signal q1:std_logic:='0'beginprocess(clk)beginif falling_edge(clk) then if sum=4 then sum<=(others=>

17、;'0');q1<=not q1;else sum<=sum+1;end if;end if;q<=q1;end process;end Behavioral;（2）計(jì)數(shù)器：模6計(jì)數(shù)器：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_unsigned.ALL;- Uncomment the following library declaration if using- arithmetic functions with Signed or Unsigned values-use IEEE.

18、NUMERIC_STD.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity cnt_6 is Port ( clk : in STD_LOGIC; clr : in STD_LOGIC; en : in STD_LOGIC; co : out STD_LOGIC; sum : out STD_LOGIC_VECTOR (2 downto 0)

19、;end cnt_6;architecture Behavioral of cnt_6 issignal temp:std_logic_vector(2 downto 0);beginprocess(clk,clr,temp)beginif clr='1' then temp<="000"co<='0'elsif (clk='1' and clk'event) thenif en='1' thenif temp="101" thentemp<="000&q

20、uot;else temp<=temp+1;end if;end if;end if;if temp="101" and en='1' thenco<='1'else co<='0'end if;sum<=temp;end process;end Behavioral;模10計(jì)數(shù)器：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_unsigned.ALL;- Uncomment the following library decla

21、ration if using- arithmetic functions with Signed or Unsigned values-use IEEE.NUMERIC_STD.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity cnt_10 is Port ( clk : in STD_LOGIC; clr : in STD_LOGIC;

22、 en : in STD_LOGIC; co : out STD_LOGIC; sum : out STD_LOGIC_VECTOR (3 downto 0);end cnt_10;architecture Behavioral of cnt_10 issignal temp:std_logic_vector(3 downto 0);beginprocess(clk,clr,temp)beginif clr='1' then temp<="0000"co<='0'elsif (clk='1' and clk'

23、;event) thenif en='1' thenif temp="1001" thentemp<="0000"else temp<=temp+1;end if;end if;end if;if temp="1001" and en='1' thenco<='1'else co<='0'end if;sum<=temp;end process;end Behavioral;計(jì)數(shù)器模塊級(jí)聯(lián)：library IEEE;use IEEE.STD_

24、LOGIC_1164.ALL;- Uncomment the following library declaration if using- arithmetic functions with Signed or Unsigned values-use IEEE.NUMERIC_STD.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity ji

25、shuqi is Port ( clk : in STD_LOGIC; clr : in STD_LOGIC; cnt : in STD_LOGIC; cout0 : out STD_LOGIC_VECTOR (3 downto 0); cout1 : out STD_LOGIC_VECTOR (3 downto 0); cout2 : out STD_LOGIC_VECTOR (3 downto 0); cout3 : out STD_LOGIC_VECTOR (2 downto 0); cout4 : out STD_LOGIC_VECTOR (3 downto 0); cout5 : o

26、ut STD_LOGIC_VECTOR (2 downto 0); coa : out std_logic);end jishuqi;architecture Behavioral of jishuqi isCOMPONENT fp1k_to_100PORT(clk : IN std_logic; q : OUT std_logic);END COMPONENT;COMPONENT cnt_10PORT(clk : IN std_logic;clr : IN std_logic;en : IN std_logic; co : OUT std_logic;sum : OUT std_logic_

27、vector(3 downto 0);END COMPONENT;COMPONENT cnt_6PORT(clk : IN std_logic;clr : IN std_logic;en : IN std_logic; co : OUT std_logic;sum : OUT std_logic_vector(2 downto 0);END COMPONENT;signal clk_100, o1,o2,o3,o4,o5 : std_logic;beginInst_fp1k_to_100: fp1k_to_100 PORT MAP(clk =>clk,q =>clk_100);In

28、st_cnt_10a: cnt_10 PORT MAP(clk =>clk_100 ,clr =>clr ,en =>cnt ,co =>o1 ,sum =>cout0 );Inst_cnt_10b: cnt_10 PORT MAP(clk =>clk_100 ,clr =>clr ,en =>o1,co =>o2 ,sum =>cout1 );Inst_cnt_10c: cnt_10 PORT MAP(clk =>clk_100 ,clr =>clr ,en =>o2 ,co =>o3 ,sum =>c

29、out2 );Inst_cnt_6a: cnt_6 PORT MAP(clk =>clk_100 ,clr =>clr ,en =>o3 ,co =>o4 ,sum =>cout3 );Inst_cnt_10d: cnt_10 PORT MAP(clk =>clk_100 ,clr =>clr ,en =>o4 ,co =>o5 ,sum =>cout4 );Inst_cnt_6b: cnt_6 PORT MAP(clk =>clk_100 ,clr =>clr ,en =>o5 ,co =>coa ,sum

30、=>cout5 );end Behavioral;（3）數(shù)據(jù)鎖存器：library IEEE;use IEEE.STD_LOGIC_1164.ALL;- Uncomment the following library declaration if using- arithmetic functions with Signed or Unsigned values-use IEEE.NUMERIC_STD.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in

31、this code.-library UNISIM;-use UNISIM.VComponents.all;entity latch is Port ( cnt_0 : in STD_LOGIC_VECTOR (3 downto 0); cnt_1 : in STD_LOGIC_VECTOR (3 downto 0); cnt_2 : in STD_LOGIC_VECTOR (3 downto 0); cnt_3 : in STD_LOGIC_VECTOR (3 downto 0); cnt_4 : in STD_LOGIC_VECTOR (3 downto 0); cnt_5 : in ST

32、D_LOGIC_VECTOR (3 downto 0); display_in : in STD_LOGIC; cnt0 : out STD_LOGIC_VECTOR (3 downto 0); cnt1 : out STD_LOGIC_VECTOR (3 downto 0); cnt2 : out STD_LOGIC_VECTOR (3 downto 0); cnt3 : out STD_LOGIC_VECTOR (3 downto 0); cnt4 : out STD_LOGIC_VECTOR (3 downto 0); cnt5 : out STD_LOGIC_VECTOR (3 dow

33、nto 0);end latch;architecture Behavioral of latch isbeginprocess(cnt_0,cnt_1,cnt_2,cnt_3,cnt_4,cnt_5,display_in)beginif display_in='1' thencnt0<=cnt_0;cnt1<=cnt_1;cnt2<=cnt_2;cnt3<=cnt_3;cnt4<=cnt_4;cnt5<=cnt_5;end if;end process;end Behavioral;（4）顯示譯碼模塊：library IEEE;use IE

34、EE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_unsigned.ALL;- Uncomment the following library declaration if using- arithmetic functions with Signed or Unsigned values-use IEEE.NUMERIC_STD.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISI

35、M;-use UNISIM.VComponents.all;entity display is Port ( clk_1k : in STD_LOGIC; cnt0 : in STD_LOGIC_VECTOR (3 downto 0); cnt1 : in STD_LOGIC_VECTOR (3 downto 0); cnt2 : in STD_LOGIC_VECTOR (3 downto 0); cnt3 : in STD_LOGIC_VECTOR (3 downto 0); cnt4 : in STD_LOGIC_VECTOR (3 downto 0); cnt5 : in STD_LOG

36、IC_VECTOR (3 downto 0); dig_out : out STD_LOGIC_VECTOR (7 downto 0); seg_out : out STD_LOGIC_VECTOR (6 downto 0); dig_in : out std_logic_vector (2 downto 0) );end display;architecture Behavioral of display issignal bcd: std_logic_vector(3 downto 0):="1000"signal seg: std_logic_vector(6 dow

37、nto 0):="1111110"signal dig: std_logic_vector(2 downto 0):="000"beginprocess(clk_1k)beginif clk_1k'event and clk_1k='1' thenif dig=7 then dig<="000"elsedig<=dig+1;end if;end if;end process;process(dig)begincase dig iswhen "000"=>dig_out<

38、;="11111110"when "001"=>dig_out<="11111101"when "010"=>dig_out<="11111011"when "011"=>dig_out<="11110111"when "100"=>dig_out<="11101111"when "101"=>dig_out<="1101111

39、1"when "110"=>dig_out<="10111111"when others=>dig_out<="01111111"end case;end process;process(dig)begincase dig iswhen "000"=>bcd<=cnt0;when "001"=>bcd<=cnt1;when "010"=>bcd<="1010"when "011

40、"=>bcd<=cnt2;when "100"=>bcd<=cnt3;when "101"=>bcd<="1010"when "110"=>bcd<=cnt4;when "111"=>bcd<=cnt5;when others=>bcd<="1010"end case;end process;process(bcd)begincase bcd iswhen "0000"=&g

41、t;seg<="0000001"when "0001"=>seg<="1001111"when "0010"=>seg<="0010010"when "0011"=>seg<="0000110"when "0100"=>seg<="1001100"when "0101"=>seg<="0100100"when &

42、quot;0110"=>seg<="0100000"when "0111"=>seg<="0001111"when "1000"=>seg<="0000000"when "1001"=>seg<="0000100"when others=>seg<="1111110"end case;end process;seg_out<=seg;end Behavioral

43、;（5）控制模塊：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_unsigned.ALL;- Uncomment the following library declaration if using- arithmetic functions with Signed or Unsigned values-use IEEE.NUMERIC_STD.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives

44、 in this code.-library UNISIM;-use UNISIM.VComponents.all;entity control is Port ( clk : in STD_LOGIC; p : in STD_LOGIC; q : in STD_LOGIC; clr : out STD_LOGIC; enc : out STD_LOGIC; enl : out STD_LOGIC);end control;architecture Behavioral of control issignal state:std_logic_vector(1 downto 0):="

45、00"signal n_state:std_logic_vector(1 downto 0):="00"signal key:std_logic_vector(1 downto 0);beginkey<=p & q;process(state,key)begincase state iswhen "00"=>if key="10" thenn_state<="01"elsen_state<=state;end if;when "01"=>case

46、key iswhen "10"=>n_state<="11"when "01"=>n_state<="10"when others=>n_state<=state;end case;when "10"=>if key="01" then n_state<="01"else n_state<=state;end if;when others=>case key iswhen "10&quo

47、t;=>n_state<="01"when "01"=>n_state<="00"when others=>n_state<=state;end case;end case;end process; process(clk)beginif falling_edge(clk) then state<=n_state;end if;end process; process(state)begincase state iswhen "00"=>clr<='1&

48、#39;enc<='1'enl<='1'when "01"=>clr<='0'enc<='1'enl<='1'when "10"=>clr<='0'enc<='1'enl<='0'when others=>clr<='0'enc<='0'enl<='1'end case;end process;en

49、d Behavioral;（6）按鍵消抖模塊：消抖：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_unsigned.ALL;- Uncomment the following library declaration if using- arithmetic functions with Signed or Unsigned values-use IEEE.NUMERIC_STD.ALL;- Uncomment the following library declaration if instantiating- any

50、Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity xiaodou is Port ( clk : in STD_LOGIC; key_in : in STD_LOGIC; key_out : out STD_LOGIC);end xiaodou;architecture Behavioral of xiaodou issignal k1,k2: STD_LOGIC;signal cnt : STD_LOGIC_VECTOR (1 downto 0);beginprocess(clk

51、,key_in)beginif clk'event and clk ='0' thenif cnt =3 thenk1<='1'elsek1<='0'cnt<=cnt+1;end if;k2<=k1;end if;if key_in ='0' thencnt <="00"end if;end process;key_out <= not k1 and k2;end Behavioral;開(kāi)關(guān)消抖組合：library IEEE;use IEEE.STD_LOGIC_1164.ALL;- Uncomment the following library declaration if using- arithmetic functions with Signed or Unsigned values-use IEEE.NUMERIC_STD.ALL;- Uncomment the following library decl