verilogFPGA狀態(tài)機(jī)描述ppt課件

1、3-1Example: Example: 一段式形狀機(jī)一段式形狀機(jī)描畫(huà)方法描畫(huà)方法 stop: begin if ( A ) begin state = clear; K2 = 1; end else state = stop; end clear: begin if ( !A) begin state = idle ; K2,K1 = 2b01; end else state = clear ; end endcase endmodule module Mealy_state_machine (clock, reset, A, K2, K1 ); input clock, reset, A;

2、 output K2, K1; reg K2, K1; reg 1,0 state; parameter idle =2b00, start =2b01; stop =2b10, clear =211; always (posedge clock or negedge reset) if (!reset) begin state = idle; K2,K1 = 2b00; end else case (state) idle: begin if ( A) begin state = start ; K1 = 0; end else state = idle ; endstart: begin

3、if ( !A) state = stop ; else state = start ; end 3.5 形狀機(jī)描畫(huà)方法形狀機(jī)描畫(huà)方法3-2module state_machine (clock, reset, rdy, r_w, oe, we); input clock, reset; input rdy, r_w; output oe,we; reg oe,we; reg 3,0 present_state, next_state; parameter idle =4b0001, decision=4b0010; read=4b0100, write=41000; / sequential

4、 state transition always (posedge clock or negedge reset ) if ( !reset ) present_state = idle ; else present_state = next_state ; /combinational block always (reset or present_state or rdy or r_w) begin case (present_state) idle: begin oe,we = 2b00; if ( rdy) next_state = decision ; else next_state

5、= idle ; enddecision: begin oe,we = 2b00; if ( r_w) next_state = read ; else next_state = write ; end read: begin oe,we = 2b10; if ( rdy) next_state = idle ; else next_state = read; end write: begin oe,we = 2b01; if ( rdy) next_state = idle ; else next_state = write ; end default: begin oe,we = 2b00

6、; next_state = 4bx ; end endcase end / end always begin endmodule;rdyrdyrdyr_wr_wResetrdyrdyidle00decision00write01read10StateidledecisionwritereadOutputsoe0001we0010Example: Example: 兩段式形狀機(jī)兩段式形狀機(jī)描畫(huà)方法引薦描畫(huà)方法引薦3-3module state_machine (clock, reset, rdy, r_w, oe, we); input clock, reset; input rdy, r_w

7、; output oe,we; reg oe,we; reg 3,0 present_state, next_state; parameter idle =4b0001, decision=4b0010; read=4b0100, write=41000; / sequential state transition always (posedge clock or negedge reset ) if ( ! reset ) present_state = idle ; else present_state = next_state ; /combinational block always

8、(reset or present_state or rdy or r_w) begin case(present_state) idle: begin idle_output; if ( rdy) next_state = decision ; else next_state = idle ; enddecision: begin decision_output; if ( r_w) next_state = read ; else next_state = write ; end read: begin read_output; if ( rdy) next_state = idle ;

9、else next_state = read; end write: begin write_output; if ( rdy) next_state = idle ; else next_state = write ; end default: begin idle_output; next_state = 4bx ; end endcase end /end always begin/output taskstask idle_output; oe,we = 2b00;endtasktask decision_output; oe,we = 2b00;endtasktask read_ou

10、tput; oe,we = 2b10;endtasktask write_output; oe,we = 2b01;endtaskendmodule;Example: Example: 兩段式形狀機(jī)描畫(huà)運(yùn)用兩段式形狀機(jī)描畫(huà)運(yùn)用tasktask引薦編碼引薦編碼3-4module state_machine (clock, reset, rdy, r_w, oe, we); input clock, reset; input rdy, r_w; output oe,we; reg oe,we; reg 3,0 present_state, next_state; parameter idle =4

11、b0001, decision=4b0010; read=4b0100, write=41000; / sequential state transition always (posedge clock or negedge reset ) if ( ! reset ) present_state = idle ; else present_state = next_state ; /combinational block always (reset or present_state or rdy or r_w) begin case (present_state) idle: begin i

12、f ( rdy) next_state = decision ; else next_state = idle ; enddecision: begin if ( r_w) next_state = read ; else next_state = write ; end read: begin if ( rdy) next_state = idle ; else next_state = read; end write: begin if ( rdy) next_state = idle ; else next_state = write ; end default: begin next_state = 4bx ; end endcase end /end always begin/Registered outputalways (posedge clock or negedge reset ) if ( ! res