68HC11PollingandInterrupts

1、168HC11 Polling and InterruptsChapter 82Polling and Interrupts CPU may need to provide support (called a service) to external devices. How? We can POLL devices We can have an Interrupt system We can have a combination of the two3Polling “Ask” each device sequentially if it needs service. Note, no de

2、vices may need servicing during the poll.4Interrupts6811IRQDevice 1Data BusPortsDevice “interrupts” CPU to indicate that it needs service.568HC11 Interrupts Interrupt system is “built-in” to 6811 Special interrupt software instructions Special interrupt hardware resources What needs to interrupt? Ex

3、ternal Devices Keyboards, Mouse, Sensors, etc. Internal Events Reset, Illegal Operation, User Interrupt, etc6Types of Interrupts Maskable The program can choose to “ignore” a maskable interrupt by setting the I bit equal to 1 in the CCR. This is called “masking” the interrupt. Setting the I bit = 0

4、“unmasks” the interrupt, allowing interrupts to be serviced. SXHINZVCCondition Code Register7Types of Interrupts Non-maskable interrupts A program cannot choose to ignore a non-maskable interrupt. A non-maskable interrupt is used for events that must always be serviced. Example: Reset A special subr

5、outine called an Interrupt Service Routine (ISR) is used to service the interrupt8Interrupt Service Routines(ISR)9Interrupt Service Routine (ISR) ISR is a special subroutine that is designed to “service” the interrupt Also called an “interrupt handler” Lets examine the interrupt process10Interrupt P

6、rocess Interrupt occurs CPU waits until the current instruction has finished being executed. Note: PC is pointing to next instruction to execute All CPU registers including the program counter (PC) and condition code register (CCR) are pushed onto stack Interrupt bit is set (STI) to mask further int

7、errupts. In most cases, you dont want the ISR to itself be interrupted. The PC is loaded with address of the Interrupt Service Routine (ISR) ISR is executed. The last instruction in the ISR must be RTI. RTI = Return from Interrupt11Return from Interrupt Your ISR should almost always end with a RTI i

8、nstruction RTI Return from Interrupt What does RTI do? Pulls all registers from stack. The I bit in the pulled CCR is clear, so interrupts are enabled. PC contains address of next instruction Continues interrupted program12Example of ISR13LED Circuit ExampleRVCCLight OnRVCCLight OffSwitch14Polling E

9、xample1568HC11 LED ExamplePolling ExamplePseudo-code (Polling)* Use PA0 for Input, PA6 for output Configure PortA ; RepeatIF(PA0=0) thenPA6=0 ; Turn LED OFFElsePA6=1; Turn LED ONEndIF Until Forever16Symbols*SymbolsData EQU $0000 ; This is the address of the data spaceProgram EQU $E000 ; This is the

10、start of the program spaceReset EQU $FFFE ; This is the reset vector* ConstantsPORTA EQU $1000 ; Port A AddressPACTL EQU $1026 ; Port A Control RegisterPACONF EQU %00000000 ; This configs PortA for I/O modeLED_BIT EQU %01000000 ; This it the LED bitMASK EQU %00000001 ; This is the input bit mask*17P

11、olling Example* Program ORG Program ; start of ProgramStart: LDAA #PACONF ; Load Port A conf bits STAA PACTL ; Configure port A* Lets use If(Bit2 = 0) then LED OFF, Else LED ON*Loop: LDX #PortA ; Load X with address of port A BRCLR 0,X MASK LED_OFF ; Branch to LED_OFF if PA0 = 0 BSET 0,X LED_BIT ; T

12、urn on LED Bit BRA Loop ; Check switch againLED_OFF: BCLR 0,X LED_BIT ; Turn the LED OFF BRA Loop ; Check switch againNote: This program continually checks to switch18Interrupt Example1968HC11 LED ExampleInterrupt ExamplePseudo-code (Interrupt)* Use PA6 for output Configure PortA ; Enable Interrupts

13、 Execute any program ISR: *Executed only when interrupt occursRead PortAIf PA0=0 Then LED=0 Else LED=1Return from Interrupt20Symbols*SymbolsData EQU $0000 ; This is the address of the data spaceProgram EQU $E000 ; This is the start of the program spaceReset EQU $FFFE ; This is the reset vectorIRQ EQ

14、U $FFF2 ; This is the IRQ vector* ConstantsPORTA EQU $1000 ; Port A AddressPACTL EQU $1026 ; Port A Control RegisterPACONF EQU %00000000 ; This configs PortA for I/O modeLED_BIT EQU %01000000 ; This is the LED bitMask EQU %00000001 ; This is the input bit*21Interrupt Example* Program ORG Program ; s

15、tart of ProgramTop: LDAA #PACONF ; Load Port A conf bits STAA PACTL ; Configure port A CLI ; Enable interrupts* The main program can do anything * Lets just wait*Loop: BRA Loop* This is the ISR. It will only execute when an interrupt occurs*ISR: LDX #PORTA BRCLR 0,X MASK LED_OFF ; If input=0 then Go

16、to LED_OFFLED_ON: BSET 0,X LED_BIT ; Turn LED ON BRA Done ; We are doneLED_OFF: BCLR 0,X LED_BIT ; Turn LED OFFDone: RTI ; Return from interrupt 22Interrupt Example ORG IRQ ; Need to set ISR vector FDB ISR ORG RESET ; Set Reset interrupt vector FDB Top 23Summary Polling InterruptSwitch Input: PA0 PA

17、0 and IRQMain Program: Checks Switch AnythingISR: Not needed Required24Interrupt Service Routine Where is the address to the ISR? The address of the ISR is stored in the Interrupt Vector Table. 68HC11 Interrupt Vector Table $FFC0-$FFFF (2 bytes for each interrupt) Example: Reset “interrupt” vector i

18、s at address $FFFE:$FFFF25Setting Vectors in Interrupt Vector Table (IVT) I_Vector EQU Vector Address ORG I_Vector FDB ISR Example: Reset EQU $FFFE ORG Reset FDB TOP2668HC11 Interrupt Vector Table Serial Systems (SCI and SPI) SCI: $FFD6:$FFD7 SPI: $FFD8:$FFD9 Timer System IRQ and XIRQ Interrupts IRQ

19、: $FFF2:FFF3 XIRQ: $FFF4:FFF5 Software Interrupts SWI, Illegal Opcode Fetch SWI: $FFF6:FFF7 Hardware Interrupts COP failure, Clock Monitor Failure, Reset27Software ExampleIRQ and ResetIRQ Vector :$FFF2:FFF3Reset Vector: $FFFE:FFFF28IRQ ExampleIRQ EQU $FFF2 ; This is the address of the IRQ interruptP

20、ORTB EQU $1004 ; Port B AddressZero EQU %00000000 ; 00DCHAR EQU %01010101 ; 55*ORGProgram ; start of ProgramStart: CLI ; Enable interrupts LDS #Stack ; Set stack pointerLoop: LDAA #Zero ; Clear byte STAA PortB BRA Loop ; Stay here *ISR: LDAA #DCHAR STAA PORTB ; Store A register into port b RTI ; Ret

21、urn from interrupt* IRQ Vector ORG IRQ ; Point Assembler to SWI address FDB ISR* Reset Vector ORGReset;reset vector FDB Start;set to start of programIf IRQ occurs, then the programat address ISR is executed.If Reset occurs, then the program at address Start is executed. 29TPS Quiz30Nonmaskable Inter

22、ruptsSection 8.531Nonmaskable Interrupts Nonmaskable interrupts cannot be ignored Several types External hardware interrupts Internal hardware interrupts Software interrupts3268HC11 Nonmaskable Interrupts Reset External hardware interrupt Reset Pin (Active low) Vector: $FFFE:FFFF SWI Instruction Sof

23、tware interrupt Vector: $FFF6:FFF7 Computer Operating Failure (COP) Internal hardware interrupt Watchdog timer: Chapter 10 Vector: $FFFA:FFFB3368HC11 Nonmaskable Interrupts Illegal Opcode Trap Software Interrupt Vector: $FFF8:FFF9 Nonmaskable Interrupt Request (XIRQ) External hardware interrupt XIRQ

24、 Pin Vector: $FFF4:FFF53468HC11 XIRQ Interrupt Nonmaskable Interrupt Request (XIRQ) External hardware interrupt On reset, the XIRQ interrupt is disabled, the programmer must enable it by clearing the XIRQ bit. E.g. During the boot process Once the XIRQ is enabled, the programmer cannot disable it E.

25、g. Users cannot turn this off! External hardware interrupt XIRQ Pin Vector: $FFF4:FFF53568HC11 Interrupt Instructions SEI: SEt Interrupt mask: Set I bit to 1 Disables (masks) all maskable interrupts CLI: CLear Interrupt mask: Reset I bit to 0 Enables (unmasks) all maskable interrupts SWI: SoftWare I

26、nterrupt Generates software interrupt WAI: WAit for Interrupt Pushes all registers onto stack Places CPU into wait state Interrupt will “wake-up” controller RTI: Return from Interrupt Pulls all registers from stack Executes interrupted program36Advanced Interrupts Section 8.737Polling “Ask” each device