第3章 CMOS gates

1、Chapter 3 Logic GatesChapter 3 Logic Gates本章任務(wù)本章任務(wù) 1.1.學(xué)習(xí)各種門(mén)電路的邏輯功能；學(xué)習(xí)各種門(mén)電路的邏輯功能； 2.2.學(xué)習(xí)各種學(xué)習(xí)各種CMOSCMOS門(mén)電路的組成，門(mén)電路的組成，會(huì)分析邏輯門(mén)電路的邏輯結(jié)構(gòu)，會(huì)分析邏輯門(mén)電路的邏輯結(jié)構(gòu)，及等效的邏輯關(guān)系；及等效的邏輯關(guān)系； 3.3.學(xué)習(xí)學(xué)習(xí)CMOSCMOS、TTLTTL邏輯門(mén)的輸入輸出邏輯門(mén)的輸入輸出特性及接口電路；特性及接口電路； 4. 門(mén)電路的分類(lèi)：門(mén)電路的分類(lèi)： 按門(mén)電路的結(jié)構(gòu)分類(lèi)按門(mén)電路的結(jié)構(gòu)分類(lèi): : .CMOS . TTL .ECL 按門(mén)電路的規(guī)模分類(lèi)按門(mén)電路的規(guī)模分類(lèi): : .S

2、SI .MSI .LSI .VLSI（PLD =） .ASIC 1. 2. 3. 4. 5.返回返回返回返回返回返回UORdEdEGS 1.Logic level for CMOS Logic circuits 2.CMOS inverterLogic 1(high)Undefined stateLogic 0(Low)5.0v3.5v1.5v0vN-MOS P-MOS+G- SD- GS- D+SGDSGDG(U in)SDR+G- SDUDS-+UGS+-UDDRD-+UGSVoutVin0關(guān)關(guān)門(mén)門(mén)開(kāi)開(kāi)門(mén)門(mén)v+5v3.5v1.5vUDS(UGS)VinVoutVDD=+5vN-Channe

3、lp-ChannelQ2Q1VinQ1Q2Vout0.0V offon5.0v5.0vonoff0.00.0v5.0vVoutVin0關(guān)關(guān)門(mén)門(mén)開(kāi)開(kāi)門(mén)門(mén)v+5v3.5v1.5v3.5V1.5V 1. NAND gate 2.CMOS NOR gate 3.CMOS NONINVERTING BUFFER 4.AND-OR-NOT gate 5.OD. 6.EX-OR gate. 7.Three-state gates-1A BA B0 00 00 10 1 0 01 11 1T T1 1 T T2 2 T T3 3 T T4 4On onOn on off off off offOff Off

4、on on on offon offOnOn off off on off off onOff off Off off on onon onf f1 11 11 10 0&A BA B0 00 00 10 1 0 01 11 1T T1 1 T T2 2 T T3 3 T T4 4On onOn on off off off offOnOn off off on off off onOff Off on on on offon offOff off Off off on onon onf f1 10 00 00 01ppNNppNNQFABCDFABCDA B C DA B C D0 0 0

5、0 0 00 0 0 1 0 1 1 0 1 0 1 1 1 10 1 0 00 1 0 0 0 1 0 1 1 0 1 0 1 1 1 11 0 0 01 0 0 0 0 1 0 1 1 0 1 0 1 1 1 11 1 0 01 1 0 0 0 1 0 1 1 0 1 0 1 1 1 1T T1 1 T T2 2 T T3 3 T T4 4Off Off onon off off ononOn On on onOff Off onon on off on offOn On On On On off off On off off onon on on on onOnOn off off on

6、on off offOnOn off off onon off offOnOn off off onon off offOnOn off off onon off offf f1 11 11 10 0T T5 5 T T6 6 T T7 7 T T8 8Off Off onon off off ononOff Off onon on off on offOn off off On off off ononOnOn off off onon off offOff Off onon off on off onOff Off on on on offon offOn off off On off o

7、ff ononOnOn off off onon off offOff off on Off off on ononOff on Off on onon off offOn off off On off off ononOnOn off off onon off offOff off on onOff off on onOff on on offOff on on offOn off off onOn off off onOn On off off onon off off1 11 11 10 01 11 11 10 00 00 00 00 0A AB BC CD DVDDfT1T3T5T7T

8、2T4T6T8 1. 異或門(mén)及其應(yīng)用異或門(mén)及其應(yīng)用 (Ex-OR Gates & its Applications) 2.傳輸門(mén)及其應(yīng)用傳輸門(mén)及其應(yīng)用 (Transmission Gates & Applications) 3.三態(tài)門(mén)三態(tài)門(mén)(Tri-state Gate ) 4.漏極開(kāi)路門(mén)漏極開(kāi)路門(mén)(OD-Gat) 5.線線與與邏輯邏輯(Wiring “AND” Logic)F=AB+AB=1p(1).電路結(jié)構(gòu)電路結(jié)構(gòu)T7T8T9T10T5T6T4T3T2T1 電路符號(hào)電路符號(hào) 0 0 0 0 1 1 1 0 1 1 1 0EnDF=1DEnF DEnFABABAB可編程可編程同相門(mén)同相門(mén)可編

9、程可編程反相門(mén)反相門(mén)Lecture:p.86ABCONTROL(LOW / HIGH)F=A B C=C (A B) + C (A B)12A BCF01A B(A B)FA BF2=A B CABC ControlledApplication Example 3Q=1時(shí)，時(shí)，A0A6Odd1. Control=0，parity bit=1；. Control=1，parity bit=0；Q=0時(shí)，時(shí)，A0A6even 1. Control=0，parity bit=0；. Control=1，parity bit=1；QA7A0=EVEN1Out=0A7A0=Odd 1Out=1OutNo

10、. of inputs(A-I) that are highoutputsevenodd0,2,4,6,8, H L1,3,5,7,9, L HB3A3 B2A2 B1A1 B0A0Y1 What will be the x and y outputs from the circuit in below figure, if the A and B inputs are either out-of- phase or in phase? 波形輸入分析波形輸入分析ABABAB畫(huà)鑒相器輸出波形畫(huà)鑒相器輸出波形 Design a circuit witch will convert a 4-bit

11、Gray-coded number G1G2G3G4 to binary D1D2D3D4. Design a circuit witch will convert a 4-bit Gray-coded number G1G2G3G4 to binary D1D2D3D4. 設(shè)計(jì)一個(gè)電路，能夠?qū)崿F(xiàn)將設(shè)計(jì)一個(gè)電路，能夠?qū)崿F(xiàn)將4位格雷碼位格雷碼G1G2G3G4轉(zhuǎn)換成轉(zhuǎn)換成4位二進(jìn)制碼位二進(jìn)制碼D1D2D3D4.的功能。的功能。G3 G2 G1 G0B3 B2 B1 B00 0 0 00 0 0 00 0 0 10 0 0 10 0 1 10 0 1 00 0 1 00 0 1 10 1 1 00

12、1 0 00 1 1 10 1 0 10 1 0 10 1 1 00 1 0 00 1 1 11 1 0 01 0 0 01 1 0 11 0 0 11 1 1 11 0 1 01 1 1 01 0 1 11 0 1 01 1 0 01 0 1 11 1 0 11 0 0 11 1 1 01 0 0 01 1 1 1 用卡諾圖化簡(jiǎn)方法可以采用用卡諾圖化簡(jiǎn)方法可以采用 最小項(xiàng)積之和（最小項(xiàng)積之和（NANDNAND門(mén)）方法；門(mén)）方法； 也可采用和之積的方法（即也可采用和之積的方法（即NORNOR門(mén)）實(shí)現(xiàn)；門(mén)）實(shí)現(xiàn)； 第三種方法采用直接觀察法（第三種方法采用直接觀察法（XORXOR實(shí)現(xiàn)）；實(shí)現(xiàn)）；

13、第四種方法，采用第四種方法，采用XOR/NXOR XOR/NXOR 門(mén)實(shí)現(xiàn)的方法。門(mén)實(shí)現(xiàn)的方法。 引出卡諾圖對(duì)角鄰與偏鄰化簡(jiǎn)法。介紹單變量、引出卡諾圖對(duì)角鄰與偏鄰化簡(jiǎn)法。介紹單變量、雙變量和多個(gè)變量的卡諾圖對(duì)角鄰與偏鄰化簡(jiǎn)法。雙變量和多個(gè)變量的卡諾圖對(duì)角鄰與偏鄰化簡(jiǎn)法。 對(duì)角鄰對(duì)角鄰 F= A B對(duì)角鄰對(duì)角鄰 F= ABABAABBBBBAAA1.偏鄰偏鄰 （ A B）C CCAB2.偏鄰偏鄰 （ A B）C C1.對(duì)角鄰對(duì)角鄰 A（B C）2.對(duì)角鄰對(duì)角鄰 B（A C）3.對(duì)角鄰對(duì)角鄰 A（BC）4.對(duì)角鄰對(duì)角鄰 B（A C）0001101101G1 G2 G3 G4D1 D2 D3 D40

14、 0 0 00 0 0 00 0 0 10 0 0 10 0 1 10 0 1 00 0 1 00 0 1 10 1 1 00 1 0 00 1 1 10 1 0 10 1 0 10 1 1 00 1 0 00 1 1 11 1 0 01 0 0 01 1 0 11 0 0 11 1 1 11 0 1 01 1 1 01 0 1 11 0 1 01 1 0 01 0 1 11 1 0 11 0 0 11 1 1 01 0 0 01 1 1 11111111111111111D1D2G1G2G3G400 01 11 10G3G4G1G200011110000111100001111000 01

15、11 10G3G4G1G1G2G1G21111111111111111D3D4G1G2G3G400 01 11 10G3G4G1G2G3G400 01 11 100001111000011110G1G2G3G1G2G3G1G2G3G1G2G3G1G2G3G4TGEnEnA ABP-MOSN-MOS分析：分析：ABYABY=(AB)(A+B)=AB(A+B)=AB 1En AYBCDEnABCDOut00110Hi-z01110Hi-z1001101100011A YEN With NOR gate control With NAND gate controlAEnfEnAFEnA YBEnA

16、Y BEn LABEn YABBUSEn1En2EniData1Data2Data-i4000系列系列74xx24074HC24074LS126EnAYAYEnAYAYEnEnEnEnEn 1.邏輯電平和噪聲容限邏輯電平和噪聲容限 (Logic Level & Noise Margin.) 2. CMOSCMOS邏輯系列的電路性能邏輯系列的電路性能 ( (Circuit Behavior of CMOS Logic family.) 3.扇入扇入/ /扇出能力扇出能力( (fanin/fanout) 4.不使用輸入端的處理不使用輸入端的處理(Unsed Inputs.)Vin0VoVIHmin

17、VILmaxVOHminVOLmax0vVDD0.7VDD0.3VDDNoise MarginNoise MarginNoise MarginVDDRUPRnRdownVOLmaxVDDRpRdownRUPSinking CurrentSource currentVOHminIOHmaxIOLmaxSpSnBUSCMOS Fo=10Fo=10 1.Drining light-emitting diodes (LEDS) 2. performing Wiring Logic 3.Driving multi-source buses ABfVDDRupABFRupABABOpen drainT T

18、1 1T T2 2F F上拉電阻上拉電阻R RUPUP的要求：的要求：.R.RUPUP要盡可能地小；要盡可能地?。? .從低電平跳到高電平時(shí)間常數(shù)最?。ㄉ仙龝r(shí)間）從低電平跳到高電平時(shí)間常數(shù)最?。ㄉ仙龝r(shí)間）；CC40107 漏極開(kāi)路輸出的漏極開(kāi)路輸出的 NAND GateNAND GateABY YR RupV ddf fABCDR RupupCDABF= = AB+CDILED=10maRupLEDABVOLmax=0.37IVVVLEDLEDOLccRup5V5V電源電壓情況下負(fù)載電流典型值電源電壓情況下負(fù)載電流典型值CMOSCMOS負(fù)載負(fù)載TTLTTL負(fù)載負(fù)載I IOLmaxOLmaxV VOLmaxOLmaxI IOHmaxOHmaxV VOHminOHmin0.020.02（2020UAUA）0.1V0.1V0.020.02（20uA20uA）4.4V4.4V4.04.0（MAMA）0.33V0.33V4.04.03.84V3.84V 3.6.1 3.6.1 Diode & Diode Logic gateDiode & Diode Logic gate 3.6.2 3.6.2 TTL NAND & NOR GateTTL NAND & NOR Gate 1.Semiconducter DiodeNPERPN JunctionERwR+-Ud返回返回返回返