EDA實現(xiàn)電子琴的程序

1、精選文檔實驗十五 電子琴設(shè)計一、 音名與頻率的關(guān)系：音樂上的十二平均律規(guī)定：每兩個八度音之間的頻率相差一倍。在這兩個八度音之間，分成十二個半音，每兩個相鄰伴音的頻率比為12Ö2。另外還規(guī)定，音名A的頻率為440Hz。音名B到C、E到F之間為半音，其余為全音。這樣，可計算得從A（簡譜的低音6）到a1（簡譜的高音6）之間每個音名的頻率為：A（6）：440Hza（6）：880Hza1（6）：1760HzB（7）：493.88Hzb（7）：987.76Hzc（1）：523.25Hzc1（1）：1046.50Hz d（2）：587.33Hzd1（2）：1174.66Hze（3）：659.25H

2、ze1（3）：1318.51Hzf（4）：698.46Hzf1（4）：1396.92Hzg（5）：783.99Hzg1（5）：1567.98Hz二、設(shè)計要求：設(shè)計一個電子琴，要求能演奏音名A到a1之間的全部音階。按下一個鍵，則演奏該音名，并用數(shù)碼管顯示音名，用發(fā)光二極管指示高、中、低音。三、設(shè)計提示：本實驗由鍵盤編碼，音頻輸出譯碼器、分頻器組成。取10MHz信號作為基準(zhǔn)。以基準(zhǔn)頻率除以上述頻率，可得各音名頻率的分頻系數(shù)。注意，為了減少輸出的偶次諧波成分，最后輸出應(yīng)為對稱方波。音頻輸出譯碼器實質(zhì)上是一個多路選擇器，根據(jù)鍵盤編碼的輸出，選擇音階發(fā)生器的不同的預(yù)置數(shù)，分頻后輸出音頻。分頻器可以為加法

3、計數(shù)器，以可以為減法計數(shù)器，計算預(yù)置數(shù)時稍有不同，應(yīng)加以注意。另外，應(yīng)根據(jù)基準(zhǔn)頻率和輸出頻率，來確定計數(shù)器的位數(shù)。設(shè)計框圖如下圖所示：按鍵編碼預(yù)置數(shù)選擇可預(yù)置計數(shù)器T觸發(fā)器（二分頻）掃描時鐘按鍵輸入鍵碼10MHz時鐘音頻輸出預(yù)置數(shù)譯碼器顯示輸出電子琴框圖四、實驗步驟1、啟動ISE集成開發(fā)環(huán)境，創(chuàng)建工程并輸入設(shè)計源文件。2、對設(shè)計進(jìn)行時序仿真，分析設(shè)計的正確性。3、鎖定引腳，完成設(shè)計實現(xiàn)過程。并在實驗箱上連線，利用iMPACT進(jìn)行程序下載。4、在實驗箱上驗證電子琴的功能，觀察并記錄實驗結(jié)果.五、實驗報告1.music的VHDL 源程序：library ieee;use ieee.std_logi

4、c_1164.all;entity music isport(kin: std_logic_vector(0 to 15); spk_out: out std_logic; led_out: out std_logic_vector(6 downto 0); index: out std_logic_vector(2 downto 0); clk: in std_logic);end music;architecture stru of music iscomponent tonetab port( index : in INTEGER range 0 to 15; tone : out IN

5、TEGER range 0 to 16#3fff#; code : out INTEGER range 0 to 15; high : out STD_LOGIC_VECTOR(2 DOWNTO 0) );end component;component tonegen port( clk : in STD_LOGIC; tone : in integer range 0 to 16#3fff#; spks : out STD_LOGIC );end component;component hex2led port( hex : in integer range 0 to 15; led : o

6、ut STD_LOGIC_VECTOR(6 downto 0) );end component;component keybord port( kin : in STD_LOGIC_VECTOR(0 to 15);kout : out INTEGER range 0 to 15 );end component;signal kout: integer range 0 to 15;signal tone: INTEGER range 0 to 16#3fff#;signal digit: integer range 0 to 15;begin u1: keybord port map (kin=

7、>kin,kout=>kout); u2: tonetab port map (index=>kout,tone=>tone,code=>digit,high=>index); u3: tonegen port map (clk=>clk,tone=>tone,spks=>spk_out); u4: hex2led port map (hex=>digit,led=>led_out);end stru;2. hex2led的VHDL 源程序 library IEEE;use IEEE.STD_LOGIC_1164.all;ent

8、ity hex2led is port( hex : in integer range 0 to 15; led : out STD_LOGIC_VECTOR(6 downto 0) );end hex2led;architecture rtl of hex2led issignal data : std_logic_vector(6 downto 0);beginled<=not data; with hex select data<= "1111001" when 1, -1 "0100100" when 2, -2 "0110

9、000" when 3, -3 "0011001" when 4, -4 "0010010" when 5, -5 "0000010" when 6, -6 "1111000" when 7, -7 "0000000" when 8, -8 "0010000" when 9, -9 "0001000" when 10, -A "0000011" when 11, -b "1000110" when 12,

10、-C "0100001" when 13, -d "0000110" when 14, -E "0001110" when 15, -F "1000000" when others; -0end rtl;3. keybord 的VHDL 源程序 library IEEE;use IEEE.STD_LOGIC_1164.all;entity keybord is port( kin : in STD_LOGIC_VECTOR(0 to 15);kout : out INTEGER range 0 to 15 );en

11、d keybord;architecture rtl of keybord issignal data:std_logic_vector(0 to 15);begindata<=kin;process(data)beginif data(0)='0' then kout<=0;elsif data(1)='0' then kout<=1;elsif data(2)='0' then kout<=2;elsif data(3)='0' then kout<=3;elsif data(4)='0&

12、#39; then kout<=4;elsif data(5)='0' then kout<=5;elsif data(6)='0' then kout<=6;elsif data(7)='0' then kout<=7;elsif data(8)='0' then kout<=8;elsif data(9)='0' then kout<=9;elsif data(10)='0' then kout<=10;elsif data(11)='0'

13、; then kout<=11;elsif data(12)='0' then kout<=12;elsif data(13)='0' then kout<=13;elsif data(14)='0' then kout<=14;elsif data(15)='0' then kout<=15;else NULL;end if;end process;end rtl;4. tonegen的VHDL源程序 library IEEE;use IEEE.STD_LOGIC_1164.all;entity t

14、onegen is port( clk : in STD_LOGIC; tone : in integer range 0 to 16#3fff#; spks : out STD_LOGIC );end tonegen;architecture rtl of tonegen issignal fullspks:std_logic;begingenspks:process(clk,tone)variable count14: integer range 0 to 16#3fff#;-std_logic_vector(0 to 13);beginif clk'event and clk=&

15、#39;1' thenif count14=16#3fff# then -"111111111111111" thencount14:=tone;fullspks<='1'elsecount14:=count14+1;fullspks<='0'end if;end if;end process;delayspks:process(fullspks)variable count2:std_logic;beginif fullspks'event and fullspks='1' thencount2:

16、=not count2;end if;spks<=count2;end process;end rtl;5. tonetab 的VHDL源程序library IEEE;use IEEE.STD_LOGIC_1164.all;entity tonetab is port( index : in INTEGER range 0 to 15; tone : out INTEGER range 0 to 16#3fff#; code : out INTEGER range 0 to 15; high : out STD_LOGIC_VECTOR(2 DOWNTO 0) );end tonetab

17、;architecture rtl of tonetab isbeginprocess(index)begincase index iswhen 0 =>tone<=5021;code<=6;high<="100"when 1 =>tone<=6262;code<=7;high<="100"when 2 =>tone<=6829;code<=1;high<="010"when 3 =>tone<=7872;code<=2;high<=&qu

18、ot;010"when 4 =>tone<=8801;code<=3;high<="010"when 5 =>tone<=9226;code<=4;high<="010"when 6 =>tone<=10007;code<=5;high<="010"when 7 =>tone<=10703;code<=6;high<="010"when 8 =>tone<=11323;code<=7;high

19、<="010"when 9 =>tone<=11607;code<=1;high<="001"when 10 =>tone<=12129;code<=2;high<="001"when 11 =>tone<=12593;code<=3;high<="001"when 12 =>tone<=12805;code<=4;high<="001"when 13 =>tone<=13196;c

20、ode<=5;high<="001"when 14 =>tone<=13544;code<=6;high<="001"when 15 =>tone<=16383;code<=0;high<="001"when OTHERS=>NULL;end case;end process;end rtl;實驗記錄：1、 設(shè)計記錄表，記錄引腳鎖定與連線情況。ISE軟件實驗箱端口名稱芯片引腳號IO類型編號clkB4InputIO1index<0>F9OutputIO13index<1>E9OutputIO14index<2>D11OutputIO15kin<0>A4InputIO2kin<1>D5InputIO3ki