版權(quán)說(shuō)明：本文檔由用戶提供并上傳，收益歸屬內(nèi)容提供方，若內(nèi)容存在侵權(quán)，請(qǐng)進(jìn)行舉報(bào)或認(rèn)領(lǐng)
文檔簡(jiǎn)介
1、十五計(jì)數(shù)器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY fiveteencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0);END fiveteencout;ARCHITECTURE counter OF fiveteencout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)
2、BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1110") THENcount_int<="0000"ELSEcount_int <= count_int 1;-ELSE- NULL ;-IF (count_int="1001") THEN-count_int<=&quo
3、t;0000"END IF;END IF;END PROCESS;count <= count_int;- IF (reset='0') then-q<="0000"-ELSIF(clk'event and clk='1') THEN-q<=q 1;-IF (q<="1001") then-q<="0000"-END IF;-IF (reset<='1')THEN-q<="00"-ELSIF-wait unt
4、il (clk'event and clk='1');-WAIT UNTIL (clk'EVENT AND clk = '1');-WAIT UNTIL (clock'EVENT AND clock = '1');- q<=q '1'-end if;-count<=q;- WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-cloc
5、k'event and clock='1'-count <= 0;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT riseedge clock = '1'-if (clock'event and clock='1') then-WAIT UNTIL rising_edge(clock);-count <= 1;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT UNTIL cloc
6、k = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-count <= 2;-end if;-end if;-end if;- END PROCESS;END counter;十四計(jì)數(shù)器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY fourteencout ISPORT(clk,reset,enable : IN std_logic; coun
7、t : OUT std_logic_vector(3 downto 0);END fourteencout;ARCHITECTURE counter OF fourteencout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count
8、_int="1101") THENcount_int<="0000"ELSEcount_int <= count_int 1;-ELSE- NULL ;-IF (count_int="1001") THEN-count_int<="0000"END IF;END IF;END PROCESS;count <= count_int;- IF (reset='0') then-q<="0000"-ELSIF(clk'event and clk=&
9、#39;1') THEN-q<=q 1;-IF (q<="1001") then-q<="0000"-END IF;-IF (reset<='1')THEN-q<="00"-ELSIF-wait until (clk'event and clk='1');-WAIT UNTIL (clk'EVENT AND clk = '1');-WAIT UNTIL (clock'EVENT AND clock = '1')
10、;- q<=q '1'-end if;-count<=q;- WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-clock'event and clock='1'-count <= 0;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT riseedge clock = '1'-if (c
11、lock'event and clock='1') then-WAIT UNTIL rising_edge(clock);-count <= 1;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-count <= 2;-end if;-end if;-end if;- END PROC
12、ESS;END counter;十三計(jì)數(shù)器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY thireteencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0);END thireteencout;ARCHITECTURE counter OF thireteencout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGI
13、NPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1100") THENcount_int<="0000"ELSEcount_int <= count_int 1;-ELSE- NULL ;-IF (count_int="1001") THEN
14、-count_int<="0000"END IF;END IF;END PROCESS;count <= count_int;- IF (reset='0') then-q<="0000"-ELSIF(clk'event and clk='1') THEN-q<=q 1;-IF (q<="1001") then-q<="0000"-END IF;-IF (reset<='1')THEN-q<="00&q
15、uot;-ELSIF-wait until (clk'event and clk='1');-WAIT UNTIL (clk'EVENT AND clk = '1');-WAIT UNTIL (clock'EVENT AND clock = '1');- q<=q '1'-end if;-count<=q;- WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL risin
16、g_edge(clock);-clock'event and clock='1'-count <= 0;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT riseedge clock = '1'-if (clock'event and clock='1') then-WAIT UNTIL rising_edge(clock);-count <= 1;-WAIT UNTIL (clock'EVENT AND clock = '1'
17、;);-WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-count <= 2;-end if;-end if;-end if;- END PROCESS;END counter;十二計(jì)數(shù)器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY twelvecout ISPORT(clk,reset,enable : I
18、N std_logic; count : OUT std_logic_vector(3 downto 0);END twelvecout;ARCHITECTURE counter OF twelvecout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1'
19、 THENIF(count_int="1011") THENcount_int<="0000"ELSEcount_int <= count_int 1;-ELSE- NULL ;-IF (count_int="1001") THEN-count_int<="0000"END IF;END IF;END PROCESS;count <= count_int;- IF (reset='0') then-q<="0000"-ELSIF(clk'ev
20、ent and clk='1') THEN-q<=q 1;-IF (q<="1001") then-q<="0000"-END IF;-IF (reset<='1')THEN-q<="00"-ELSIF-wait until (clk'event and clk='1');-WAIT UNTIL (clk'EVENT AND clk = '1');-WAIT UNTIL (clock'EVENT AND clock =
21、 '1');- q<=q '1'-end if;-count<=q;- WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-clock'event and clock='1'-count <= 0;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT riseedge clock = '
22、;1'-if (clock'event and clock='1') then-WAIT UNTIL rising_edge(clock);-count <= 1;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-count <= 2;-end if;-end if;-end
23、if;- END PROCESS;END counter;十一計(jì)數(shù)器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY elevencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0);END elevencout;ARCHITECTURE counter OF elevencout ISSIGNAL count_int:std_logic_vector(0 to 3);
24、BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1010") THENcount_int<="0000"ELSEcount_int <= count_int 1;-ELSE- NULL ;-IF (count_int="1001")
25、THEN-count_int<="0000"END IF;END IF;END PROCESS;count <= count_int;- IF (reset='0') then-q<="0000"-ELSIF(clk'event and clk='1') THEN-q<=q 1;-IF (q<="1001") then-q<="0000"-END IF;-IF (reset<='1')THEN-q<="
26、00"-ELSIF-wait until (clk'event and clk='1');-WAIT UNTIL (clk'EVENT AND clk = '1');-WAIT UNTIL (clock'EVENT AND clock = '1');- q<=q '1'-end if;-count<=q;- WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL r
27、ising_edge(clock);-clock'event and clock='1'-count <= 0;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT riseedge clock = '1'-if (clock'event and clock='1') then-WAIT UNTIL rising_edge(clock);-count <= 1;-WAIT UNTIL (clock'EVENT AND clock = '1
28、');-WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-count <= 2;-end if;-end if;-end if;- END PROCESS;END counter; 十計(jì)數(shù)器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY count ISPORT(clk,reset,enable
29、 : IN std_logic; count : OUT std_logic_vector(3 downto 0);END count;ARCHITECTURE counter OF count ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENI
30、F(count_int="1001") THENcount_int<="0000"ELSEcount_int <= count_int 1;-ELSE- NULL ;-IF (count_int="1001") THEN-count_int<="0000"END IF;END IF;END PROCESS;count <= count_int;- IF (reset='0') then-q<="0000"-ELSIF(clk'event an
31、d clk='1') THEN-q<=q 1;-IF (q<="1001") then-q<="0000"-END IF;-IF (reset<='1')THEN-q<="00"-ELSIF-wait until (clk'event and clk='1');-WAIT UNTIL (clk'EVENT AND clk = '1');-WAIT UNTIL (clock'EVENT AND clock = '
32、1');- q<=q '1'-end if;-count<=q;- WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-clock'event and clock='1'-count <= 0;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT riseedge clock = '1'
33、;-if (clock'event and clock='1') then-WAIT UNTIL rising_edge(clock);-count <= 1;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-count <= 2;-end if;-end if;-end if;- E
34、ND PROCESS;END counter;九計(jì)數(shù)器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY ninecout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0);END ninecout;ARCHITECTURE counter OF ninecout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(
35、clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1000") THENcount_int<="0000"ELSEcount_int <= count_int 1;-ELSE- NULL ;-IF (count_int="1001") THEN-count_in
36、t<="0000"END IF;END IF;END PROCESS;count <= count_int;- IF (reset='0') then-q<="0000"-ELSIF(clk'event and clk='1') THEN-q<=q 1;-IF (q<="1001") then-q<="0000"-END IF;-IF (reset<='1')THEN-q<="00"-ELSI
37、F-wait until (clk'event and clk='1');-WAIT UNTIL (clk'EVENT AND clk = '1');-WAIT UNTIL (clock'EVENT AND clock = '1');- q<=q '1'-end if;-count<=q;- WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(cl
38、ock);-clock'event and clock='1'-count <= 0;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT riseedge clock = '1'-if (clock'event and clock='1') then-WAIT UNTIL rising_edge(clock);-count <= 1;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT
39、UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-count <= 2;-end if;-end if;-end if;- END PROCESS;END counter;八計(jì)數(shù)器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY eightcout ISPORT(clk,reset,enable : IN std_logic
40、; count : OUT std_logic_vector(2 downto 0);END eightcout;ARCHITECTURE counter OF eightcout ISSIGNAL count_int:std_logic_vector(0 to 2);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count
41、_int="111") THENcount_int<="000"ELSEcount_int <= count_int 1;-ELSE- NULL ;-IF (count_int="1001") THEN-count_int<="0000"END IF;END IF;END PROCESS;count <= count_int;- IF (reset='0') then-q<="0000"-ELSIF(clk'event and clk=
42、9;1') THEN-q<=q 1;-IF (q<="1001") then-q<="0000"-END IF;-IF (reset<='1')THEN-q<="00"-ELSIF-wait until (clk'event and clk='1');-WAIT UNTIL (clk'EVENT AND clk = '1');-WAIT UNTIL (clock'EVENT AND clock = '1');-
43、 q<=q '1'-end if;-count<=q;- WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-clock'event and clock='1'-count <= 0;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT riseedge clock = '1'-if (clo
44、ck'event and clock='1') then-WAIT UNTIL rising_edge(clock);-count <= 1;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-count <= 2;-end if;-end if;-end if;- END PROCES
45、S;END counter;六計(jì)數(shù)器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY sixcout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(2 downto 0);END sixcout;ARCHITECTURE counter OF sixcout ISSIGNAL count_int:std_logic_vector(0 to 2);BEGINPROCESS(clk,reset)BE
46、GINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="101") THENcount_int<="000"ELSEcount_int <= count_int 1;-ELSE- NULL ;-IF (count_int="1001") THEN-count_int<="00
47、00"END IF;END IF;END PROCESS;count <= count_int;- IF (reset='0') then-q<="0000"-ELSIF(clk'event and clk='1') THEN-q<=q 1;-IF (q<="1001") then-q<="0000"-END IF;-IF (reset<='1')THEN-q<="00"-ELSIF-wait until (
48、clk'event and clk='1');-WAIT UNTIL (clk'EVENT AND clk = '1');-WAIT UNTIL (clock'EVENT AND clock = '1');- q<=q '1'-end if;-count<=q;- WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-clock
49、9;event and clock='1'-count <= 0;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT riseedge clock = '1'-if (clock'event and clock='1') then-WAIT UNTIL rising_edge(clock);-count <= 1;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-count <= 2;-end if;-end if;-end if;- END PROCESS;END
溫馨提示
- 1. 本站所有資源如無(wú)特殊說(shuō)明，都需要本地電腦安裝OFFICE2007和PDF閱讀器。圖紙軟件為CAD,CAXA,PROE,UG,SolidWorks等.壓縮文件請(qǐng)下載最新的WinRAR軟件解壓。
- 2. 本站的文檔不包含任何第三方提供的附件圖紙等，如果需要附件，請(qǐng)聯(lián)系上傳者。文件的所有權(quán)益歸上傳用戶所有。
- 3. 本站RAR壓縮包中若帶圖紙，網(wǎng)頁(yè)內(nèi)容里面會(huì)有圖紙預(yù)覽，若沒(méi)有圖紙預(yù)覽就沒(méi)有圖紙。
- 4. 未經(jīng)權(quán)益所有人同意不得將文件中的內(nèi)容挪作商業(yè)或盈利用途。
- 5. 人人文庫(kù)網(wǎng)僅提供信息存儲(chǔ)空間，僅對(duì)用戶上傳內(nèi)容的表現(xiàn)方式做保護(hù)處理，對(duì)用戶上傳分享的文檔內(nèi)容本身不做任何修改或編輯，并不能對(duì)任何下載內(nèi)容負(fù)責(zé)。
- 6. 下載文件中如有侵權(quán)或不適當(dāng)內(nèi)容，請(qǐng)與我們聯(lián)系，我們立即糾正。
- 7. 本站不保證下載資源的準(zhǔn)確性、安全性和完整性, 同時(shí)也不承擔(dān)用戶因使用這些下載資源對(duì)自己和他人造成任何形式的傷害或損失。
最新文檔
- 公司組織建黨節(jié)目活動(dòng)方案
- 2025年智能制造與工業(yè)轉(zhuǎn)型相關(guān)知識(shí)考試試卷及答案
- 2025年生物醫(yī)學(xué)工程師職業(yè)資格考試題及答案
- 2025年青少年心理健康教育課程考試試題及答案
- 2025年民俗文化與社會(huì)變遷考試試題及答案
- 2025年就業(yè)指導(dǎo)與職業(yè)規(guī)劃考試試卷及答案
- 2025年婚姻家庭咨詢師職業(yè)資格考試試卷及答案
- 2025年國(guó)際貿(mào)易知識(shí)考試及其答案
- 2025年法律法規(guī)與社會(huì)責(zé)任考試試卷及答案
- 2025護(hù)理科內(nèi)自查分析討論
- 《水火箭制作》課件
- 網(wǎng)絡(luò)安全預(yù)防電信詐騙主題班會(huì)PPT
- 農(nóng)村垃圾清運(yùn)投標(biāo)方案
- 優(yōu)秀物業(yè)管理項(xiàng)目評(píng)選方案
- 貴州大方富民村鎮(zhèn)銀行股份有限公司（籌）招聘上岸提分題庫(kù)3套【500題帶答案含詳解】
- GB/T 5470-2008塑料沖擊法脆化溫度的測(cè)定
- 圖書管理系統(tǒng)畢業(yè)論文參考文獻(xiàn)精選,參考文獻(xiàn)
- 中國(guó)當(dāng)代舊體詩(shī)選讀幻燈片
- 吉林省全省市縣鄉(xiāng)鎮(zhèn)衛(wèi)生院街道社區(qū)衛(wèi)生服務(wù)中心基本公共衛(wèi)生服務(wù)醫(yī)療機(jī)構(gòu)信息名單目錄995家
- 倔強(qiáng)的小紅軍-精講版課件
- 信息隱藏與數(shù)字水印課件(全)全書教學(xué)教程完整版電子教案最全幻燈片
評(píng)論
0/150
提交評(píng)論