計數(shù)顯示電路設(shè)計

1、課程名稱：VHDL數(shù)字系統(tǒng)設(shè)計與測試題 目 計數(shù)顯示電路 學(xué) 院 電子工程學(xué)院 學(xué) 號 1202121273 姓 名 馬澤偉 一 設(shè)計功能和要求要求：設(shè)計一個輸出為3位BCD碼的計數(shù)顯示電路。該計數(shù)顯示電路由三個模塊構(gòu)成：1、十進制計數(shù)器（BCD_CNT）2、七段顯示譯碼器電路（DEC_LED）3、分時總線切換電路（SCAN）。該電路功能為通過對外部一信號脈沖進行計數(shù)，并以十進制進行計數(shù)，計到百位。同時利用數(shù)碼管動態(tài)掃描原理進行三位數(shù)碼管進行顯示出來。二 設(shè)計思路整個設(shè)計分十進制計數(shù)器模塊（BCD_CNT）、分時總線切換電路模塊（SCAN）和七段顯示譯碼器電路模塊（DEC_LED）構(gòu)成?？偟妮?/p>

2、入為十進制計數(shù)器時鐘clk_1k，異步復(fù)位清零信號rst_n，分時總線切換電路時鐘clk_1m。在rst信號為0期間，在每個clk的上升沿計數(shù)器將加1。在每個clk_1k的上升沿將會改變對三個數(shù)碼管的掃描選通。總的輸出為數(shù)碼管選通信號sel（三位），輸出到七段數(shù)碼管的數(shù)據(jù)信號led（七位）。電路原理圖如下：根據(jù)設(shè)計思路，設(shè)計詳細的電路原理圖如下：利用quartus進行綜合生成RTL電路如下圖：頂層模塊邏輯結(jié)構(gòu)圖如下：頂層模塊主要將十進制計數(shù)器、分時總線切換和七段顯示譯碼模塊進行連接搭建。其中從十進制模塊中輸出的data13:0、data23:0、data33:0分別為個、十、百位的BCD碼。分

3、時總線切換的輸出data3:0為其中要顯示的一個BCD碼和位選信號一一對應(yīng)。1.十進制計數(shù)模塊十進制模塊輸入輸出IO口有計數(shù)時鐘輸入sysclk、系統(tǒng)復(fù)位端rst_b、BCD輸出端data和進位端co。當(dāng)計數(shù)時鐘端來一脈沖時，data將會計數(shù)，當(dāng)來10個脈沖時，data端將會清零，并且產(chǎn)生一個進位脈沖信號。如此將三個十進制模塊通過進位端co進行級聯(lián)，則可成為百位BCD計數(shù)器。2.分時總線切換這個模塊時本設(shè)計的重點和難點，分時總線切換經(jīng)過系統(tǒng)時鐘進行分頻得到掃描時鐘，每當(dāng)掃描時鐘上升沿時，進行切換，使得當(dāng)data_sel2:0=”011”,data3:0=data13:0,依次類推。3.七段顯示

4、譯碼將data3:0的BCD碼譯碼成為數(shù)碼管顯示碼，采用共陰極.四：源代碼設(shè)計1.頂層模塊代碼LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY declariation ENTITY display IS PORT ( Global system input sysclk : in STD_LOGIC; rst_b : in STD_LOGIC; tim_clk: in STD_LOGIC; Output ports data_sel : out STD_LOGIC_VECTOR

5、(2 DOWNTO 0); data_ out : out STD_LOGIC_VECTOR(6 DOWNTO 0) ); END ENTITY; Architecture declaritionARCHITECTURE code of display isSignal declarationSIGNAL data1,data2,data3 : STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL temp : STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL co1,co2 : STD_LOGIC;COMPONENT BCD_CNTCOMPONENT

6、BCD_CNT PORT ( Sysclk : IN STD_LOGIC; rst_b : IN STD_LOGIC; dataout: OUT STD_LOGIC_VECTOR (3 DOWNTO 0); co : OUT STD_LOGIC ); END COMPONENT;COMPONENT DEC_LEDCOMPONENT DEC_LED PORT ( data_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0); data_out : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ); END COMPONENT;COMPONENT SCAN

7、COMPONENT SCAN PORT ( sysclk : IN STD_LOGIC; rst_b : IN STD_LOGIC; data1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); data2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); data3 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); data_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); data_sel : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) ); END COMPONENT; BEG

8、IN U1: BCD_CNT PORT MAP (sysclk => tim_clk,rst_b => rst_b,dataout => data1,co => co1); U2: BCD_CNT PORT MAP (sysclk => co1 , rst_b => rst_b,dataout => data2,co => co2); U3: BCD_CNT PORT MAP (sysclk => co2 ，rst_b => rst_b,dataout => data3); U4: SCAN PORT MAP (sysclk =

9、> sysclk , rst_b => rst_b,data1 => data1, data2=>data2, data3 => data3, data_out => temp, data_sel => data_sel); U5: DEC_LED PORT MAP (data_in => temp, data_out => data_out); END code;1. 十進制模塊該模塊完成bcd碼的計數(shù)過程，每當(dāng)系統(tǒng)時鐘的上升沿到來，計數(shù)器的低位加1，滿10進位，依次類推完成計數(shù)功能，復(fù)位信號使計數(shù)器清零。源程序如下：LIBRARY IE

10、EE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;Entity declarationENTITY BCD_CNT IS PORT ( sysclk : IN STD_LOGIC; rst_b : IN STD_LOGIC; dataout: OUT STD_LOGIC_VECTOR (3 DOWNTO 0); co : OUT STD_LOGIC );END BCD_CNT;Architecture declarationARCHITECTURE cnt OF BCD_CNT ISSignal declartio

11、nSIGNAL temp : STD_LOGIC_VECTOR (3 DOWNTO 0); BEGIN PROCESS (sysclk,rst_b) BEGIN IF rst_b = '0' THEN temp <= "0000" ELSIF sysclk'event AND sysclk = '1' THEN IF temp = "1001" THEN temp <= "0000" ELSE temp <= temp + '1' END IF; END IF;

12、 END PROCESS; PROCESS(temp) BEGIN IF temp = "0000" THEN co <= '1' ELSE co <= '0' END IF; END PROCESS; dataout <= temp;END cnt；2.分時總線切換模塊也即數(shù)碼管刷新電路，其實質(zhì)是一個在高頻時鐘控制下的多路數(shù)據(jù)選擇器，在這里為三路數(shù)據(jù)選擇器。源程序如下：LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; En

13、tity declarationENTITY SCAN IS PORT ( Global input ports sysclk : IN STD_LOGIC; rst_b : IN STD_LOGIC; data1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); data2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); data3 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); Output ports data_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); data_sel : OUT ST

14、D_LOGIC_VECTOR(2 DOWNTO 0) ); END ENTITY; Architecture declarationARCHITECTURE code OF SCAN ISSignal declarationSIGNAL count : STD_LOGIC_VECTOR (3 DOWNTO 0);SIGNAL SEL_NUM : STD_LOGIC_VECTOR (1 DOWNTO 0);BEGIN PROCESS(sysclk,rst_b) BEGIN IF rst_b = '0' THEN count <= "0000" ; ELS

15、IF sysclk'event AND sysclk = '1' THEN count <= count + '1' END IF; END PROCESS; PROCESS (count,sysclk,rst_b) BEGIN IF rst_b = '0' OR SEL_NUM = "11" THEN SEL_NUM <= "00" ELSIF sysclk'event AND sysclk = '1' THEN IF count = "0000&qu

16、ot; THEN SEL_NUM <= SEL_NUM + '1' END IF; END IF; END PROCESS; PROCESS (SEL_NUM) BEGIN CASE SEL_NUM IS WHEN "00" => data_sel <= "011" WHEN "01" => data_sel <= "101" WHEN "10" => data_sel <= "110" WHEN OTHERS =&g

17、t; data_sel <= "111" END CASE; END PROCESS; PROCESS (SEL_NUM) BEGIN CASE SEL_NUM IS WHEN "00" => data_out <= DATA1; WHEN "01" => data_out <= DATA2; WHEN "10" => data_out <= DATA3; WHEN OTHERS => data_out <= "0000" END CASE;

18、 END PROCESS; END code; 3.七段顯示譯碼電路模塊根據(jù)七段數(shù)碼管的顯示原理，將bcd碼譯成為數(shù)碼管所能顯示的字符。源程序如下：LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;Entity declaritionENTITY DEC_LED IS PORT ( data_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0); data_out : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ); END ENTITY;Architecture declaritionArchitecture cod

19、e OF DEC_LED IS BEGIN PROCESS(data_in) BEGIN CASE data_in IS WHEN "0000" => data_out <= "1000000" WHEN "0001" => data_out <= "1111001" WHEN "0010" => data_out <= "0100100" WHEN "0011" => data_out <= "0

20、110000" WHEN "0100" => data_out <= "0011001" WHEN "0101" => data_out <= "0010010" WHEN "0110" => data_out <= "0000010" WHEN "0111" => data_out <= "1111000" WHEN "1000" => data_out <= "0000000" WHEN "1001" => data_out <= "0010000" WHEN OTHERS => data_out <= "1111111&