fpga驅動vga接口的vhdl語言實現

1、fpga 驅動 vga 接口的 vhdl 語言實現轉載 來自于基于 FPGA 的嵌入式系統(tǒng)設計我使用 ep2c5的實驗板作過了實驗,沒有問題的,可惜只能顯示彩條,方格。 McMaster University 有一篇介紹 vga 接口協(xié)議的 vhdl 實現介紹 , 可以自己下載 參考。library IEEE;entity vgacore isPort ( clk : in std_logic;reset : in std_logic;md : in std_logic_vector(1 downto 0;hs : out std_logic;vs : out std_logic;r : ou

2、t std_logic_vector(1 downto 0;g : out std_logic_vector(2 downto 0;b : out std_logic_vector(2 downto 0;end vgacore;architecture Behavioral of vgacore issignal sysclk : std_logic;signal hsyncb : std_logic;signal vsyncb : std_logic;signal enable : std_logic;signal hloc : std_logic_vector(9 downto 0;sig

3、nal vloc : std_logic_vector(9 downto 0;signal rgbx,rgby,rgbp,rgb: std_logic_vector(7 downto 0;-定義 VGASIG 元件,產生同步信號進行行、場掃描,即顯示驅動 component vgasigPort (clock : in std_logic;reset : in std_logic;hsyncb : buffer std_logic;vsyncb : out std_logic;enable : out std_logic;Xaddr : out std_logic_vector(9 downt

4、o 0;Yaddr : out std_logic_vector(9 downto 0;end component;-定義 colormap 元件,確定顏色及位置信息component colormapPort (hloc : in std_logic_vector(9 downto 0;vloc : in std_logic_vector(9 downto 0;rgbx : out std_logic_vector(7 downto 0;rgby : out std_logic_vector(7 downto 0;end component;beginrgb(7 <= rgbp(7 a

5、nd enable;rgb(6 <= rgbp(6 and enable;rgb(5 <= rgbp(5 and enable;rgb(4 <= rgbp(4 and enable;rgb(3 <= rgbp(3 and enable;rgb(2 <= rgbp(2 and enable;rgb(1 <= rgbp(1 and enable;rgb(0 <= rgbp(0 and enable;-產生 25Mhz 的像素輸出頻率divclk: process(clk,resetbeginif reset='0' thensysclk &

6、lt;= '0'elsif clk'event and clk='1' thensysclk <= not sysclk;end if;end process;-模式選擇單元:本測試程序我們使用了 4種模式,由 KEY_B2,KEY_B3控制, 當選擇模式 "11" 時,即不按下 B2, B3, VGA 顯示豎彩條;當選擇模式 "00" 時, 即同時按下 B2, B3時, VGA 顯示全黑;當選擇模式 "01" 時,即只按下 B2時, VGA 顯示橫彩條;當選擇模式 "10&qu

7、ot; 時,即只按下 B3時, VGA 時顯示橫豎彩條。 modchoice: process(md,rgbx,rgbybeginif md="11" then rgbp <= rgbx;elsif md="01" then rgbp <= rgby;elsif md="10" then rgbp <= rgbx xor rgby; else rgbp <= "00000000"end if;end process;makesig: vgasig Port map(clock => s

8、ysclk,reset => reset,hsyncb => hsyncb,vsyncb => vsyncb,enable => enable,Xaddr => hloc,Yaddr => vloc;makergb: colormap Port map(hloc => hloc,vloc => vloc,rgbx => rgbx,rgby => rgby;hs <= hsyncb;vs <= vsyncb;r <= rgb(7 downto 6;g <= rgb(5 downto 3;b <= rgb(2

9、 downto 0;end Behavioral;library IEEE;entity vgasig isPort ( clock : in std_logic;reset : in std_logic;hsyncb: buffer std_logic;vsyncb: out std_logic;enable: out std_logic;Xaddr : out std_logic_vector(9 downto 0;Yaddr : out std_logic_vector(9 downto 0;end vgasig;architecture Behavioral of vgasig is-

10、定義相關常量,可參考 VGA 相關工業(yè)標準constant H_PIXELS: INTEGER:=640;constant H_FRONT: INTEGER:=16;constant H_BACK: INTEGER:=48;constant H_SYNCTIME:INTEGER:=96;constant H_PERIOD: INTEGER:= H_SYNCTIME + H_PIXELS + H_FRON T + H_BACK;constant V_LINES: INTEGER:=480;constant V_FRONT: INTEGER:=11;constant V_BACK: INTEGER

11、:=32;constant V_SYNCTIME: INTEGER:=2;constant V_PERIOD: INTEGER:= V_SYNCTIME + V_LINES + V_FRONT + V_BACK;signal hcnt: std_logic_vector(9 downto 0; - 行計數器signal vcnt: std_logic_vector(9 downto 0; - 場計數器begin-產生行計數(記錄每行的點數, H_PERIOD 為行周期計數值。A: process(clock, resetbegin-復位時行計數器清零if reset = '0'

12、 thenhcnt <= (others => '0'elsif (clock'event and clock = '1' then-當行計數到達計數周期時將重置if hcnt < H_PERIOD thenhcnt <= hcnt + 1;elsehcnt <= (others => '0'end if;end if;end process;-產生場記數(記錄每幀中的行數, V_PERIOD為場周期計數值B: process(hsyncb, resetbegin- 復位場計數器清零if reset=&

13、#39;0' thenvcnt <= (others => '0'elsif (hsyncb'event and hsyncb = '1' thenif vcnt < V_PERIOD thenvcnt <= vcnt + 1;elsevcnt <= (others => '0'end if;end if;end process;-產生行同步信號, H_PIXELS為行顯示點數, H_FRONT為前消隱點數, H_S YNCTIME 為行同步點數C: process(clock, resetbe

14、ginif reset = '0' thenhsyncb <= '1'elsif (clock'event and clock = '1' thenif (hcnt >= (H_PIXELS + H_FRONT and hcnt < (H_PIXELS + H_SYNC TIME + H_FRONT thenhsyncb <= '0'elsehsyncb <= '1'end if;end if;end process;-產生場同步信號, V_LINES為場顯示點數, V_FRO

15、NT為前消隱點數, V_SY NCTIME 場同步點數D: process(hsyncb, resetbeginif reset = '0' thenvsyncb <= '1'elsif (hsyncb'event and hsyncb = '1' thenif (vcnt >= (V_LINES + V_FRONT and vcnt < (V_LINES + V_SYNCTI ME + V_FRONT thenvsyncb <= '0'elsevsyncb <= '1'end

16、 if;when "100" => rgbx <= "00111000" when "101" => rgbx <= "11000111" when "110" => rgbx <= "11111000" when "111" => rgbx <= "11111111" when others => rgbx <= "00000000" end case;

17、case vloc(7 downto 5 is when "000" => rgby <= "10101010" when when when when "001" "010" "011" "100" => => => => rgby rgby rgby rgby <= <= <= <= "01010101" "11001110" "00110001" "00101110&qu