電源的反饋設(shè)計(jì)應(yīng)用集錦開關(guān)電源閉環(huán)控制

1、實(shí)戰(zhàn)官方：點(diǎn)擊打開，有問必答）（廣告勿擾100%拒絕水貼，10名瘋狂工程師運(yùn)營的Control Loop CookbookLloyd H. DixonINTRODUCTION:Switching powerKEA(S) KMOD KPWR KLC(S)KFBError amplifier with compensation Pulse width modulatorPower switching topology Output power filterFeedbacks used-loopfeedback to achieve design objectives for line andloa

2、dregulationanddynamicresponse.Fortunately, the switching power plicated, permittingd-loop systems used in s are usually not very com- the use of simple analyticaltechniques to achieve loop stabilization. A simpli- fied version of the Nyquist stability criteria can beAlthough the pulse width modulato

3、r and power switching circuit are really not linear elements, their state-space averaged linear equivalents can be used at frequencies below the switching frequency, fS.used because ugain crossover occurs onlyonce in the gain vs. frequency characteristic. Bode plots provide a simple and powerful met

4、hod of dis- playing and calculating the loop gain parameters (see Appendix B). This paper begins with a quick review of basic control loop theory.Linear Control Loop TheoryAs shown in Figure 1, a power supply feedback loop can be described in terms of small-signal lin- ear equivalent gain blocks. Th

5、e (s) appended to certain gain blocks indicates that the gain varies as a function of frequency.Open-loop andd-loop gain:The open-loop gain, T, is defined as the total gain around the entire feedback loop (whether the loop i ually open, for purpose of measurement,ord, in normal operation).T(s) = KEA

6、 KMOD KPWR KLC KFB (1)d-loop gain, G, defines the output vs.control input relationship, with the loopd:Figure 1. - Feedback Loop5-1Control Loop Cookbook實(shí)戰(zhàn)官方：點(diǎn)擊打開實(shí)戰(zhàn)官方：點(diǎn)擊打開，有問必答）（廣告勿擾100%拒絕水貼，10名瘋狂工程師運(yùn)營的“Gain” elements as shown in Figure 1 need not have the same units for their output and input (such

7、as Volts/Volt). If Fig. 1 is a current mode con- trol loop, “Output” is a current source, and KFB is 1 KFB T 1 + TG(s) =(2)At low frequencies, open-loopgain T is nor-mally very much greater than 1, so thatd-loopmost likely a currense resistor. KFB “gain” isgain G approaches the ideal 1/KFB. At highe

8、r fre- quencies, T diminishes, mostly because of the low-pass filter characteristic KLC(S). The frequencywhere T has diminished to 1 (0dB) is defined as thecrossover frequency, fC. Referring to Eq. 2 and Figure 2, at fC (where T = 1, with associated 90°then expressed in Volts/Amp, G(s) iloop ga

9、inPulse width modulatorKMODhas its gainexpressed as d/V (Duty cycle/Volt). This discrep- ancy in “gain” units is resolved in the next gain block, KPWR, whose characteristic is V/d.Overall open-loop gain T(s) determines howmuch output error results from a disturbance intro- duced at any point in the

10、loop compared to the result if the loop was open. Project the disturbance forward to the output (multiply by the gain between the dis- turbance and the output), then divide by total open-loop gain, T. For example, with no feedback (open loop, constant duty cycle), a 10% change in VIN results in a 10

11、% VOUT change. With the feed-phase lag), thed-loop gain G(s) is 3db down(with 45° phase lag). Thus, the open-loop cross-over frequency is also the frequency”, where G(s) rolls off.d-loop “cornerIn a power supply voltage control loop, G(s) defines the power supply output vs. the reference voltag

12、e. KFB is usually a simple voltage divider. Forexample, if VREF is 2.5 V, a 2:1 divider (KFB = 0.5, G= 2) results in VOUT = 5 Volts. (Refer to Appendix A.) In a two-loop system (as with current-modeback loopd, if T is 100 at the frequency of thecontrol, to be discussed later) thed-loop gaindisturban

13、ce (DC in this example), then theVOUTG(s) of the inner loop is one element of the open- loop gain T(s) of the outer loop.change is only 0.1% (10%/100). Note that the Output accuracy does not depend significantly onopen-loop gain accuracy. In the example above, if Twas 80 instead of 100,VOUTwould cha

14、nge by0.125% (10% ³VIN/80), instead of 0.1%. However, output accuracy does depend directly on the accu- racy of the feedback portion of the control loop, KFB.Alternatively, a disturbance can be projectedback to the sumpoint at the input of the erroramplifier. For example, the 1Volt “valley” vol

15、tage ofthe sawtooth ramp applied to thecompara-tor is effectively a 1VoC offset or “disturbance”.If the E/A gain is 1000, this 1V error is equivalent to a 1mV error in the reference voltage, and trans- lates into the same percentage error at the output.Nyquist Stability Criteria:Referring to Figure

16、2, if the open-loop gain T crosses 1 (0 dB) only once, the system is stable if the phase lag at the crossover frequency, fC, is lessthan 180° (in addition to the normal 180° phaseshift associated with any negative feedback sys- tem). Let us define the term “phase lag” to refer to any addit

17、ional amount of phase lag beyond the 180° inherent with negative feedback. If the (addi-Figure 2. - Open &d Loop Gain5-2Control Loop Cookbook實(shí)戰(zhàn)官方：點(diǎn)擊打開實(shí)戰(zhàn)官方：點(diǎn)擊打開，有問必答）（廣告勿擾100%拒絕水貼，10名瘋狂工程師運(yùn)營的tional) phase lag at fC exceeds 180°, the loop will oscillate at frequency fC.The “phase margin”

18、 is the amount by which the phase lag at fC is less than the critical value of 180°. The gain margin is the factor by which thebounds, such as when a large step load change occurs. The system will then oscillate and probably never recover. So it is not a good practice to depend upon a condition

19、ally stable loop.How can the loop be stable with 180° phase lag and gain much greater than 1 ?gain is less than u(0 dB) at the frequencywhere the phase lag reaches 180°. If the phase lag at fC is only a few degrees less than 180° (small phase margin), the system will be stable, but wi

20、llexhibit considerable overshoot and ringing at fre- quency fC. A phase margin of 45° provides for good response with a little overshoot, but noringing.Note that Nyquists 180° phase limit applies only at fC. At frequencies below fC, the phase lag is permitted to exceed 180°, even thou

21、gh the open- loop gain is very much greater than 1. The system is then said to be conditionally stable. But if the loop gain temporarily decreases so that fC moves down into the frequency range where the phase lag exceeds 180°, conditional stability is violatedFigure 3 shows the sumpoint voltag

22、evectors at a frequency where the open loop gain is 10, for three different amounts of phase lag around the loop.Figure 3a shows the vector relationship with zero additional phase lag. This condition usually occurs at low frequencies where there are no active poles, so that the gain characteristic s

23、lope is zero (flat). The feedback voltage vFB is 10 timesgreater than error voltage vE and 180° out ofphase. (Note that with an open-loop gain of only 10, the vE magnitude causes vC to be less than vFB. This inequality diminishes with higher loopgain.)Figure 3b shows the vector relationship wit

24、h a gain of 10 but at a frequency where one pole is active, resulting in 1 gain slope and 90° phaseand the loop becomes unstable. Thiually doesoccur whenever the system runs into large signalFigure 3. - Vector Diagrams - Gain = 105-3Control Loop Cookbook實(shí)戰(zhàn)官方：點(diǎn)擊打開實(shí)戰(zhàn)官方：點(diǎn)擊打開，有問必答）（廣告勿擾100%拒絕水貼，10名

25、瘋狂工程師運(yùn)營的lag. Feedback voltage vFB is 10 times greater than vE, but lags by 270°. Note that vE now causes very little inequality between vC and vFB because of its phase. This situation is perfectly stable. With vC = 1 V and open-loop gain of 10 with 90 ° phase lag,only this outcome is possi

26、ble.In Figure 3c, two poles are active at the fre- quency where the gain is 10, resulting in 2 gain slope and 180° additional phase lag. Feedback voltage vFB is now in-phase with vE and 10 timesgreater. Our intuition tells us that this should be arunaway situation. But intuition is wrong, when

27、our thinking is restricted to this one frequency. The vector relationships in Fig. 3c are perfectly stable. They are locked in to each other. This is the only way they can exist, under the defined conditions. Note that vE now causes vFB to be greater than vC.This does not signify instability in fact

28、, if the gainis increased further, vFB becomes smaller, reduc- ing the error without becoWhy does oscillation occu the open loop gain equals 1 ?The vectors of Figure 4a show dition that exists when the gain slopepasses through the crossover frequency. gle active pole results in 90° phase lag. F

29、eevoltage vFB is equal to vE, but lags by 270°. Aga this is the only possible relationship between thesevectors under the conditions defined. Note that vFB, which represents the output, lags control v age vC by 45° (plus 180° negative feedbthe magnitude is down 3dB to .707Fig. 3). Thi

30、s represents theat the open loop crossover frequency, as shown in Fig. 2.The vector diagram for a 2 gain slope at fC where open-loop gain equals 1 cannot be drawn,as it is unstable. Figure 4b shows the vectors at a gain of 1.2, instead. With a 2 slope, vE and vFB are in-phase. With a control voltage

31、 vC of 1V, a feedback voltage of 6 V with an error voltage of 5 V is required to resolve the vector diagram. As loop gain approaches 1, it can be seenvC must become zero, or vE andis 1. The system is definitely unstable.How to design a stable loop:The first step in the design of a stable, high per-

32、formance feedback loop is to define the gain/phase characteristic of each of the known loop elements (usually everything except the error amplifier, KEA). Then, the characteristic of the remaining elements (KEA) is tailored to complement the combined characteristics of the other elements in a way th

33、at will meet the overall loop stability criteria while achieving the highest possible loop gain and band- width.In a switching power supply, the loop elements which actually handle the power are mostly defined by the parameters of the application. However, many options do exist, and they should be e

34、xplored. (Design experience helps to narrow down the list of possible options.) Bode plots (Appendix B) are used to display the overall char- acteristics of all of the loop elements except KEAquire-the loop is characteristic isor the entire loop. The teristic (Appendix B) is thenthe difference betwe

35、en the Bode e overall loop goal and the plot of thewn loop elements without KEA.Limitations on crossover frequency:infinite.Thus, thebecomes infinite, even though the open-loop gainFigure 4. Vector Relationships at Crossover5-4Control Loop Cookbook實(shí)戰(zhàn)官方：點(diǎn)擊打開實(shí)戰(zhàn)官方：點(diǎn)擊打開，有問必答）（廣告勿擾100%拒絕水貼，10名瘋狂工程師運(yùn)營的Ach

36、ieving a high fC is a worthwhile objective because the system can respond more rapidly to minimize the effects of high frequency and tran-sient disturbances. In a purely linear feedback loop, fC is limited by cumulative phase lags in var- ious system elements. These phase lags inevitablyincrease wit

37、h frequency in a manner that often varies unpredictably. Compensation becomes impossible, forcing the designer to set fC at a fre-quency where the phase lags are still manageable.In switching power supply loops, an additional important limitation occurs. Sampling delays inher- ent in any switched sy

38、stem introduce additional phase lags that force the crossover frequency to be well below the switching frequency. This will be discussed later.Transient Response:Transient behavior, in the time domain, is pre- dictably related to the shape of the loop frequency domain characteristics as shown in the

39、 Bode plot.A power supply can function without the help of a feedback loop. The duty cycle could be adjusted manually to the value that would provide thecharacteristic, in the frequency domain, with the transient response in the time domain. For exam- ple, the initial slope of the transient response

40、 to a step change is directly related to the crossover fre- quency.The simple single pole characteristic of Fig. 5a has an exponential characteristic with a time con- stant equal to 1/2pfC, as shown in Figure 5b. In responding to a step change, the initial slope wouldreach the final value in exactly

41、 one time constant (16msec in this example), but like any exponential, it falls away to 63% of the final value at 1 time con-desiredVOUT.But without feedback, even smallchanges in VIN or IOUT (the usual disturbances ina power supply application) would sendVOUTcareening out of spec. With a functional

42、 feedback loop, when an ac disturbance at a specific fre-quency is introduced, the open-loop gain magnitude at the frequency of the disturbance defines how much the output disturbance is reduced compared to what would have occurred without feedback.Figure 5a is the Bode plot of a loop having the gai

43、n characteristic of a single pole (1 slope, 20dB/decade). A crossover frequency of 10kHz is shown, with the open-loop gain rising to 1000 at 10Hz. The gain shown at each frequency indicates the amount by which the feedback loop will reduce a disturbance at that frequency.The gain vs. frequency plot

44、can also be used to show the reduction in the Fourier components of a transient disturbance, or how the loop will respond to the Fourier components of a step change in the control signal. Fortunately, Fourier analysis is usu- ally not required to interrelate the Bode plotFigure 5a. Single Pole Chara

45、cteristicFigure 5b. Single Pole Characteristic5-5Control Loop Cookbook實(shí)戰(zhàn)官方：點(diǎn)擊打開實(shí)戰(zhàn)官方：點(diǎn)擊打開，有問必答）（廣告勿擾100%拒絕水貼，10名瘋狂工程師運(yùn)營的stant and reaches 98% (2% error) in 4 time con- stants (64msec). It takes a long time for the error to diminish ultimately to 0.1% because the loop gainfilter capacitor, whose volta

46、ge sags as a result. Ultimately, the output voltage is restored and thecharge deficit loop responds source current t value. However,takes considerable Figure 6b showonly is the charge deup only becaureaches 1000 only for the Fourier below 10Hz.The single pole characteristiccomponentsor final entiond

47、epicted inFigure 5 is extremely conservative. The 1 slope with its 90° phase margin results in the exponential characteristic which takes a long time to achieve good accuracy.Figure 6 shows a less conservative approach which reduces the error much more rapidly. Two active poles provide a 2 slop

48、e below fC raisingthe gain below fC. This improves audio susceptibil-ity at these frequencies, and improves response to the higher frequency Fourier components of a tran- sient disturbance or control signal. As shown in Fig. 6a, the gain reaches 1000 at 300Hz, rather than at 10Hz. Note that at fC, t

49、he 2 gain slopetransitions to a single pole 1 slope. This is neces-sary because if the 2 slope continued above fC, the phase margin would be too small, resulting in severe underdamped oscillations at fC. The transi- tion to a single pole at fC results in an acceptable phase margin of 52°.Figure

50、 6b shows that the initial slope is the same as in Figure 5b, because fC is the same in both cases. But the transient response holds better because the gain rises more rapidly a frequencies below fC. However, this results overshoot, which occurs at .58/fC (58ms example).Although the peak error with

51、exceeds the error at the same ti slope, it subsequently diminis What is more, the overshoot isome situations.For example, in a power supply application with an inner current control loop and an outer volt- age control loop, assume Figure 5b shows the transient response of the current control loop to

52、 a step change in load current at time 0. The load cur- rent rises immediately to the final value, but the source current follows the transient response char- acteristic. Area “A” shows the charge deficit that results. The load draws this deficit from the outpute poles, not but the over-” which canc

53、els mediately, withoutshoot results in a char all or part of the chargeFigure 6b. Two Pole Characteristic5-6Control Loop Cookbook實(shí)戰(zhàn)官方：點(diǎn)擊打開實(shí)戰(zhàn)官方：點(diǎn)擊打開，有問必答）（廣告勿擾100%拒絕水貼，10名瘋狂工程師運(yùn)營的requiring voltage loop intervention.Switching Power Supply LoopsPower Circuit Design:Just as the power supply is often the

54、 step-child in the design of the complete system, the control loop is often the step-child in the design of the power supply. The power handling circuit topology with its associated components is the most signifi- cant portion of the control loop design, causing most of the problems and complexity.

55、The power circuit is usually defined first, attempting to imple- ment system requirements in the most cost- effective way, with little consideration given to con- trol loop closure. The control loop design usually must adapt to a predefined power circuit.Before proceeding with the control loop it is

56、 necessary to examine some of the power circuitcontrolling the output. An output filter averages thepower pulses to obtain a DC output with acceptable ripple.Continuous Current Mode (CCM):This operating mode occurs, by definition, when inductor current flows continuously through- out the switching p

57、eriod. The CCM current waveforms, shown in Figure 8, apply to all three topologies. But, referring to Figure 7, input and out- put currents differ for each topology because of the different locations of the inductor, switch and diode. There are two operational states Switch ON, when it carries the inductor current, or Switch OFF, when the diode carries the inductor current.Under steady-state conditions, inductor volt- age VL must average zero during each switching period. With only two states, a specific