QUARTUSII仿真流程示例

1、QUARTUSII仿真流程示QUARTUSII72時(shí)序仿真流程（以encoder為例）點(diǎn)擊File->new,見女口卜圖:HewXDevice Design Files Other Files |AHDL Include FileBlock Symbol FileChain Description FileHexadecimal (I nt el-Format) FileIn-System Sources and Probes Editor FileLogie Analyzer Interface FileMemory Initialization FileS ignallap II L

2、ogic Analyzer FileSnopsps Design Constraints FileT cl Script FileT ext FileVector Waveform FileOKCancel點(diǎn)擊OK,出現(xiàn)如下圖:4 Quart us II - C:/Byeda/encoder/encoder encoder - I avei OIB1 wfM File Edit View Project Assignments Processing Tools Yiniw Helpc | encoderD色I(xiàn)S I0俸Project NavigatorXEntityI Logic&Cy

3、clone H: EI2C3S7672C6， y encoder9陰愈 encodei.vhdra Masiei lime Bar 9.725 n$ 4 " Pointer:Waveform!.vwf10.25 n$ Interval525 pz Stat:SaneValue at9.73 ns10.0 ns9.725 ns以±運(yùn)迤翼C2 »L健<<1/ 2JI ±1加 H) eQ【chy | 國 Files 如 Design Unts出現(xiàn)如下圖：在name下的空白貝雙擊，encoder.vhdMaster Time Ba匚N-cuno9.7

4、25 ns Pointer:Value at9. 73 nsvwf400 p$Interval:10. 0 ns9.725 ris9.33 ns Start:End:loserX Node ox Dus:7*k點(diǎn)擊Node Finder.按鈕,出現(xiàn)如下圖:將如上圖的Filter設(shè)為Pins： all,點(diǎn)擊list按鈕，出現(xiàn)如下圖:Node FinderNamed:Filter： | Pim: SICustomize.刁7 Include sub entitiesCancelNodes Found:NameT na bl01I 1321H習(xí)H4K5H6K7K wK eHY伯Y¥Sele

5、cted Nodes: NameAssignments I T點(diǎn)擊按鈕，見如下圖:UnaAcignedhUnassignedItUnassignedIrUnassignedIrUnassignedIrUnassignedIrllnassigned Ir Un as$ig ned Ir UnassignedIrUnassignedIrUnassianed C Unassigned C UnoAsigned C Unassigned CNode FinderNamed: pLook in:Nodes Found:NameE nableIl0I l2I網(wǎng) l4I II Y Y0Y1Y2 I Filt

6、er: | Pins: allCustomize.0 Include $ubentiAiesSelected Nodes:sg£.Assignments TNameAssignmentsTUnassignedIrEAlencoderlE nableUnassignedrUnas$ignedIrAlencoderllUnassignedrUnas$ignedIrnAlencoderllfOUnassignedrUnas$ignedIrDA|encoder|l1UnassignedrUnassignedIrUA|encoder|l2UnassignedrUnas$ignedIrDA|en

7、coder|l3UnassignedrUna$ignedIr、IDAlencoderllfAUnassignedrUna$ignedIr。InA|encoder|l5UnassignedrUnassignedIrI » iSAlencoderlUGUnassignedrUnassignedIrUnassignedrUnas$ignedc-IAlencoderf/Unassigned0Unas$igned匚“IAlencoderAfOUnassignednUnasAignedc<< IlAlencoderAnUnassignedVoUnas$igned r43A|encod

8、erf/2Unassigned0點(diǎn)擊OK,見下圖:vhdencoder,M aster T ime B ar:9.725 n$ " Pointer:Waveforml.vwf200 p$Interval:9.53 ns Start:Value at選他9.73 ns10.0 ns9.725 nsEnd:20.0 ns«篩wAMXE9/、矗II鬲面溺蕾z $谷1舅|11|求可圈 竺奇涵瘵涵裔"學(xué)贏爐Ab- c5waveform_ ， rL F9.725 ns A po-n 一er20251053 ns startg725胡II淌濟(jì)i淌話h 待享J1 »奇溺

9、離裔A器人isr巴法 tuOCCJllLl d ： 1 poin$c 2.35T dT 17bOns i u s 帕 - 7.38ns 9 ns 20 - p ns7 A n<e4設(shè)置信號(hào)輸入，點(diǎn)擊I7,右邊信號(hào)輸入部分變藍(lán)，見圖下圖:選擇如圖所小的Overwrite Clock圖標(biāo)£3 File Edit Vi project XssignnentsProcessing Tools Wiaio? HelpD| encoder耳燙去©僭© ®roject Navigator隹 encoder.vhdQ Wavefoml.vwrFiles 茨 enc

10、oder. yJii encoder, wf泡薇SA金 Hie(6)cfv I Files I n5 De?ion Unh出現(xiàn)如下圖:Kanre皿.9.13 :岸0EnableA 0刖 IX 0一，二-I7)Ad 血-I6AO24-I5AO15-I4A 0由-I3AO*7-I2A 0-IlAO1*9LioA 0同;。國YX 02 Ozervrite ClockWW1Master I ime Bar: 9.725 ns ? 、 Pointer"psID 0 ns20.0 ns9.725 ns Jr匚0r0Ops End: I 1.Du325 ps Start:10.05 Interna

11、lClock"orml.vwrTime rangeStArt time: 10IpsjjEnd time: |I.O|U$ jdATime period:?Period:0.0Offset:K.Ruty cycle 肉：)50斗Cancel設(shè)置Time period后點(diǎn)擊OK,見如下圖:存encoder, vhd| 也 Waveforml.vwf1faster Time Bar:9.725 ns ； |； | Pointer:6.05 ns Interval:*3.68 ns Start:Ops End:klValu.Name9.73 :)ps10.0 ns20. 0 ns9.725

12、 ns J吵0EnableA 0矽1JA12i(0X128X0x128x0x12吵2-lTA 11K1A0DA4A0的5A0陟6A0-l5 -l4 - a 0吵8I 網(wǎng)-I 2 A 0吵9-ll "0A 0矽10ihYA0(0<< 1用同樣的方法設(shè)置I6, I5, I4, I3, I2, Il, I0的輸入值,并設(shè)置Enable 的值為1 (H)，見如下圖:NameValu.9.73:20 q)PS1。.小-Y -9.TZ5 ns JEnableAW莎0處1nTA ,fmi Yi3" ftiRniY¥r9RiY M 7 n A21 Y 24AI

13、65; fui Y n I/T171 1n±<LU J A世ILkOUJ人I乙JJ人L乙OJ人 XJ 人L_L。乙人I乙q。人LOJ人U人LX11J0A2-l7A 11iir-l6A 1rIlli，4-I 5A 1 iiir-IAOI-I 3A 1ir-I 2AO iii28-l1JAOr0A9LioA 1ir»10EYA0/ 10117.75 n$ Interval:0 ps End: 1.0 us9.725 n$ 。| ' Pointer:803 n$ Slait:Master Time Bar:保存文件為（與vhd文件名一致）點(diǎn)擊Assignment F

14、的Setting見如下圖:魏encoder, vhdCategory:GeneralFilesLibrariesDevice+ Operating Settings and Conditions+ Compilation Process Settings囪 EDA Tool Settings+ Analysis & Synthesis Settings Filler Sellings 帝 Timing Analysis Settings AsGcmblcrDesign AssistantSignal Tap II Logic AnalyserLogic .Analyzer Interf

15、aceSJ- Simulator SettingsPowerPlay Power Analyzer Settings迅 Waveforml.vwr©Km |Cancel I £ £ :r再點(diǎn)擊SimulatorSettingSr見如卜圖:Settings encoderCategorp:GeneidlFilesLibrariesDevice+ Operatina Settings and Conditions* Compilation Process Setting*i± EDA Tool SoUingo十 Analysis & Synthesi

16、s Sellings+ Fitter Settings + T iming Analysis 5 ettings AssemblerDesign AssistantSignalTap II Logic AnalpzerLogic Analyzer InterfaceSimulator SettingeSimulation VerificationSimulation Output FilesPowerPlay Power Analyzer SettingsOKCancel將 Simulation mode 設(shè)為 Timimg, Simulation input 設(shè)為，見如 F 圖:Category:GeneralFilesLibrariesDevice網(wǎng) Operating S ettings and Conditions+ Compilation Process Settings+ EDA Tool Settings乞 Analysis & Synthesis Settings+ Fitter Settings+ T imin g Analysis S etti