Freescale MPC5634M 32位MCU開發(fā)方案

1、freescale mpc5634m 32位mcu開發(fā)方案 公司的mpc5634m是基于power architecture 的32位,用戶模式100%和power architecture 命令集兼容,工作頻率0 mhz80 mhz ,工作溫度到+150度c,具有低功耗性能,工作4.5 v5.25 v,內(nèi)部穩(wěn)壓器提供3.3v和1.2v用于內(nèi)核和規(guī)律,主要用于氣油引擎管理,摩托車引擎控制,混合動力汽車,熱量表和溫度控制器,can等.本文介紹了mpc5634m主要特性,框圖,trk-mpc5634m低成本開發(fā)系統(tǒng)主要特性,和元件布局圖. this document provides electr

2、ical specifications, pin assignments, and package diagrams for the mpc5634m series of microcontroller units (mcus). for functional characteristics, refer to the mpc5634m microcontroller reference manual.the mpc5634m series microcontrollers are system-on-chip devices that are built on power architect

3、ure technology and:are 100% user-mode compatible with the power architecture instruction setcontain enhancements that improve the architectures fit in embedded applicationsinclude additional instruction support for digital signal processing ()integrate technologies such as an enhanced time processor

4、 unit, enhanced queued analog-to-digital converter,controller area network, and an enhanced modular input-output systemmpc5634m主要特性:operating parameters fully static operation, 0 mhz 80 mhz (plus 2% frequency modulation - 82 mhz) 40 degreec to 150 degreec junction temperature operating range low pow

5、er design less than 400 mw power dissipation (nominal) designed for dynamic power management of core and peripherals software controlled clock gating of peripherals low power stop mode, with all clocks stopped fabricated in 90 nm process 1.2 v internal logic single power supply with 5.0 v -10%/+5% (

6、4.5 v to 5.25 v) with internal regulator to provide 3.3 v and 1.2 v for the core input and output pins with 5.0 v -10%/+5% (4.5 v to 5.25 v) range 35%/65% vdde switch levels (with hysteresis) selectable hysteresis selectable slew rate control nexus pins powered by 3.3 v supply designed with emi redu

7、ction techniques phase-locked loop frequency modulation of system clock frequency on-chip bypass capacitance selectable slew rate and drive strengthhigh performance e200z335 core processor 32-bit power architecture book e programmers model variable length encoding enhancements allows power architect

8、ure instruction set to be optionally encoded in a mixed 16 and 32-bit instructions results in smaller code size single issue, 32-bit power architecture technology compliant cpu in-order execution and retirement precise exception handling branch processing unit dedicated branch address calculation ad

9、der branch acceleration using branch lookahead instruction buffer load/store unit one-cycle load latency fully pipelined big and little endian support misaligned access support zero load-to-use pipeline bubbles thirty-two 64-bit general purpose registers (gprs) memory management unit (mmu) with 16-entry fully-assoc