掃描數(shù)碼顯示器實(shí)驗(yàn)

1、 4.2 掃描數(shù)碼顯示器實(shí)驗(yàn)4.2.1 實(shí)驗(yàn)?zāi)康?. 學(xué)習(xí)狀態(tài)機(jī)的原理及使用 VHDL語(yǔ)言設(shè)計(jì)的方法；2.學(xué)習(xí)復(fù)雜數(shù)學(xué)系統(tǒng)的設(shè)計(jì)方法；3.掌握動(dòng)態(tài)掃描數(shù)碼顯示器的設(shè)計(jì)方法。4.2.2 實(shí)驗(yàn)設(shè)備 PC微機(jī)一臺(tái)，TD-EDA試驗(yàn)箱一臺(tái)，SOPC開發(fā)板一塊。4.2.3 實(shí)驗(yàn)內(nèi)容狀態(tài)機(jī)是一類很重要的時(shí)序電路，是許多數(shù)字電路的核心部件。根據(jù)狀態(tài)機(jī)的輸出方式可以分為Mealy型和Moore型兩種狀態(tài)機(jī)。輸出與狀態(tài)有關(guān)而與輸入無(wú)關(guān)的狀態(tài)機(jī)類型稱為Moore型狀態(tài)機(jī)。輸出與狀態(tài)及輸入皆有關(guān)系的狀態(tài)機(jī)稱為Mealy型狀態(tài)機(jī)。狀態(tài)機(jī)通常包含：說(shuō)明部分、主控時(shí)序進(jìn)程、主控組合進(jìn)程、輔助進(jìn)程幾個(gè)部分。利用狀態(tài)機(jī)進(jìn)行設(shè)

2、計(jì)的步驟如下：1. 分析設(shè)計(jì)要求，列出狀態(tài)機(jī)所有可能的狀態(tài)，并對(duì)每一個(gè)狀態(tài)進(jìn)行狀態(tài)編碼；2. 根據(jù)狀態(tài)轉(zhuǎn)移關(guān)系和輸出函數(shù)畫出狀態(tài)轉(zhuǎn)移圖；3. 由狀態(tài)轉(zhuǎn)移圖，用狀態(tài)機(jī)語(yǔ)句描述狀態(tài)機(jī)。是數(shù)碼管動(dòng)態(tài)掃描顯示的方式主要是為了節(jié)省I/O管腳和內(nèi)部邏輯資源，它利用人的視覺(jué)暫留現(xiàn)象，將6位數(shù)數(shù)碼管分別循環(huán)選通，配合傳送相應(yīng)的要顯示的數(shù)據(jù)，只要掃描的速度足夠快，就可以使人的視覺(jué)感到好像是6位數(shù)碼管的同時(shí)顯示。一般掃描頻率使用1KHz就可以了。本實(shí)驗(yàn)設(shè)計(jì)一個(gè)可以使6位數(shù)碼管動(dòng)態(tài)刷新顯示的掃描電路。分析系統(tǒng)的要求可知此設(shè)計(jì)需要包括6進(jìn)制計(jì)數(shù)器、BCD譯碼器、數(shù)據(jù)選擇多路開關(guān)等多個(gè)小單元模塊。實(shí)驗(yàn)需要設(shè)計(jì)一個(gè)模塊來(lái)

3、為6個(gè)數(shù)碼塊提供要顯示的數(shù)據(jù)，設(shè)計(jì)一個(gè)六位數(shù)123456從左向右移動(dòng)的方式，直到最高一位移出最右邊數(shù)碼塊后，最低位6再?gòu)淖钭竺鏀?shù)碼塊移進(jìn)，從而實(shí)現(xiàn)循環(huán)移動(dòng)。4.2.4 實(shí)驗(yàn)步驟1.運(yùn)行Quartus 軟件，建立新工程，工程名稱及頂層文件名稱為SCANLED。2.選擇FileNew菜單，創(chuàng)建圖形設(shè)計(jì)文件，在圖形編輯器界面中選擇Block Tool工具按鈕，分別新建DAT、MULX、BCD_LED子模塊，完成模塊的定義及模塊之間的連接，完成如圖4-2-1所示的數(shù)碼掃描顯示器頂層設(shè)計(jì)電路圖。3.將創(chuàng)建的圖形設(shè)計(jì)文件保存為SCANLED.BDF作為整個(gè)設(shè)計(jì)的頂層文件。4.右鍵單擊DATA模塊，在彈出的

4、菜單中選擇“Create Design File from selected Block”，生成名稱為DATA.VHD的VHDL設(shè)計(jì)文件。5.在文本編輯器界面中編寫程序，文件保存為DATA.VHD。源程序如下：LIBRARY LEEE;USE LEEE.STD_LOGIC_1164.ALL;ENTITY DATA IS PORT(CLK:IN STD_LOGIC; CLR:IN STD_LOGIC; AH:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); AL:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); BL:OUT STD_LOGIC_VECTOR(

5、3 DOWNTO 0); BH:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CL:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CH:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);BND DATA;ARCHITECTURE DATA_BEHAV OF DATA IS TYPE STATE IS(ST0,ST1,ST2,ST3,ST4,ST5,ST6,ST7,ST8,ST9,ST10,ST11); SIGNAL CURRENT_STATE,NEXT_STATE:STATE; SIGNAL DAL,DAH,DBL,DBH,DCL,D

6、CH:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN REG:PROCESS(CLR,CLK)BEGIN IF CLR=1 THEN CURRENT_STATE<=ST0;ELSIF CLK=1AND CLKEVENT THEN CURRENT_STATE<=NEXT_STATE; END IF; END PROCESS; COM:PROCESS(CURRENT_STATE,DAL,DAH,DBL,DBH,DCL,DCH) BEGIN WHEN STO=> DAL<=”0110”;DAH<=”0101”;DBL<=”0100”;DBH&

7、lt;=”0011”;DCL<=”0010”;DCH<=”0001”;NEXT_STATE<=ST1;WHEN ST1=> DAL<=”0101”;DAH<=”0100”;DBL<=”0011”;DBH<=”0010”;DCL<=”0001”;DCH<=”1111”;NEXT_STATE<=ST2;WHEN ST2=> DAL<=”0100”;DAH<=”0011”;DBL<=”0010”;DBH<=”0001”;DCL<=”1111”;DCH<=”1111”;NEXT_STATE<

8、;=ST3;WHEN ST3=> DAL<=”0011”;DAH<=”0010”;DBL<=”0001”;DBH<=”1111”;DCL<=”1111”;DCH<=”1111”;NEXT_STATE<=ST4;WHEN ST4=> DAL<=”0010”;DAH<=”0001”;DBL<=”1111”;DBH<=”1111”;DCL<=”1111”;DCH<=”1111”;NEXT_STATE<=ST5;WHEN ST5=> DAL<=”0001”;DAH<=”1111”;DBL&

9、lt;=”1111”;DBH<=”1111”;DCL<=”1111”;DCH<=”1111”;NEXT_STATE<=ST6;WHEN ST6=> DAL<=”1111”;DAH<=”1111”;DBL<=”1111”;DBH<=”1111”;DCL<=”1111”;DCH<=”1111”;NEXT_STATE<=ST7;WHEN ST7=> DAL<=”1111”;DAH<=”1111”;DBL<=”1111”;DBH<=”1111”;DCL<=”1111”;DCH<=”0110

10、”;NEXT_STATE<=ST8;WHEN ST8=> DAL<=”1111”;DAH<=”1111”;DBL<=”1111”;DBH<=”1111”;DCL<=”0110”;DCH<=”0101”;NEXT_STATE<=ST9;WHEN ST9=> DAL<=”1111”;DAH<=”1111”;DBL<=”1111”;DBH<=”0110”;DCL<=”0101”;DCH<=”0100”;NEXT_STATE<=ST10;WHEN ST10=> DAL<=”1111”;DA

11、H<=”1111”;DBL<=”0110”;DBH<=”0101”;DCL<=”0100”;DCH<=”0011”;NEXT_STATE<=ST11;WHEN ST11=> DAL<=”1111”;DAH<=”0110”;DBL<=”0101”;DBH<=”0100”;DCL<=”0011”;DCH<=”0010”;NEXT_STATE<=ST0; WHEN OTHERS=> DAL<=”0000”;DAH<=”0000”;DBL<=”0000”;DBH<=”0000”;DCL&l

12、t;=”0000”; DCH<=”0000”;NEXT_STATE<=ST0; END CASE; END PROCESS; AL<=DAL;AH<=DAH; BL<=DBL;BH<=DBH; CL<=DCL;CH<=DCH; END DATA_BEHAV;6 右鍵單擊MULX模塊，在彈出的菜單中選擇”Create Design File from Selected Block”, 生成名稱為MULX.VHD的VHDL設(shè)計(jì)文件。7. 在文本編譯器界面中編寫程序，文件保存為MULX.VHD。源程序如下： LIBRARY LEEE;USE LEEE.

13、STD_LOGIC_1164.ALL;ENTITY MULX ISPORT( AL:IN STD_LOGIC_VECTOR(3 DOWNTO 0);AH:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);BL:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);BH:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CL：IN STD_LOGIC_VECTOR（3 DOWNTO 0）; CH：IN STD_LOGIC_VECTOR（3 DOWNTO 0）; CLK1:IN STD_LOGIC; BCD: OUT STD_LOGIC_VECTOR（

14、3 DOWNTO 0）; SEG : OUT STD_LOGIC_VECTOR（3 DOWNTO 0）; END MULX; ARCHITECTURE MULX_BEHAV OF MULXIS TYPE STATE IS(ST0,ST1,ST2,ST3,ST4,ST5); SIGNAL CURRENT_STATE,NEXT_STATE:STATE;BEGIN SS1:PROCESS(CLK1) BEGIN IF(CLK1=1 AND CLK1EVENT)THEN CURRENT_STATE<=NEXT_STATE; END IF; END PROCESS;SS2:PROCESS(CURR

15、ENT_STATE) BEGIN CASE CURRENT_STATE IS WHEN ST0=>BCD<=AL ;SEG<=”011111”;NEXT_STATE<=ST1; WHEN ST1=>BCD<=AH;SEG<=”101111”;NEXT_STATE<=ST2; WHEN ST2=>BCD<=BL ;SEG<=”110111”;NEXT_STATE<=ST3; WHEN ST3=>BCD<=BH;SEG<=”111011”;NEXT_STATE<=ST4; WHEN ST4=>BC

16、D<=CL ;SEG<=”111101”;NEXT_STATE<=ST5; WHEN ST5=>BCD<=CH;SEG<=”111110”;NEXT_STATE<=ST0; END CASE; END PROCCESS;END MULX_BEHAV;8. 右鍵單擊 BCD_LED 模塊，在彈出的菜單中選擇“Create Design File from Selected Block”，生成名稱為BCD_LED.VHD 的VHDL設(shè)計(jì)文件。9.在文本編輯器界面中編寫程序，文件保存為BCD_LED.VHD。源程序如下：LIBRARY IEEE;USE IE

17、EE.STD_LOGIC_1164.ALL;ENTITY BCD_LED IS PORT( BCD:IN STD_LOGIC_VECTOR(3 DOWNTO 0); LED:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END BCD_LED;ARCHITECTURE BCD_LED_BEHV OF BCD_LED ISBEGIN PROCESS(BCD) BEGIN CASE BCD IS -Dpgfedcba WHEN “0000” =>LED<=”00111111”; WHEN “0001” =>LED<=”00000110”; WHEN “0

18、010” =>LED<=”01011011”; WHEN “0011” =>LED<=”01001111”; WHEN “0100” =>LED<=”01100110”; WHEN “0101” =>LED<=”01101101”; WHEN “0110” =>LED<=”01111101”; WHEN “0111” =>LED<=”00000111”; WHEN “1000” =>LED<=”01111111”; WHEN “1001” =>LED<=”01101111”; WHEN OTHERS =>LED<=”00000000”;END CASE;END PROCESS;END BCD_LED_BEHV;10.選擇ToolsCompiler Tool菜單，編譯SCANLED.BDF源文件。編譯無(wú)誤后建立仿真波形文件SCANLED.VWF。11.選擇ToolsSimulator Tool菜單進(jìn)行仿真。分析仿真結(jié)果，仿真正確后選擇AssignmentsAssignment Edito